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`Global Foundaries US v. Godo Kaisha
`Global Ex. 1018
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`Page 1 of 7
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`J}
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`4 >93.J?Z5.1§
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`% ="“"
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`Page 3 of 7
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`U.S. Patent
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`Jan. 20, 1987
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`Sheet 3 of3
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`4,638,347
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`Page40f7 _
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`Page 4 of 7
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`1
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`4,638,347
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`2
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`cal
`the present invention
`leakage across the spacer,
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`provides a discontinuous metal film over the sidewall
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`isolation layer rather than a continuous metal film as
`obtained in accordance with the above discussed tech-
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`nique.
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`Providing a discontinuous film over the sidewall
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`isolation spacer prevents the formation of a continuous
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`silicon diffusion path over the spacer. This prevents the
`formation of a continuous silicide film over the spacer
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`and thereby precludes electrical
`leakage across the
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`spacer after the unreacted metal has been selectively
`etched away.
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`This discontinuous path is created by recessing the
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`sidewall isolation layer so that metal deposited thereon
`would be discontinuous over the isolation region. In
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`particular, the sidewall isolation is fabricated of at least
`two different materials and the composite isolation re-
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`gion is then selectively etched in order to create a recess
`therein.
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`In particular, the present invention is concerned with
`a sidewall isolation structure for field effect transistors
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`which structure comprises a first electrical insulating
`material and a second and different electrical insulating
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`material. The second electrical insulating material is
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`contiguous with and preferably embedded in the first
`V
`insulating material. Moreover,
`the second
`electrical
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`electrical insulating material is etched above or prefera-
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`bly below the surface level of the first electrical insulat-
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`ing material to provide a recess in the sidewall isolation
`structure. This,
`in turn, prevents the formation of a
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`continuous metal film over the sidewall isolation struc-
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`ture.
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`Another aspect of the present invention is a process
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`for preparing sidewall isolation for field effect transis-
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`tors. The process comprises providing a first electrical
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`insulating layer over at least the sidewalls of an electri-
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`cally conductive region. A second and different electri-
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`cal insulating layer is provided adjacent the first electri-
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`cal insulating layer on at least the sidewalls of the con-
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`ductive region.
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`Although the present invention can be practiced with
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`only two layers, it is preferred to provide a third electri-
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`cal insulating layer adjacent the second and different
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`insulating layer on at least the sidewalls. The third elec-
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`trical insulating layer, if provided, can have substan-
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`tially the same or a different etch rate as does the second
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`insulating layer or the first insulating layer. However, it
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`is preferred that such a third layer have an etch rate
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`substantially the same as that of the first electrical insu-
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`lating layer. The layers are then etched whereby the
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`second layer is etched at a rate different than the first
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`layer to thereby provide recesses in the sidewall isola-
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`tion. Preferably the second layer is etched at a rate
`faster than the first layer and third layer, if present,
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`resulting in a recess below the surface level of the first
`and third layers.
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`BRIEF DESCRIPTION OF DRAWINGS
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`FIGS. 1-8 are.cross-sectional views of a simplified
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`field effect transistor in various stages of fabrication
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`according to the present invention.
`BEST AND VARIOUS MODES FOR CARRYING
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`OUT INVENTION
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`For convenience, the discussion of the fabrication
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`steps is directed to the preferred aspect of employing a
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`p-type silicon substrate as the semiconductive substrate
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`and n-type impurities. This leads to the n-channel FET
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`GATE ELECTRODE SIDEWALL ISOLATION
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`SPACER FOR FIELD EFFECT TRANSISTORS
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`This application is a continuation of application Ser.
`No. 447,543, filed Dec. 7, 1982, now abandoned.
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`DESCRIPTION
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`
`5
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`1. Technical Field
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`The present invention is concerned with certain side-
`wall isolation structures for field effect transistors. In
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`particular, the present invention is concerned with a
`sidewall isolation structure for field effect transistors
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`which structure contains a plurality of electrical insulat-
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`ing materials. The present invention is also concerned
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`with a process for fabricating the sidewall
`isolation
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`structure and, particularly, for fabricating a sidewall
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`isolation structure having a plurality of insulating mate-
`rials.
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`2. Background Art
`The metallic type electrical connections to the
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`source, drain, and gate regions of a field effect transistor
`can be achieved by various processes. One such proce-
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`dure involves the selective reaction of a metal such as
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`titanium, cobalt, palladium, or nickel with exposed sili-
`con to obtain self-aligned contacts to the source, drain,
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`and gate regions of the device. Achieving self-align-
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`ment is significant in the fabrication of field effect tran-
`sistors since one of the most crucial steps in preparing
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`FET devices is a lithographic masking step which re-
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`quires high precision in registration (i.e., relative mask-
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`to-mask alignment) and extreme care in execution.
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`With respect to the above procedure for achieving
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`self-alignment of metallic type contacts to the source,
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`drain, and gate regions of a FET device, it is important
`to maintain the electrical isolation of the gate from the
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`source and drain regions. This is accomplished by pro-
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`viding an isolation or electrical insulation layer on the
`sidewalls of the gate (which can be referred to as
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`“spacer”) and between the gate and semiconductor
`substrate. To obtain self-aligned contacts, a metal is
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`deposited over the entire region (the source, drain, gate,
`and over the sidewall isolation between the gate and the
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`source and drain regions). Subsequent to this, the metal
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`is reacted with the available exposed silicon which it
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`contacts to form a metallic silicide. Since the sidewalls
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`are of an isolation material such as an oxide or nitride,
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`reaction between the metal and the sidewall should not
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`occur to form silicide. Subsequent to this, the unreacted
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`metal on the sidewall isolation can then be selectively
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`etched away.
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`However, it has been observed in attempting to pre-
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`pare devices by the procedure discussed above, that
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`although free silicon is not present on the sidewalls,
`nonetheless, metallic silicides have formed thereon.
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`in turn, causes electrical
`leakage between the
`This,
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`source, drain, and gate areas across the spacer paths. It
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`is not entirely understood as to what causes the silicide
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`formation on the sidewalls, but it is believed that possi-
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`bly silicon is diffused through the metal on the sidewall
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`due to the temperature of the silicide formation and this
`leads to silicide formation there. This is particularly
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`noticeable when employing metals such as cobalt and
`titanium to form the silicide.
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`DISCLOSURE OF INVENTION
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`In order to prevent possible diffusion paths on the
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`silicon over the spacer and thereby eliminating electri-
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`65
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`Page 5 of 7
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`Page 5 of 7
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`4
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`Next, a layer 8 of an electrically insulating material,
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`different from the silicon dioxide, is provided over the
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`silicon dioxide. An example of such a material is silicon
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`nitride. Other materials which can be used as layer 7 or
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`layer 8 include oxides such as aluminum oxide and mag-
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`nesium oxide.
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`The silicon nitride can be formed by chemical vapor
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`deposition and is usually about 100 to 1,000 angstroms
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`thick.
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`An additional layer 9 of silicon dioxide is then depos-
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`ited. The silicon dioxide layer is approximately 500 to
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`1,500 angstroms thick and may be formed by chemical
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`vapor deposition.
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`Through vertically directional reactive ion etching,
`silicon dioxide layer 7, silicon nitride layer 8, and silicon
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`oxide layer 9 are etched so that as to obtain the structure
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`shown in FIG. 5. Since the rates of etching of the silicon
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`oxide and silicon nitride employing reactive ion etching
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`are substantially the same, no depressions or recesses
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`are formed in the isolation structure employing the
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`reactive ion etching technique. Typical conditions of
`reactive ion etching include using a CF4 gas at about 25
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`microns of prespure at a gas flow rate of about 40 stan-
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`dard cubic centimeters per minute and employing about
`20 watts of power, which is equivalent to a power den-
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`sity of about 0.073 watts per cmz. These particular pa-
`rameters provide for an etch rate of about 160 ang-
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`stroms per minute.
`0
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`The sidewall spacer so formed is about 2000 A wide
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`at the base. Also, in this process, the source and drain
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`regions are exposed. Source and drain may be formed,
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`for example, by ion-implantation of n-type dopant at
`this stage.
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`Next, the remaining silicon dioxide layer 7, silicon
`nitride layer 8, and silicon dioxide 9 are subjected to a
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`chemical etch to thereby form recess in the sidewall
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`isolation as illustrated in FIG. 6. A typical etch em-
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`ployed is phosphoric acid solution at about 180° C. The
`silicon nitride is etched to a much greater extent than
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`the silicon dioxide in the presence of the phosphoric
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`acid. Accordingly, recess in the sidewall isolation is
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`achieved as illustrated in FIG. 6. Generally, the etch
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`rate ratio of layer 8 to layers 7 and 9 is at least about 10:1
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`and, preferably, at least about 100:1.
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`The etching is carried out for about 2-10 minutes to
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`cause a 200-1000 A recess in the sidewall isolation.
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`Next, a metal
`layer 10, such as cobalt,
`titanium,
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`nickel, and platinum series metals is deposited over the
`structure such as by sputtering or, preferably, evapora-
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`tion. The recesses prevent a continuous metallic film
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`from forming on the sidewalls of the gate, as illustrated
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`in FIG. 7.
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`Next, the metal is reacted with the silicon at elevated
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`temperature such as about 400° to about 800° C. to
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`provide a metallic silicide 11. The preferred metals
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`employed are cobalt and titanium. The temperatures
`employed for the cobalt and titanium are at least about
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`550° C., while those for the platinum type metals are
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`about 400° to about .500“ C.
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`After formation of the silicide, the unreacted metal
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`can be removed from the structure by etching in a mate-
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`rial which will not effect the silicide, but will selectively
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`remove the unreacted metal. For instance, with tita-
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`nium, the etch employed can be a solution of 1:1:5 vol-
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`ume ratio of ammonium hydroxide, hydrogen peroxide,
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`and water (see FIG. 8).
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`What is claimed is:
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`technology. Accordingly, it is understood that a n-type
`substrate and a p-type diffused or implanted dopant
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`impurity can be employed according to the present
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`invention in p-channel FET technology.
`It is understood that when the discussion refers to
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`n-type impurities, the process steps are applicable to
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`p-type impurities and vice versa. Also, when reference
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`is made to impurities of the “first type” and to impurities
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`of a “second type”, it is understood that the “first type”
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`refers to the opposite conductivity. That is, if the “first
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`type” is p, then the “second type” is n. If the “first type”
`is n, then the “second type” is p.
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`Although the fabrication process is described em-
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`ploying the preferred material, polycrystalline silicon,
`other suitable materials can be employed.
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`Referring to FIG. 1, there is shown a p-type silicon
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`substrate 2 having any desired crystal orientation (e.g.,
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`< 100>). Such can be prepared by slicing and polishing
`a p-type boule grown in the presence of a p-type dop-
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`ant, such as boron following conventional crystal
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`growth techniques. Other p-type dopants for silicon
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`include aluminum, gallium, and indium.
`Field oxide isolation 12 can be fabricated by any of
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`the several known procedures including thermal oxida-
`25
`tion of the semiconductor substrate or by well-known
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`vacuum vapor deposition techniques. Furthermore, the
`field oxide 12 may be formed above the semiconductor
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`surface or it may be partially or fully recessed into the
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`semiconductor substrate. An example of one such pro-
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`cedure is the fully recessed oxide isolation technique
`disclosed in U.S. Pat. No. 3,899,363, disclosure of which
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`is incorporated herein by reference.
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`For the purposes of illustration of the procedure of
`the present
`invention, a non-recessed field isolation
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`35
`oxide 12 will be used. The field isolation regions are
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`generally about 4,000 to about 10,000 angstroms thick.
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`The field oxide regions 12 and the regions under which
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`source and drain regions 4 and 5 are formed are delin-
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`eated by employing a lithographic mask. The mask is of
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`a transparent material having opaque portions in a pre-
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`determined pattern. Next, source and drain regions 4
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`and 5 are formed in the p-silicon substrate 2, such as by
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`thermal diffusion or ion-implantation of an impurity of
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`the n-type. Examples of some n-type impurities for
`45
`silicon substrates include arsenic, phosphorus, and anti-
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`mony.
`The field oxide 12 using a photolithographic tech-
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`nique is etched from that area where a thin gate oxide
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`insulator layer 3 is to be subsequently grown.
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`A relatively thin gate insulator layer of silicon diox-
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`ide 3 (see FIG. 2) is grown on or deposited onto the
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`silicon substrate 2. This gate insulator, which is usually
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`about 100 to about 1,000 angstroms thick, can be formed
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`by thermal oxidation of the silicon substrate at about
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`800°—1000° C. in the presence of oxygen.
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`Next, the gate 6 of the FET is deposited and delin-
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`eated by known photolithographic technique. The gate
`6 of the FET is of preferably polycrystalline silicon and
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`is generally doped to the same conductive type as the
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`source and drain.
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`Next, a layer 7, of silicon dioxide is provided over the
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`entire structure including the polycrystalline silicon
`gate 6 (see FIG. 4). This silicon dioxide layer can be
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`grown on or deposited on to the substrate and the gate
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`6. This layer is usually about 500 to about 1,500 ang-
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`stroms thick and can be formed by thermal oxidation of
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`the silicon surface and polycrystalline silicon surface at
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`about 800°—1000° C. in the presence of oxygen.
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`6
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`5. The sidewall isolation structure of claim 1 which
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`further includes a third electrical insulating material
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`adjacent said second and different electrical insulating
`material.
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`6. The sidewall isolation structure of claim 5 wherein
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`said third electrical insulating material has an etch rate
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`different from the etch rate of said second and different
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`electrical insulating material.
`7. The sidewall isolation structure of claim 5 wherein
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`said third electrical insulating material has an etch rate
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`substantially the same as the etch rate of said first elec-
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`trical insulating material.
`8. The structure of claim 5 wherein said first electri-
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`cal insulating material is silicon dioxide.
`9. The structure of claim 8 wherein said second elec-
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`trical insulating material is silicon nitride.
`10. The structure of claim 5 wherein said second
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`electrical insulating material is silicon nitride.
`11. The structure of claim 8 wherein said third electri-
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`cal insulating material is silicon dioxide.
`1!
`It
`it
`#
`*
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`4,638,347
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`5
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`1. A sidewall isolation structure for the gate electrode
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`of an insulated gate field effect transistor which com-
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`prises a first electrical insulating material and a second
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`and different electrical insulating material contiguous
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`with said first electrical insulating material, and wherein
`said second and different electrical insulating material
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`being etched below the surface level of said first electri-
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`cal insulating material and being etched to a greater
`extent than and at a rate faster than said first electrical
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`insulating material to provide a recess in said sidewall
`isolation structure wherein said recess is such as to
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`prevent the formation of a continuous metal film over
`the sidewall isolation.
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`2. The structure of claim 1 wherein said first electri-
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`cal insulating material is silicon dioxide.
`3. The structure of claim 2 wherein said second elec-
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`trical insulating material is silicon nitride.
`4. The structure of claim 1 wherein said second elec-
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`trical insulating material is silicon nitride.
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`Page 7 of 7
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`Page 7 of 7
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