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`United States Patent
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`Douglas
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`[191
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`[11] Patent Number:
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`[45] Date of Patent:
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`4,957,590
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`Sep. 18, 1990
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`Inventor:
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`[75]
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`[73] Assignee:
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`[54] METHOD FOR FORMING LOCAL
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`INTERCONNECTS USING SELECTIVE
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`ANISOTROPY
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`Monte A. Douglas, Coppell, Tex.
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`Texas Instruments Incorporated,
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`Dallas, Tex.
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`[21] Appl. No.: 402,944
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`[22] Filed:
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`Sep. 5, 1989
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`VLSI Applications”, J. Electrochem. Soc.: Solid—State
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`Science and Technol., vol.
`131, No.
`10, 1984, pp.
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`2325-2335.
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`Donnelly et a1., “Anisotropic Etching in Ch1orine—Con-
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`taining Plasmas”, Solid-State Techol., vol. 24, No. 4,
`1981, pp. 161-166.
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`Shah, “Refractory Metal Gate Processes for VLSI
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`Applications”, IEEE Trans on Electron Devices, vol.
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`ED—26, No. 4, Apr. 1979, pp. 631-640.
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`Primary Examiner—William A. Powell
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`Attorney, Agent, or Firm—-Rodney M. Anderson
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`ABSTRACT
`[57]
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`A method for etching titanium nitride local intercon-
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`nects is disclosed. A layer of titaniun nitride is either
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`formed as a by-product of the formation of titanium
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`silicide by direct reaction or by deposition. The location
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`of the interconnects is defined by patterning photoresist
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`at the desired locations. A plasma etch using a chlorine-
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`bearing agent such as CCI4 as the etchant etches the
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`titanium nitride anisotropically at those locations cov-
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`ered by photoresist, and isotropically elsewhere, so that
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`filaments of the titanium nitride are removed without
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`undercutting the photoresist mask. The etch is selective
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`relative to the underlying material, such as a refractory
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`metal silicide, refractory metals, or silicon, due to the
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`passivation of the underlying material by the carbon
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`atoms of the CC14. The selectivity, together with the
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`selective anisotropy, even allows significant overetch of
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`the material to remove the filaments without undercut-
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`ting the masked interconnect material.
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`[63]
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`Related U.S. Application Data
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`Continuation-in-part of Ser. No. 273,287, Nov. 17,
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`1988, Pat. No. 4,863,559, which is a continuation of
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`Ser. No. 159,282, Feb. 22, 1988, Pat. No. 4,793,396.
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`[51]
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`Int. Cl.5 ...................... .. B44C 1/22; co3c 15/oo;
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`co3c 25/O6; C23F 1/02
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`[52] U.s. c1. .................................... 156/643; 156/646;
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`156/662; 156/659.1; 204/192.35
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`[58] Field of Search ............. .. 156/643, 646, 652, 653,
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`156/655, 656, 657, 659.1, 662, 667; 204/192.32,
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`192.35, 192.37; 357/23.1, 65, 67; 437/180, 200,
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`228; 252/79.1
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`References Cited
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`U.S. PATENT DOCUMENTS
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`4,574,177
`3/1986 Wang ............................ 219/121 PE
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`4,657,628 4/1987 Holloway et al
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`156/643
`4,676,866 6/ 1987 Tang et al.
`..
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`4,690,730 9/1987 Tang et al.
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`156/643
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`4,784,973 11/1988 Stevens ct al
`437/200
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`4,793,896 12/1988 Douglas ............................ .. 156/643
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`OTHER PUBLICATIONS
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`Chow et al., “Plasma Etching of Refractory Gates for
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`29 Claims, 4 Drawing Sheets
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`TSMC Exhibit 1011
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`U.S. Patent
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`U.S. Patent
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`Sep.18,1990
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`1
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`METHOD FOR FORMING LOCAL
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`INTERCONNECTS USING SELECTIVE
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`ANISOTROPY
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`This application is a continuation-in-part of applica-
`tion S.N. 273,287 filed Nov. 17, 1988, now U.S. Pat. No.
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`4,863,559, which is a continuation of application S.N.
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`159,282 filed Feb. 22, 1988, now U.S. Pat. No. 4,793,896
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`issued Dec. 27, 1988.
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`This invention relates in general to semiconductor
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`devices, and in particular to an improved method for
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`forming local
`interconnects using chlorine bearing
`agents.
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`BACKGROUND OF THE INVENTION
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`Increasing the number of levels of interconnects
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`(both intra-level and inter-level) in integrated circuits
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`provides additional routing capability, more compact
`layouts, better circuit performance and greater use of 20
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`circuit design within a given integrated circuit surface
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`area. A particularly useful level of connection is com-
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`monly called local interconnection, where neighboring
`diffused areas are connected to one another, and to
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`neighboring polysilicon and metal lines.
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`For example, a conventional method for creating
`local interconnects uses metal interconnection of dif-
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`fused regions to one another, as well as to other layers.
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`The metal interconnection is formed by etching vias
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`through a thick oxide layer to the locations to be inter-
`connected. A conductor is then formed to fill the vias
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`and make the connection. This method is limited, for
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`purposes of reducing the area required for such connec-
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`tion, by the state of the technology of etching contact
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`holes and the planarization of interlevel dielectrics.
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`These limitations include the alignment tolerance of the
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`vias to the underlying region to be connected, the size
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`of the via required (and accordingly the size of the
`contact area in the underlying region) which can be
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`reliably etched, and the step coverage of the conductor
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`in filling the via and making good ohmic contact to the
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`underlying region. Also, the additional layer of a metal-
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`of planarization in subsequent levels.
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`An alternative method developed by Hewlett Pack-
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`ard and published at page 118 of the 1984 IEDM Pro-
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`ceedings uses additional patterned silicon to provide
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`conductive silicide regions extending over the field
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`oxide as desired. A layer of titanium is deposited over
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`the substrate and, prior to the direct reaction of the
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`titanium with the underlying silicon to form the silicide,
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`a thin layer of silicon is patterned on top of the titanium
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`metal to define an interconnect extending over a silicon
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`dioxide region separating the two regions to be inter-
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`connected. Where this silicon layer remains, a silicide is
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`formed during the reaction process extending over the
`oxides. This method requires the deposition and pat-
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`terning of the additional layer of silicon to define the
`local interconnection. In addition, the resulting silicide
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`strap provides a conduit through which typical n-type
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`dopants such as phosphorous can diffuse, since titanium
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`silicide is a very poor diffusion barrier to conventional
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`semiconductor dopants. If a silicide strap is used to
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`connect n-type regions to p-type regions, for example .
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`n-doped polysilicon to p-type diffusion, subsequent
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`processing must be done at relatively low temperatures
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`to minimize the counterdoping of the p-type region
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`4,957,590
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`2
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`with the n-type dopant through the silicide intercon-
`nect.
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`Another known method uses molybdenum metal as a
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`local
`interconnect material. Molybdenum, however,
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`also acts as a diffusion conduit through which phospho-
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`rus, used to dope n-type regions of the semiconductor
`device, can diffuse. The molybdenum interconnect
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`therefore is not an effective local interconnect between
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`n-type and p-type regions, as the p-type regions can be
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`undesirably counterdoped by the phosphorous diffusing
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`through the molybdenum, similarly as the silicide strap
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`interconnect.
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`Another local interconnection method is disclosed in
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`U.S. Pat. No. 4,675,073, issued to me on June 23, 1987,
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`and assigned to Texas Instruments Incorporated, incor-
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`porated herein by this reference. As disclosed therein,
`the desired local interconnect is formed by patterning
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`the residual titanium compound, for example titanium
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`nitride, from the direct reaction forming titanium sili-
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`cide cladding of the diffusions and polysilicon gates.
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`The titanium nitride is sufficiently conductive so that it
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`is useful to make local interconnections between neigh-
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`boring regions. The disclosed process uses carbon tetra-
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`fluoride (CF4) as the reactant in a plasma etch to re-
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`move the undesired titanium nitride faster than titanium
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`silicide. This plasma etch using carbon tetrafluoride
`etches titanium nitride or titanium oxide at approxi-
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`mately twice the rate it removes titanium silicide. This
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`technique also etches silicon oxides at twice the rate,
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`and photoresist at five times the rate, as it etches tita-
`nium nitride or titanium oxide. Additionally, products
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`of the etching process include solids that tend to adhere
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`to the etching device. This requires extra maintenance
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`and cleanup time that is nonproductive. Thus, a need
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`has arisen for a method for producing a local intercon-
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`nect with increased selectivity to the refractory metal
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`compound of the local interconnect (e.g., titanium ni-
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`tride or titanium oxide) relative to silicides, silicon ox-
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`ides and photoresist, so that an additional layer of inter-
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`connection may be more consistently manufactured
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`with precisely located interconnects and improved pla-
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`narization compatible with sub-micron technology.
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`For purposes of forming such small feature sizes for
`the interconnect, it is well known that etches which are
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`substantially anisotropic (i.e., directional) are preferred.
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`Anisotropic etches provide improved control in fabri-
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`cation, since the patterned masking material more
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`closely defines the feature to remain after the etch;
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`etches which are more isotropic tend, of course,
`to
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`undercut the mask, requiring that the size of the pat-
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`terned masking material be made larger than that of the
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`desired feature in order to compensate for the line width
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`loss resulting from the undercut.
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`However, substantially anisotropic etches can leave
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`filaments of the material being etched. Such filaments
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`tend to occur at locations where the etched material
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`makes a step over surface topography. In the case of the
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`local interconnect discussed above, such filaments can
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`create a short circuit between conductive structures at
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`the top of, and at the bottom of, a step where no such
`connection is desired. In addition, filaments may be
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`present
`laterally, connecting two otherwise uncon-
`nected structures.
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`It should also be noted that the titanium nitride may
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`be used as a gate material, especially in the case where
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`it is deposited. Similar problems concerning the etch as
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`described above will also affect the etch of such tita-
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`Page 4 of 10
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`4,957,590
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`3
`nium gate electrodes, as well as other structures for
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`which a conductive titanium compound may be used.
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`It is therefore an object of this invention to provide
`an etch for the residual material over insulating layers
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`remaining from the direct react silicidation which is
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`anisotropic at the locations where the masking layer is
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`in place to define the interconnect, but which is iso-
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`tropic elsewhere so that filaments of the interconnect
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`material are removed.
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`It is a further object of this invention to provide such
`an etch which also has improved etch selectivity (i.e.,
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`an increased etch rate ratio) of the interconnect relative
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`to underlying conducting layers.
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`It is a further object of the present invention to pro-
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`vide such an etch with improved selectivity to titanium
`nitride or titanium oxide with respect to titanium sili-
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`cide, silicon dioxide and photoresist.
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`It is a further object of the present invention to pro-
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`vide such an etch which reduces the preventative main-
`tenance and cleanup schedules and procedures by the
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`use of a chlorine bearing agent as opposed to a flourine
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`agent.
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`Other objects and advantages of the invention will
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`become apparent to those of ordinary skill in the art
`having reference to the following specification in con-
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`junction with the drawings.
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`SUMMARY OF THE INVENTION
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`The invention may be incorporated into a method for
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`forming a local interconnect on a semiconductor sur-
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`face. A dielectric layer of a prefabricated integrated
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`circuit is covered with a conductive chemical com-
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`pound of a refractory metal, such as titanium. The com-
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`pound may be formed by deposition, or as a by-product
`of the silicidation of the refractory metal at locations
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`where it is in contact with the underlying semiconduc-
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`tor. Photoresist is placed over this chemical compound
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`layer to protect a specific portion thereof which will
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`serve as an interconnect. A chlorine bearing agent is
`used to etch the exposed conductive chemical com-
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`pound layer, which occurs in substantially an aniso-
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`tropic manner at those locations where the photoresist
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`is in place. At those locations where the photoresist is
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`absent, the etch is substantially isotropic. Accordingly,
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`the etch removes filaments which may otherwise re-
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`main upon clearing of the surfaces, without undercut-
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`ting the photoresist mask. The chlorine bearing agent
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`etches the conductive chemical compound at a greater
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`rate than the underlying silicide, or other material used
`as a conductor.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`For a more complete understanding of the present
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`invention, and for further advantages thereof, reference
`is now made to the following description taken in con-
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`junction with the accompanying drawings in which:
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`FIG. 1 is a cross-sectional view of a partially fabri-
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`cated integrated circuit with a titanium chemical com-
`pound formed over the entire surface;
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`FIG. 2 is a cross-sectional view of the device of FIG.
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`1 with patterned masking material added over the area
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`to be protected;
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`FIG. 3 is a cross-sectional view of an integrated cir-
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`cuit with a local interconnect formed in accordance
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`with the present invention.
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`FIGS. 4a and 4b are cross-sectional views of an inte-
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`grated circuit with a local interconnect formed accord-
`ing to an alternate embodiment of the invention.
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`4
`FIG. 5 is a cross-sectional SEM microphotograph
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`illustrating the anisotropy of the etch described herein.
`DETAILED DESCRIPTION OF THE
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`PREFERRED EMBODIMENTS
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`FIG. 1 shows the first step utilizing the method of the
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`preferred embodiment of the present invention, as di-
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`rected to an integrated circuit wafer 44. Wafer 44 con-
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`tains a semiconducting substrate 10 formed of silicon.
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`Field oxide 12, preferably silicon dioxide (SiOz),
`is
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`grown or deposited in selected portions of the surface of
`the substrate 10 for isolation of active regions from one
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`another according to the well known local oxidation
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`(LOCOS) isolation technique; of course, other isolation
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`techniques such as trench isolation may alternatively be
`used. The active transistors of the integrated circuit
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`device are formed into the locations of the surface of
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`substrate 10 not covered with field oxide 12, such loca-
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`tions commonly called moat regions. In FIG. 1, a tran-
`sistor 44 is shown having source and drain regions 14
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`and 16, respectively, diffused into the moat region be-
`tween two portions of field oxide 12. Source and drain
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`regions 14 and 16 are generally implanted and subse-
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`quently diffused after the placement of polysilicon gate
`electrode 30 over gate dielectric 24, so that source and
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`drain regions 14 and 16 are self-aligned relative to gate
`electrode 30. As described in U.S. Pat. No. 4,356,623,
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`issued Nov. ll, 1982 and assigned to Texas Instruments
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`Incorporated, the incorporation of sidewall oxide fila-
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`ments 26 along the side of gate electrode 30 provide for
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`a graded junction, as shown in FIG. 1. FIG. 1 further
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`illustrates a polysilicon layer 42 overlying field oxide 12
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`serving as an interconnect to another portion of the
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`integrated circuit, for example extending to another
`moat region (not shown) and serving as the gate elec-
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`trode for a transistor.
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`In this embodiment of the invention, source and drain
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`regions 14 and 16, and gate electrodes 30 and 42, are
`clad with a refractory metal silicide such as titanium
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`silicide. This cladding is performed by depositing a
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`layer of the refractory metal, and subsequently heating
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`the wafer 44 so that the metal directly reacts with the
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`underlying silicon to form the silicide, as described in
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`U.S. Pat. No. 4,384,301, issued on May 17, 1983 and
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`assigned to Texas Instruments Incorporated. An exam-
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`ple of the conditions for such direct reaction is heating
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`the wafer 44 in a nitrogen and argon ambient at a tem-
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`perature on the order of 675° C. Other methods of
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`achieving the direct reaction may alternatively be used,
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`for example, by use of a single-wafer Rapid Thermal
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`Processor (RTP) where the wafer 44 is rapidly heated
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`to the appropriate temperature for a sufficient amount
`of time to perform the direct reaction described above.
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`It has been determined by physical analysis that the
`titanium silicide formed in this manner may not be stoi-
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`chiometrically, or chemically, pure titanium silicide, but
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`that measurable amounts of other materials such as
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`silicon oxide and other oxides are also present in the
`film.
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`As described in said U.S. Pat. No. 4,675,073, where
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`titanium is used as the refractory metal, as a result of the
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`direct reaction process a layer of a conductive titanium
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`compound covers the surface of the wafer 44, including
`the silicide regions. Referring to FIG. 1, source region
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`14, drain region 16, and gate electrodes 28 and 42 are
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`shown clad with titanium silicide film 20, 22, 28 and 40,
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`respectively. A layer 43 of residual material containing,
`for example, titanium nitride if the direct reaction is
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`Page 5 of 10
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`Page 5 of 10
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`

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`5
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`performed in a nitrogen atmosphere, remains over the
`surface; if a layer of oxide (not shown) is provided over
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`the top of the titanium metal layer prior to the direct
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`reaction, as described in U.S. Pat. No. 4,690,730 issued
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`Sept. 1, 1987 and assigned to Texas Instruments Incor-
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`porated, layer 43 may contain titanium oxide. When
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`formed in the nitrogen atmosphere, in the event that
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`oxygen is present (at contamination-level concentra-
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`tion) in the titanium metal or in the atmosphere, or from
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`the underlying silicon dioxide, layer 43 may also include
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`titanium oxide, for example in the form of titanium
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`oxynitride (TiO);Ny).
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`Layer 43 will have a thickness on the order of 100 nm
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`over field oxide 12, and will be thinner (e.g., on the
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`order of 40 nm thick) in the locations over silicide film
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`20, 22, 28 and 40 cladding the underlying silicon or
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`polysilicon. If desired, the thickness of layer 43 may be
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`increased by a second deposition of titanium metal after
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`the initial direct reaction, followed by a second direct
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`reaction in a nitrogen atmosphere, as described in U.S.
`
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`Pat. No. 4,676,866 issued June 30, 1987 and assigned to
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`Texas Instruments Incorporated.
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`It should further be noted that the instant invention is
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`also applicable to other structures, as well as to similar
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`interconnection structures formed in a different manner.
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`For example, layer 43 may alternatively be formed by
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`way of deposition, for example by chemical vapor de-
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`position or by sputtering of titanium nitride. If layer 43
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`is deposited, it should be noted that the structure may
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`not necessarily include a silicide cladding on the sur-
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`faces of the source/drain regions 14 and 16, or on the
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`gate electrode 30. However, for such a structure the
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`etch process described herein is also beneficial for the
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`selective etching of the interconnect layer 43.
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`Referring to FIG. 2, the next step in the preferred
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`embodiment of the present invention is illustrated. A
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`layer of masking material is deposited over layer 43, and
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`is patterned according to conventional techniques to
`remain in the locations of the eventual local intercon-
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`nect, as shown by patterned masking material 46 in
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`FIG. 2. The masking material 46 serves to protect the
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`covered portion of layer 43 from subsequent etching.
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`The patterned masking material 46 may be photoresist,
`or a hardmask material such as silicon dioxide.
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`When photoresist serves as the masking material 46, it
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`is preferable to clean the surface of wafer 44 prior to
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`beginning the etching process, by use of an 02 based
`resist descum to establish etch rate uniformity, to pre-
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`vent extended etch initiation periods and to eliminate
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`post-etch scumming problems or incomplete etching of 50
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`layer 48. An 02 descum time equal to the removal of
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`approximately 400A of resist is sufficient. Wafer 44 is
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`then hardbaked at 120° C. for approximately 60 minutes
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`in an oven and then 02 descummed again. It is necessary
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`to redo the descum if more than a three hour delay is
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`incurred after the descum before the local interconnect
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`dry etch described below to avoid incomplete etching
`of the local interconnect. It should also be noted that
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`the oxygen descum, if performed after hard bake, will
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`remove the resist anisotropically.
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`After patterning masking material 46, wafer 44 is
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`placed in any appropriate plasma ‘etching device such as
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`plasma mode etcher, a reactive ion etcher or a micro-
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`wave after glow, which are well known in the art. In
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`the preferred embodiment, a plasma mode etcher, not
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`shown, utilized. The plasma mode etcher comprises a
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`symmetrical parallel plate reactor, for example with the
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`substrate grounded. The powered top plate comprises
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`4,957,590
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`6
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`graphite or titanium, and the bottom plate may com-
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`prise bare aluminum. The plates are spaced approxi-
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`mately one centimeter apart, and approximately 200
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`watts of power is applied. Radio frequency (RF) energy
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`is transmitted between the parallel plates by an RF
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`generator. The powered electrode also serves as a gas
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`dispersal source similar to a shower head. According to
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`the invention, a chlorine bearing agent such as carbon
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`tetrachloride (CCI4) is used as the dry etch reactant in
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`the plasma mode etcher. Wafer 44 is placed on the
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`grounded plate which is spaced apart from the powered
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`plate by approximately one centimeter. The preferred
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`substrate temperature is on the order of 50° C.
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`Carbon tetrachloride is a particularly useful chlorine-
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`bearing agent for thisletch because it can exhibit low
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`etch rates of photoresist and silicon dioxide. Carbon
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`tetrachloride also has a carbon center which will serve
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`to “poison” the titanium silicide first layers 20, 22, 28
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`and 40 once layer 43 of the titanium compound lying
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`over them has been etched. This poisoning, or surface
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`passivation, is due to carbon, probably in the form of a
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`partially dissociated carbon tetrachloride molecule
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`(such as CC]; where it: 1, 2 or 3) reacting with either
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`the titanium or the silicon in the titanium silicide film 20,
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`22, 28 and 40 to form silicon carbide or titanium carbide.
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`Since silicon carbide and titanium carbide are both non-
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`volatile, the reactive sites on the titanium silicide first
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`layers 20, 22, 28 and 40 are effectively “tied up”, con-
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`sumed or covered, thus preventing reaction of layers 20,
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`22, 28 and 40 with the other reactive species in the etch,
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`namely chlorine. If not passivated, the chlorine in the
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`etch is capable of volatilization and etching of the tita-
`nium or the silicon in silicide film 20, 22, 28 and 40.
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`Moreover, the surface passivation from the chlorocar-
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`bon reagents can be of such a magnitude that a polymer
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`film is formed, so that the surface passivation is on a
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`macroscopic scale rather than a molecular scale.
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`Conversely, the reactive carbon containing species
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`will react with the nitrogen component of the titanium
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`nitride in layer 43 to form CN or CN2, each of which is
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`volatile. If oxygen is present in layer 43, the reactive
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`carbon containing species will react with the oxygen to
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`form carbon monoxide, also volatile. The residual
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`atomic chlorine radicals will react with the titanium
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`component in the titanium nitride of layer 43 to form
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`titanium chloride (TiClx where x=1—4), which is also
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`volatile. Thus, the titanium nitride of layer 43 which is
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`not protected by patterned masking material 46 will be
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`etched, while leaving the titanium silicide first layers 20,
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`22 28 and 4-0, field oxide 12, and patterned masking
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`material 46.
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`This mechanism, where the carbon from the carbon
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`tetrachloride builds a residue on the material which is
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`not to be substantially etched, but which reacts with
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`nitrogen in the titanium nitride film to form volatile
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`cyanogen (and with oxygen to form volatile carbon
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`monoxide), can apply to other underlying layers having
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`the same property as the titanium silicide. These other
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`underlying layers can be either insulating or conduc-
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`tive. Examples of conductive material which are be-
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`lieved to have the property of being unable to volatilize
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`the carbon, and which therefore will have a residue
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`buildup thereupon when the titanium nitride is etched
`with the carbon tetrachloride etch described above,
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`include silicon, cobalt silicide, tungsten, molybdenum,
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`among others.
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`In order to initiate the plasma, it is necessary to de-
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`tach electrons from the chlorocarbon anions present in
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`Page 6 of 10
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`Page 6 of 10
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`7
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`the plasma gas. Because neutral chlorocarbon species
`have high cross-sections for electron attachment, the
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`reaction chamber tends to become depleted of free
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`electrons, which are crucial to the ignition of the plasma
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`by the mechanism of electron-impact ionization of other
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`atomic and molecular species. Such electron-impact
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`ionization is generally required to ignite the plasma
`once the avalanche condition is reached. As is well
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`known in the art, the electron is an important charged
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`species in plasma ignition since its low mass allows it to
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`be sufficiently energized by an RF electric field to ion-
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`ize a neutral species.
`A useful method according to the invention for gen-
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`erating sufficient free electrons to ignite the CCI4
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`plasma is to illuminate the reaction chamber with a light
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`source, with the light havi