“
`
`Proceedings of the
`
`Interconnect
`Infernationd|
`Te&thnology Gonference
`
`June 1-3, 1998
`Hyatt Regency Airport Hotel,
`San Francisco, California
`
`The HTC is sponsored by the IEEE Electron
`
`Devices Society.
`
`Its goal is to provide a forum
`
`for professionals in semiconductor processing,
`
`academia and equipment developmentto present
`
`and discuss exciting new science and technology.
`
`Sponsored by the
`IEEE Electron Devices Society
`
`,
`
`
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`ME
`y- CONG
`.
`{*.
`S\
`Proceedingsof the
`NGF)
`IEEE 1998
`|
`INTERNATIONAL
`INTERCONNECT TECHNOLOGY
`CONFERENCE
`
`Hyatt Regency Hotel
`San Francisco, CA
`
`June 1 - 3, 1998
`
`Its goalis to provide a forum for professionals
`TheIITC is sponsored by the IEEE Electron Devices Society.
`in semiconductor processing, academia and equipment developmentto present and discuss exciting new
`science and technology.
`
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`
`
`1998 International Interconnect Technology Conference
`Digest of Technical Papers
`
`Papers have beenprinted withoutediting as received from the authors.
`
`Copyright and Reprint Permissions: Abstracting is permitted with credit to the source. Libraries are
`permitted to photocopy beyondthelimit of U.S. Copyright law for private use of patrons thosearticlesin
`this volume that carry a codeat the bottom ofthefirst page, provided the per-copy fee indicated in the
`codeis paid through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For
`other copying, reprint or republication permission, write to IEEE Copyrights Manager, IEEE Service
`Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331. All rights reserved.
`Copyright © 1998 bytheInstitute of Electrical and Electronics Engineers, Inc.
`
`PRINTED IN THE UNITED STATES OF AMERICA
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`7K 787
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`» 6S
`2SIIS
`1738
`
`Additional copies may be orderedfrom:
`IEEE Order Dept.
`445 Hoes Lane
`Piscataway, NJ 08855
`TEL: (800) 678-4333
`
`IEEE Catalog Number: 98EX102
`ISBN: 0-7803-4285-2 (Softbound)
`ISBN: 0-7803-4286-0 (Microfiche)
`Library of Congress: 97-80205
`
`a 3 O2 0G
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`

`INORGANIC LOW K DIELECTRIC INTEGRATION
`SESSION 4:
`Co-chairs: Michael Thomas and Nobuo Hayasaka
`
`A Manufacturable Embedded Fluorinated SiO, for Advanced 0.25 um
`4:00
`CMOSVLSIMultilevel Interconnect Applications
`C.S. Pai, A.N. Velaga*, W.S. Lindenberger, W.Y.-C. Lai, K.P. Cheung,F.H.
`Baumann, C.P. Chang, C.T. Liu, R. Liu, P.W. Diodato, J.I. Colonel, H. Vaidya,
`S.C. Vitkavage*, J.T. Clemens and F. Tsubokura**, Lucent Technologies, Murray
`Hill, NJ, “Orlando, FL and **NEC Corporation, Kanagawa, Japan
`
`Highly Reliable Low-c (3.3) SiOF HDP-CVD for Subquarter-Micron CMOS
`Applications
`T. Fukuda, T. Hosokawa, E. Sasaki, and N. Kobayashi, Hitachi, Ltd., Tokyo,
`Japan
`
`Integration of Unlanded Via in a Non-Etchback SOG Direct-on-Metal
`Approach in 0.25 Micron CMOSProcess
`T. Gao”, B. Coenegrachts*, J. Waeterloos*, G. Beyer*, H. Meynen*, M. Van Hove*
`and K. Maex***, IMEC, Leuven, Belgium and **INSYS, K.U., Leuven, Belgium
`
`Suppressing Oxidization of Hydrogen Silsesquioxane Films by Using H,O
`Plasmain Ashing Process
`E. Tamaoka, T. Ueda, N. Aoi and S. Mayumi, Matsushita Electronics Corp., Kyoto,
`Japan
`
`Tuesday, June 2
`
`IMPACT ON CIRCUIT PERFORMANCE
`SESSION 5:
`Co-chairs: Krishna Saraswat and Genda Hu
`
`Invited - Impact of Interconnect on Circuit Design Performance
`J-P. Schoellkopf, SGS-Thomson, Crolles, France
`
`8:55 Minimum Repeater Count, Size, and Energy Dissipation for
`Gigascale Integration (GSI) Interconnects
`J.C. Eble, V.K. De*, D.S. Wills and J.D. Meindl, Georgia Institute of Technology,
`Atlanta, GA and *Intel Corp., Hillsboro, OR
`
`Low-k Dielectrics Influence on Crosstalk: Electromagnetic Analysis and
`Characterization
`C. Cregut, G. Le Carval* and J. Chilo, PFT-CEM,St Martin d'Heres, France and
`*LETI/CEA, Grenoble, France
`
`Advanced Wiring RC Delay Issues for sub-0.25-micron Generation CMOS
`A.K. Stamper, M.B. Fuselier and X. Tian, IBM Microelectronics, Essex Junction VT
`
`4:00
`4.1
`
`4:25
`4.2
`
`4:50
`43
`
`5-15
`4.4
`
`8:30
`5.1
`
`8:55
`BZ
`
`9:20
`OS
`
`9:45
`5.4
`
`39
`
`42
`
`45
`
`48
`
`53
`
`56
`
`59
`
`62
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`

`4:10
`12.4
`
`4:35
`12.5
`
`5:00
`12.6
`
`5:25
`27,
`
`P1.1
`
`P1.2
`
`P1.3
`
`P1.4
`
`P1.5
`
`P1.6
`
`Paz.
`
`P1.8
`
`P1.9
`
`P1.10
`
`Impact of Low Pressure Long Throw Sputtering Method on Submicron Copper
`Metallization
`T. Saito, N. Ohashi, J. Yasuda, J. Noguchi, T. Imai, K. Sasajima, K. Hiruma, H.
`Yamaguchi and N. Owada, Hitachi Ltd., Tokyo, Japan
`
`CVD Cu ProcessIntegration for Sub-0.25 um Technologies
`J. Zhang, D. Denning, G. Braeckelmann, R. Venkatraman, R. Fiordalice and E.
`Weitzman, Motorola Inc., Austin, TX
`
`Self-Annealing of Electrochemically Deposited Copper Films in Advanced
`Interconnect Applications
`T. Ritzdorf, L. Graham,S. Jin*, C. Mu* and D. Fraser*, Semitool, Inc., Kalispell, MT and
`*Intel Corp., Santa Clara, CA
`
`A Novel Cu-Plug Formation Using High Pressure Reflow Process
`K. Maekawa, T. Yamamura*, T.Fukada, A. Ohsaki and H. Miyoshi, Mitsubishi Electric
`Corp., Hyogo, Japan and *Ryoden Semiconductor System Engineering Corp., Japan
`
`POSTER SESSION|
`
`Effects of PECVD Deposition Fluxes on the Spatial Variation of Thin Film Density
`of As-Deposited SiO2 Films in Interconnect Structures, K. Lee, M. Deal, J. McVittie,
`J. Plummerand K. Saraswat, Stanford University, Stanford, CA
`Modeling of Metal-over-Silicon Microstrip Interconnections: The Effect of SiO02
`Thickness on Slow-WaveLosses, L. Wang, Y.L. Le Coz, R.B. Iverson and J.F.
`McDonald, Rensselaer Polytechnic Institute, Troy, NY
`Application of Charge Based Capacitance Measurement (CBCM) Techniquein
`Interconnect Process Development, S. Bothra, G.A. Rezvani, H. Sur, M. Farr, and
`J.N. Shenoy, VLSI Technology, Inc., San Jose, CA
`Stochastic Interconnect Network Fan-Out Distribution Using Rent's Rule, P.
`Zarkesh-Ha,J.A. Davis, W. Loh* and J.D. Meindl, Georgia Institute of Technology,
`Atlanta, GA and *LSI Logic Corp., Milpitas, CA
`
`Robustnessof Self-Aligned Titanium Silicide Process: Improvementin Yield of
`Silicided Devices with APM Cleaning Step, C.W. Lim***, K.H. Lee**, K.L. Pey**, H.
`Gong’, A.J. Bourdillon*, S.K. Lahiri*, “National University of Singapore and **Chartered
`Semiconductor Manufacturing Ltd., Singapore
`The Effects of Stress on the Formation of Titanium Silicide, S.L. Cheng, H.Y.
`Huang, Y.C. Peng L.J. Chen, B.Y. Tsui*, C.J. Tsai**, S.S. Guo** and K.H. Yu**, National
`Tsing Hua University, *ERSO/ITRI, and **National Chung Hsing University, Taiwan,
`ROC
`
`Correlation of Film Thickness and Deposition Temperature with PAI and the
`Scalability of Ti-SALICIDE Technology to Sub-0.18um Regime, C. S.Ho, R.P.G.
`Karunasiri, S.J. Chua, K.L. Pey*, S.Y. Soh*, K. H. Lee*, and L. H. Chan’*, National
`University of Singapore and *Chartered Semiconductor Manufacturing Ltd., Singapore
`
`Interconnect Material and CMP Process ChangeEffects on Local Interconnect
`Planarity, J. Mendonca, C. Dang, C. Pettinato, J. Cope, H. Garcia, J. Saravia, J.
`Farkas, D. Watts, and J. Klein, Motorola, Inc., Austin, TX
`
`One Step Effective Planarization of Shallow Trench Isolation, H-W. Chiou and L-J.
`Chen, ERSO/ITRI, Taiwan, ROC
`
`Nitrogen Effect on Post-Nucleation Tungsten CVD Film Growth, R. Petri, H. Hauf*,
`D. Berenbaum’, J.C. Favreau*, P. Mazet, ATMEL and *Applied Materials, Rousset,
`France
`
`160
`
`163
`
`166
`
`169
`
`175
`
`178
`
`181
`
`184
`
`187
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`190
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`193
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`196
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`199
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`202
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`

`P1.11
`
`P1142
`
`Pits
`
`P1.14
`
`P1.15
`
`P1.16
`
`PLAT
`
`P1.18
`
`P1.19
`
`P1.20
`
`P1.21
`
`P2.4
`
`P2:2
`
`P2.3
`
`P2.4
`
`Laser Programmable Metallic Vias, J.B. Bernstein, W. Zhang and C.H. Nicholas,
`University of Maryland, College Park, MD
`New Via Formation Process for Suppressing the Leakage Current Between
`Adjacent Vias for HydrogenSilicate Based Inorganic SOGIntermetal Dielectric, N.
`Oda, T. Usami, T. Yokoyama, A. Matsumoto, K. Mikagi, H. Gomi, and |. Sakai, NEC
`Corp., Kanagawa, Japan
`Study on the Stability of HDP-SiOF Film and IMD Application for 0.25u.m LSI
`Device, H.J. Shin, S.J. Kim, B.J. Kim, H.K. Kang and M.Y. Lee, Samsung Electronics
`Co., Kyungki, Korea
`Chemical Vapor Deposition and Physical Vapor Deposition of Metal/Barrier Binary
`Stacks on Polytetrafluorethylene Low-k Dielectric, R. Talevi, S. Nijsten, H.
`Gundlach, A. Knorr, K. Kumar. Z. Bian, T. Rosenmayer*, A.E. Kaloyeros and R.E. Geer,
`State University of New York, Albany, NY and *W.L. Gore and Assoc., Eau Claire, WI
`Integration of Low k Spin-on Polymer (SOP) Using Electron Beam Cure for Non-
`Etch-Back Application, J.C.M. Hui, Y. Xu, C.Y. Foong, L. Marvin, L. Charles, L.Y.
`Shung, A. Inamdar*, J. Yang*, J. Kennedy*, M. Ross* and S.-Q. Wang, Chartered
`Semiconductor Manufacturing Ltd., Singapore and “AlliedSignal, Inc., Santa Clara, CA
`A Novel Wholly Aromatic Polyetheras an Interlayer Dielectric Material, T. Tanabe,
`K. Kita, M. Maruyama, K. Sanechika, M. Kuroki and N. Tamura, Asahi Chemical Industry
`Co., Ltd., Shizuoka, Japan
`A Methodfor Improving the Adhesion of PE-CVD SiO, to Cyclotene™ 5021
`Polymeric Interlayer Dielectric, E.O. ShafferII, M.E. Mills, D.D. Hawn, J.C. Liu* and
`J.P. Hummel*, The Dow Chemical Co., Midland, MI and *IBM, Hopewell Junction, NY
`
`Two-Step Planarized Al-Cu PVD Process Using Long Throw Sputtering
`Technology, T.-K. Ku, H.-C. Chen, Y. Mizusawa*, N. Motegi*, T. Kondo*, S. Toyoda’,
`C. Wei**, J. Chen** and L.-J. Chen, ERSO/ITRI, Taiwan, ROC, *ULVAC Japan, Ltd.,
`Japan, and **ULVAC Taiwan Branch, Taiwan, ROC
`
`0.60 xm Pitch Metal Integration in 0.25m Technology, J.R.D. DeBord, V.
`Jayaraman, M. Hewson, W. Lee, S. Nair, H. Shimada, V.L. Linh, J. Robbins, A.
`Sivasothy, Texas Instruments Inc., Dallas, TX
`
`Study of Cu Contamination During CopperIntegraton in a Dual Damascene
`Architecture for Sub-Quarter Micron Technology, J. Torres, J. Palleau, P. Motte’, F.
`Tardif** and H. Bernard*, FT/CNET, Meylan, France, *SGS-Thomson Microelectronics,
`Crolles, France and **CEA/LETI, Grenoble, France
`Developmentof Cu Etch Process for Advanced Cu Interconnects, Y. Ye, D. Ma, A.
`Zhao, P. Hsieh, W. Tu, X. Deng, G. Chu, C. Mu*, J. Chow*, P. Moon* and S. Sherman’,
`Applied Materials Inc., Santa Clara, CA and “Intel Corp., Santa Clara, CA
`
`POSTERSESSION II
`
`Measurementand Modeling of High-SpeedInterconnect-Limited Digital Ring
`Oscillators: The Effect of Dielectric Anisotropy, A. Garg, Y. L. Le Coz, HJ. Greub,
`J.F. McDonald, and R.B. Iverson*, Rensselaer Polytechnic Institute, Troy, NY and
`*Random Logic Corporation, Fairfax, VA
`A Case Study of RC Effects to Circuit Performance, C.S. Pai, P.W. Diodato and R.
`Liu, Bell Laboratories, Lucent Technologies, Murray Hill, NJ
`Modeling Microstructure Developmentin Trench-Interconnect Structures, J.
`Sanchez,Jr. and P. R. Besser*, The University of Michigan, Ann Arbor, MI and
`“Advanced Micro Devices, Sunnyvale, CA
`SAP — A Program Packagefor Three-Dimensional Interconnect Simulation, R.
`Sabelka and S. Selberherr, Institute for Microelectronics, Vienna, Austria
`
`205
`
`208
`
`211
`
`214
`
`217
`
`220
`
`223
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`226
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`229
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`232
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`235
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`241
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`244
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`247
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`250
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`

`

`Comparison of Barrier Materials and Deposition Processes for Copper Integration
`
`M. Moussavi, Y. Gobil, L. Ulmer, L. Perroud, P. Motte***, J. Torrés*, F. Romagna’*,
`M.Fayolle, J. Palleau* and M.Plissonnier**
`
`LETI (CEA Technologies Avancées). DMEL-CEA/G - 17, rue des Martyrs - 38054 Grenoble cedex 9, France
`*FRANCE TELECOM , CNETT/CNS,BP 98, 38243 Meylan cedex, France
`** Applied Materials France 11B, chemin de la Dhuy, 38246 Meylan cedex, France
`***SGS Thomson Microelectronics 850 rue Jean Monnet, 38926 Crolles cedex, France
`
`Abstract
`
`Experimental
`
`This paper reports the investigation of MOCVD (Metal
`Organic Chemical Vapor Deposition) TiN, and IMP
`(Ionized Metal Plasma) Ta and TaN thin films as barrier
`layers
`for
`copper metallization. Evaluation of both
`deposition
`techniques
`including
`step
`coverage, Cu
`adhesion, Cu diffusion and selectivity regarding Cu-CMP
`‘process have been performed. Successful
`implementation
`with copper metallization in high aspect ratio line and via
`patternsis reported.
`
`A. Barrier Materials
`
`An Applied Materials Endura system using IMP (Ionized
`Metal Plasma) was used to deposit Ta and TaN barriers.
`Prior to film deposition, wafers were degassed at 350°C
`and sputter cleaned using a standard AMAT PCIIreactor.
`CVD TiN was performed in P5000 reactor using TDMAT
`precursor with successive steps of deposition and plasma
`treatments.
`
`Introduction
`
`B. Copper Deposition Equipment
`
`integration density continuously increases,
`As circuit
`interconnection size is predicted to decrease both in vertical
`and lateral dimensions. Unfortunately,
`intrinsic properties
`of the materials currently used for interconnection such as
`resistivity and electromigration performance do not allow
`an optimal scaling. This explains the growing interest in
`copper
`for overcoming limitations of the conventional
`aluminium basedalloys (1,2). The two mostcritical aspects
`for
`integration of copper metallization are the optimal
`choice of diffusion barrier material - the Cu diffusion in the
`active areas resulting into degradation of the devices- and
`diffusion barrier material and copper deposition techniques.
`The barrier layer should meet stringent requirements : the
`thickness has to be small enough to not impactinterconnect
`resistance while still acting as a good barrier against Cu
`diffusion. Several barrier materials have been reported as
`good candidates. TiN barrier, currently used with Al-based
`metallization, has shown convenientresults (3). However
`other papers suggest that Tantalum and Tantalum nitride
`could be the best choice.
`In this work a comprehensive
`comparison of the TiN, Ta and TaN performance was
`carried out with regards to Cu integration. A variety of
`solutions have been developed to deposit copper : Ionized
`Metal Plasma, CVD, combination of these techniques and
`the newelectroplating method.
`
`IMP copper used as a seed layer was deposited on an
`Endura system. The Chemical Vapor Deposition of copper
`was performed in a Precision 5000 AMAT cluster tool.
`Two CVD chambers
`are
`available, one for copper
`deposition and the second for TiN-CVD. Copper was
`therefore deposited on TiN barrier, without vacuum break
`between TiN. The cluster equipment allows a clean and
`reproducible TiN/Cu interface. Copper Electroplating on
`various seed layers was performed on a Semitool Equinox
`system using pulsed current in order to achieve uniform
`films with high deposition rates up to 400 nm/min.
`
`C. Chemical Mechanical Polishing
`
`Polishing experiments were carried out on a PRESI
`MECAPOL 550 polisher, using a RODEL IC1000 pad
`stacked on a SUBA IV pad. Theslurry is alumina-based
`and has to be mixed with hydrogen peroxide oxidizer prior
`to use (5).
`Copperand barrier removalrates (RR) were determined by
`polishing respectively Cu, TiN, Ta and TaN blanket wafers.
`Barrier layer selectivities were calculated by the following
`formula: Selectivity = Copper RR / Barrier RR.
`Planarization performance was investigated on topological
`wafers with copper line widths and oxide spaces varying
`from 0.3m to 100pm.
`
`Page12,0f14.«| 0.90 © 1998 IEEE
`
`IITC 98-295
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`Figure3b. Electroplated Copper Film after CMP
`
`C. Chemical Mechanical Polishing
`
`Barrier versus copperselectivity determined on full sheet
`wafers are reported on table 1. Unlike TiN, Ta and TaN
`removalrates are much lower than copper removalrate.
`The elimination of these barrier layers was investigated on
`topological wafers. The 40nm TiN layer was entirely
`removed while keeping acceptable copper dishing and
`oxide erosion effects. The high selectivity of Ta and TaN
`barrier layers was confirmed on topological wafers. To
`quantitatively determine this effect, a thick Ta barrier layer
`(100nm) was used. After polishing using the same
`conditions than for the TiN barrier layer, the remaining Ta
`barrier thickness was measured by SEM. As shown on
`figure 4, less than Snm of the barrier layer were removed,
`demonstrating the excellent CMPstop layer capability of
`Ta material.
`
`
`
`Figure 4. Copper CMPwith Ta barrier
`(0.3 pm line width / 0.3 um oxide space)
`
`Conclusion
`
`A variety of solutions for 0.25um copper interconnect
`technology have been developed. Complete via filling was
`achieved by combination of CVD and IMPtechniques, and
`by electroplating deposition. A comprehensive comparison
`of TiN, Ta and TaN materials as barrier layers for copper
`metallization has been carried out, as these three materials
`proved to block copper diffusion. TiN was suitable for
`usual CMPprocess, involving removal of the entire metal
`stack during polishing. Ta and TaN barriers
`showed
`excellent CMP stop layer capabilities. Therefore, these new
`materials can lead to a novel CMP approach, in which the
`barrier layer is used to prevent from oxide erosion.
`
`Acknowledgment
`
`This work has been carried out within the GRESSI
`Consortium between CEA-LETI and France Telecom-
`CNET.The authors would like to thank B. Chin, T-Y Yao,
`L. Chen and M. Bakli from Applied Materials for their
`active contribution.
`
`References
`
`1. D.Edelstein et al, "Full copper wiring in a sub-0.25ym CMOS ULSI
`technology", Proc. IEEE IEDM,1997, pp. 773-776
`2. S.Venkatesan et al, "A high performance 1.8V, 0.20mm CMOS
`technology with copper metallization", Proc. IEEE IEDM, 1997, pp.
`769-772
`3. C. Marcadal et al, "OMCVD TIN diffusion barrier for copper contact
`an via andline", Proc. VMIC, 1997, pp. 405-410
`4. C. Marcadal et al, "OMCVD Copper process for dual damascene
`metallization", Proc. VMIC,1997, pp. 93-98
`;
`5. M.Fayolle and F. Romagna, "Copper CMPevaluation :planarization
`issues", Proc. Materials for Advanced Metallization Conference,
`Villard de Lans France, 1997, pp. 135-141
`
`Page 14 of 14
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`IITC 98-297
`
`
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