Paper: 14
`Trials@uspto.gov
`571-272-7822 Entered: August 4, 2017
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`CALIFORNIA INSTITUTE OF TECHNOLOGY,
`Patent Owner.
`____________
`
`Case IPR2017-00700
`Patent 7,421,032 B2
`____________
`
`
`
`Before KEN B. BARRETT, TREVOR M. JEFFERSON, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`BARRETT, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`Trials@uspto.gov
`571-272-7822 Entered: August 4, 2017
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`CALIFORNIA INSTITUTE OF TECHNOLOGY,
`Patent Owner.
`____________
`
`Case IPR2017-00700
`Patent 7,421,032 B2
`____________
`
`
`
`Before KEN B. BARRETT, TREVOR M. JEFFERSON, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`BARRETT, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`IPR2017-00700
`Patent 7,421,032 B2
`
`
`INTRODUCTION
`I.
`A. Background and Summary
`Apple Inc. (“Petitioner”) filed a Petition requesting inter partes
`
`review of U.S. Patent No. 7,421,032 B2, issued September 2, 2008
`(“the ’032 patent,” Ex. 1001). Paper 5 (“Pet.”). The Petition challenges the
`patentability of claims 11–17 of the ’032 patent on various grounds of
`obviousness under 35 U.S.C. § 103. California Institute of Technology
`(“Patent Owner”) filed a Preliminary Response to the Petition. Paper 13
`(“Prelim. Resp.”).
`An inter partes review may not be instituted “unless . . . the
`
`information presented in the petition . . . shows that there is a reasonable
`likelihood that the petitioner would prevail with respect to at least 1 of the
`claims challenged in the petition.” 35 U.S.C. § 314(a). Having considered
`the arguments and evidence presented by Petitioner and Patent Owner, we
`determine that Petitioner has demonstrated a reasonable likelihood that it
`would prevail in establishing the unpatentability of challenged claims 11–16
`of the ’032 patent, and that Petitioner has not demonstrated a reasonable
`likelihood that it would prevail in establishing the unpatentability of
`claim 17 of the ’032 patent.
`
`B. Related Proceedings
`One or both parties identify, as matters involving or related to the
`
`’032 patent, Cal. Inst. of Tech. v. Broadcom Ltd., No. 2:16-cv-03714 (C.D.
`Cal. filed May 26, 2016) and Cal. Inst. of Tech. v. Hughes Commc’ns, Inc.,
`2:13-cv-07245 (C.D. Cal. filed Oct. 1, 2013), and Patent Trial and Appeal
`Board cases IPR2015-00059, IPR2015-00060, IPR2015-00061, IPR 2015-
`00067, IPR2015-00068, IPR2015-00081, IPR2017-00210, IPR2017-00211,
`
`2
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`IPR2017-00700
`Patent 7,421,032 B2
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`IPR2017-00219, IPR2017-00297, IPR2017-00423, IPR2017-00701, and
`IPR2017-00728. Pet. 3, Paper 7.
`
`C. The ’032 Patent
`The ’032 patent is titled “Serial Concatenation of Interleaved
`
`Convolutional Codes Forming Turbo-Like Codes.” The ’032 patent
`explains some of the prior art with reference to its Figure 1, reproduced
`below.
`
`
`Figure 1 is a schematic diagram of a prior “turbo code” system. Ex. 1001,
`2:16–17. The ’032 patent specification describes Figure 1 as follows:
`A block of k information bits is input directly to a first coder 102.
`A k bit interleaver 106 also receives the k bits and interleaves
`them prior to applying them to a second coder 104. The second
`coder produces an output that has more bits than its input, that is,
`it is a coder with rate that is less than 1. The coders 102, 104 are
`typically recursive convolutional coders.
`
`Three different items are sent over the channel 150: the
`original k bits, first encoded bits 110, and second encoded bits
`112. At the decoding end, two decoders are used: a first
`constituent decoder 160 and a second constituent decoder 162.
`Each receives both the original k bits, and one of the encoded
`portions 110, 112. Each decoder sends likelihood estimates of
`the decoded bits to the other decoders. The estimates are used to
`decode the uncoded information bits as corrupted by the noisy
`channel.
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`IPR2017-00700
`Patent 7,421,032 B2
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`Id. at 1:41–56.
`
`A coder 200, according to a first embodiment of the invention, is
`described with respect to Figure 2, reproduced below.
`
`
`Figure 2 of the ’032 patent is a schematic diagram of coder 200.
`
`The coder 200 may include an outer coder 202, an
`interleaver 204, and inner coder 206. . . . The outer coder 202
`receives the uncoded data. The data may be partitioned into
`blocks of fixed size, say k bits. The outer coder may be an (n,k)
`binary linear block coder, where n>k. The coder accepts as input
`a block u of k data bits and produces an output block v of n data
`bits. The mathematical relationship between u and v is v=T0u,
`where T0 is an n×k matrix, and the rate[1] of the coder is k/n.
`
`The rate of the coder may be irregular, that is, the value of
`T0 is not constant, and may differ for sub-blocks of bits in the
`data block. In an embodiment, the outer coder 202 is a repeater
`that repeats the k bits in a block a number of times q to produce
`a block with n bits, where n=qk. Since the repeater has an
`irregular output, different bits in the block may be repeated a
`different number of times. For example, a fraction of the bits in
`the block may be repeated two times, a fraction of bits may be
`repeated three times, and the remainder of bits may be repeated
`four times. These fractions define a degree sequence, or degree
`profile, of the code.
`
`The inner coder 206 may be a linear rate-1 coder, which
`means that the n-bit output block x can be written as x=TIw,
`where TI is a nonsingular n×n matrix. The inner coder 210 can
`
`1 We understand that the “rate” of an encoder refers to the ratio of the
`number of input bits to the number of resulting encoded output bits related to
`those input bits.
`
`4
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`IPR2017-00700
`Patent 7,421,032 B2
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`
`have a rate that is close to 1, e.g., within 50%, more preferably
`10% and perhaps even more preferably within 1 % of 1.
`Id. at 2:36–60. In an embodiment, the second (“inner”) encoder 206 is an
`accumulator. Id. at 2:66–67. “The serial concatenation of the interleaved
`irregular repeat code and the accumulate code produces an irregular repeat
`and accumulate (IRA) code.” Id. at 3:30–32.
`
`Figure 4 of the ’032 patent is reproduced below.
`
`
`Figure 4 shows an alternative embodiment in which the outer encoder is a
`low-density generator matrix (LDGM). Id. at 3:56–59. LDGM codes have a
`“sparse” generator matrix. Id. at 3:59–60. The IRA code produced is a
`serial concatenation of the LDGM code and the accumulator code. Id.
`at 3:60–62. No interleaver (as in the Figure 2 embodiment) is required in the
`Figure 4 arrangement because the LDGM provides scrambling otherwise
`provided by the interleaver in the Figure 2 embodiment. Id. at 3:62–64.
`
`“The set of parity checks may be represented in a bipartite graph,
`called the Tanner graph, of the code.” Id. at 3:33–35. Figure 3, shown
`below, depicts such a Tanner graph.
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`Patent 7,421,032 B2
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`
`
`Figure 3 is described as a Tanner graph for an irregular repeat and
`accumulate (IRA) coder. Id. at 2: 20–21. The left-most column of nodes,
`information nodes 302 (the open circles), are variable nodes that receive
`information bits. The column of nodes (the filled circles) just to the right of
`the “RANDOM PERMUTATION” block are check nodes v indicated by
`reference numeral 304. An information bit node connected to two check
`nodes represents a repeat of 2. An information node connected to three
`check nodes represents a repeat of 3. The nodes (the open circles) in the
`right-most column are parity bit nodes x, referenced by 306. As shown by
`the edges2 of the Tanner graph, each parity bit is a function of its previous
`parity bit and is also a function of information bits (edges connect through
`
`
`2 We understand that “edges” are the straight lines that connect one node to
`another node of a Tanner graph. See Ex. 1001, 3:53–54.
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`Patent 7,421,032 B2
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`check nodes and random permutation to information bit nodes). Ex. 1001,
`3:34–55; see also Ex. 1004 ¶ 110 (discussing the relationship between parity
`bits in the context of the claimed Tanner graph and the ’032 patent’s
`specification).
`
`D. Illustrative Claim
`Of the challenged claims of the ’032 patent, claim 11 is the only
`
`independent claim. The remaining challenged claims depend directly or
`indirectly from claim 11. Claim 11, reproduced below as originally issued
`and before issuance of the Certificate of Correction, is illustrative:
`11. A device comprising:
`
`an encoder configured to receive a collection of message
`bits and encode the message bits to generate a collection of parity
`bits in accordance with the following Tanner graph:
`
`
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`7
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`Patent 7,421,032 B2
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`Ex. 1001, 8:63–9:34. A Certificate of Correction for the ’032 patent
`replaced the labels V1, U1, and X1 from the lower portion of the Tanner
`graph in claim 11 with Vr, Uk, and Xr, respectively. See id. at Certificate of
`Correction.
`
`Reference
`
`E. Applied References
`Dates
`
`D. J. C. MacKay et al., Comparison of Constructions of
`Irregular Gallager Codes, IEEE TRANSACTIONS ON
`COMMUNICATIONS, Vol. 47, No. 10, pp. 1449–54, October
`1999 (“MacKay”)
`L. Ping et al., Low Density Parity Check Codes with Semi-
`Random Parity Check Matrix, IEE ELECTRONICS LETTERS,
`Vol. 35, No. 1, pp. 38–39, Jan. 7, 1999 (“Ping”)
`M. Luby et al., Practical Loss-Resilient Codes, PROCEEDINGS
`OF THE TWENTY-NINTH ANNUAL ACM SYMPOSIUM ON THEORY
`OF COMPUTING, May 4–6, 1997, at 150–159 (“Luby97”)
`Dariush Divsalar, et al., Coding Theorems for “Turbo-Like”
`Codes, PROCEEDINGS OF THE THIRTY-SIXTH ANNUAL
`ALLERTON CONFERENCE ON COMMUNICATION, CONTROL, AND
`COMPUTING, Sept. 23–25, 1998, at 201–209 (“Divsalar”).
`H. Pfister and P Siegel, The Serial Concatenation of Rate-1
`Codes Through Uniform Random Interleavers, Presentation at
`Allerton Conference, Sept. 22–24, 1999 (“Pfister Slides”).
`Petitioner also relies on the Declaration of Dr. James A. Davis, dated
`
`January 19, 2017 (Ex. 1004), in support of its arguments. Patent Owner
`relies upon the Declaration of Dr. R. Michael Tanner, dated May 8, 2017
`(Ex. 2001), in support of its arguments.
`
`Exhibit
`No.
`Ex. 1002
`
`Ex. 1003
`
`Ex. 1008
`
`Ex. 1017
`
`Ex. 1022
`
`8
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`
`
`F. Asserted Grounds of Unpatentability
`Petitioner asserts the following grounds of unpatentability:
`References
`Basis
`Claim(s)
`Ping, MacKay, and Divsalar
`§ 103(a) 11, 12, and 14–16
`Ping, MacKay, Divsalar, and Luby97
`§ 103(a)
`13
`Ping, MacKay, Divsalar, and Pfister Slides § 103(a)
`17
`
`II. ANALYSIS
`A. Claim Construction
`In an inter partes review, claim terms in an unexpired patent are given
`their broadest reasonable construction in light of the specification of the
`patent in which they appear. 37 C.F.R. § 42.100(b); see also Cuozzo
`Speed Techs. LLC v. Lee, 136 S. Ct. 2131, 2144–46 (2016). Under the
`broadest reasonable construction standard, claim terms are given their
`ordinary and customary meaning, as would be understood by one of ordinary
`skill in the art in the context of the entire patent disclosure. In re Translogic
`Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`Tanner graph
`In a prior decision regarding the ’032 patent, the Board construed the
`
`Tanner graph of claim 18 (not challenged here) as follows:
`[1] a graph representing an [irregular3 repeat accumulate] IRA
`code as a set of parity checks where every message bit is
`
`3 The Board, the prior decision regarding the ’032 patent, adopted a
`construction where, “[i]n the context of the ’032 patent specification, . . .
`‘irregular’ refers to the notion that different message bits or groups of
`message bits contribute to different numbers of parity bits.”
`IPR2015-00060, Paper 18, 12 (Decision denying institution); see also
`Pet. 24 (advocating the adoption of that construction in this case); Prelim.
`
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`
`repeated, at least two different subsets of message bits are
`repeated a different number of times, and
`[2] check nodes, randomly connected to the repeated message
`bits, enforce constraints that determine the parity bits[, and] . . .
`[3] a parity bit is determined as a function of both information
`bits and other parity bits as shown by the configuration of nodes
`and edges of the Tanner graph.
`IPR2015-00060, Paper 18, 12–14 (numbering and paragraphing added for
`clarity). The Tanner graph of claim 18 is the same as that of claim 11. See
`Ex. 1004 ¶ 99 (Dr. Davis); Ex. 2001 ¶ 20 (Dr. Tanner).
`
`Petitioner supports the application of the same construction here.
`Pet. 26. Patent Owner contends “no construction is necessary beyond
`observing that in the above Tanner graph, different subsets of message bits
`are repeated a different number of times.” Prelim. Resp. 6. Patent Owner’s
`position corresponds to only the first of the three requirements in the
`Board’s prior construction. Patent Owner’s proposed construction does not
`go far enough as it does not address the other limitations apparent from the
`Tanner Graph.
`
`We adopt our prior construction for purposes of this decision.
`
`B. The Alleged Obviousness of
`Claims 11, 12, and 14–16 Over Ping, MacKay, and Divsalar
`Petitioner alleges that claims 11, 12, and 14–16 of the ’032 patent
`
`would have been obvious over Ping, MacKay, and Divsalar. Pet. 39–64.
`Patent Owner opposes. Prelim. Resp. 7–21.
`
`
`Resp. 6 (asserting that the “irregularity” of the Tanner graph of claim 11
`means “different subsets of message bits are repeated a different number of
`times”).
`
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`Petitioner asserts that Ping discloses much of the subject matter of
`
`claim 11, but maintains that Ping’s outer coder is regular. Pet. 41; see also
`id. at 51. Petitioner relies on MacKay for the teaching of irregularity, id.
`at 39, 41, and relies on Divsalar for the teaching of repetition “if Ping
`standing alone is not understood to teach, or render obvious, repeating
`information bits,” id. at 44.
`1. Ping (Ex. 1003)
`Ping is an article directed to “[a] semi-random approach to low
`
`density parity check [LDPC] code design.” Ex. 1103, 38. In this approach,
`“[a]n LDPC code is defined from a randomly generated parity check matrix
`H.” Id. The size of matrix H is (n–k) × n where k is the information length
`and n is the coded length. Id. A codeword c is decomposed “as c = [p, d],
`where p and d contain the parity and information bits, respectively.” Id.
`Parity check matrix H can be decomposed into two parts corresponding to p
`and d as “H = [Hp, Hd].” Id. Hp is defined as follows:
`
`
`Id. Hd is created such that it “has a column weight of t and a row weight of
`kt/(n–k) (the weight of a vector is the number of 1s among its elements),” id.,
`such that
`
`11
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`
`𝑝𝑝1=�ℎ1𝑗𝑗𝑑𝑑
`𝑗𝑗
`
`𝑑𝑑𝑗𝑗 and 𝑝𝑝𝑖𝑖=𝑝𝑝𝑖𝑖−1+�ℎ𝑖𝑖𝑗𝑗𝑑𝑑
`𝑗𝑗
`
`𝑑𝑑𝑗𝑗 (mod 2)
`
`Ex. 1104 ¶ 74.
`Parity bits “p = {pi} can easily be calculated from a given d = {di}”
`
`using the following expressions:
`
`Ex. 1103, 38 (equation (4)).4
`2. MacKay (Ex. 1002)
`MacKay is a paper related to Gallager codes based on irregular
`
`graphs, which are “low-density parity check codes whose performance is
`closest to the Shannon limit.” Ex. 1002, 1449. According to MacKay,
`“[t]he best known binary Gallager codes are irregular codes whose parity
`check matrices have nonuniform weight per column.” Id. A parity check
`matrix that “can be viewed as defining a bipartite graph with ‘bit’ vertices
`corresponding to the columns and ‘check’ vertices corresponding to the
`rows” where “[e]ach nonzero entry in the matrix corresponds to an edge
`connecting a bit to a check.” Id. at 1450. As an example of an irregular
`
`
`4 The reference to “mod 2” refers to modulo-2 addition. Modulo-2 addition
`
`corresponds to the exclusive-OR (XOR or ⊕) logical operation, which is
`defined as follows: 0⊕0=0, 0⊕1=1, 1⊕0=1, and 1⊕1=0. See Ex. 1004
`
`¶ 185.
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`code in a parity check matrix, MacKay describes a matrix that “has columns
`of weight 9 and of weight 3 [and] all rows hav[ing] weight 7.” Id. at 1451.
`3. Divsalar (Ex. 1017)
`Divsalar teaches “repeat and accumulate” codes, described as “a
`
`simple class of rate 1/q serially concatenated codes where the outer code is a
`q-fold repetition code and the inner code is a rate 1 convolutional code with
`transfer function 1/(1 + D).” Ex. 1004 ¶ 89 (quoting Ex. 1017, 1 (Abstr.)).
`Petitioner relies on Divsalar’s Figure 3, reproduced below.
`
`
`
`Figure 3 of Divsalar describes an encoder for a (qN, N) repeat and
`accumulate code. Ex. 1017, 5. The numbers above the input-output lines
`indicate the length of the corresponding block, and those below the lines
`indicate the weight of the block. Id.
`4. The Alleged Obviousness of Independent Claim 11
`For reasons discussed below, Petitioner has shown a reasonable
`
`likelihood that it would prevail in establishing unpatentability of
`independent claim 11 as obvious over Ping, MacKay, and Divsalar.
`
`As discussed above in the context of claim construction, independent
`claim 11 contains a Tanner graph having at least three elements. Petitioner,
`in articulating its obviousness challenge of claim 11, relies on the testimony
`of Dr. Davis and maps the teachings of the prior art against those three
`elements as well as the express recitations of the claim. Pet. 46–57.
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`Petitioner maintains that Ping teaches the recited “encoder configured
`
`to receive a collection of message bits and encode the message bits to
`generate a collection of parity bits.” Id. at 46–47 (citing Ex. 1004 ¶¶ 127–
`128). Specifically, Petitioner contends that Ping provides equations from
`which parity bits p can easily be calculated from information bits d, and that
`one of ordinary skill in the art would recognize that “message bits” and
`“information bits” are synonymous. Id.
`
`As for the Tanner graph, Petitioner addresses the three elements but in
`an order different than that listed above in the claim construction section.
`For the element “[3] a parity bit is determined as a function of both
`information bits and other parity bits as shown by the configuration of nodes
`and edges of the Tanner graph,” Petitioner asserts that Ping teaches a two-
`stage, low-density parity-check (LDPC)-accumulate code where the value of
`one parity bit is used in the calculation of the next parity bit. Id. at 27, 48–
`50; see also id. at 51–52 (maintaining that Ping’s inner coder is an
`accumulator).
`
`The next element of the Tanner graph addressed by Petitioner is “[1] a
`graph representing an [irregular repeat accumulate] IRA code as a set of
`parity checks where every message bit is repeated, at least two different
`subsets of message bits are repeated a different number of times.” Pet. 50–
`54. Petitioner asserts that a particular code may be represented as matrices
`or as a Tanner graph, with those being two ways of describing the same
`thing, and contends that the proposed combination would have been
`understood by one of ordinary skill in the art to correspond to the claimed
`Tanner graph. Id. at 52–54.
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`Petitioner contends that, “[i]n Ping’s Hd matrix, every column
`
`corresponds to an information bit (di) and every row corresponds to a
`summation
`” and that one of ordinary skill in the art would have
`understood that the summations are computed as the first stage of computing
`the parity bits in Ping. Id. at 31, 32. According to Petitioner, “Ping’s outer
`LDPC code is regular because each column in Ping’s generator matrix Hd
`contains the same number of 1s – exactly ‘t’ 1s,” and notes that “Ping thus
`states that matrix ‘Hd has a column weight of t . . . .’” Id. at 41 (quoting
`Ex. 1003, 38). Petitioner cites MacKay for teaching that “[t]he best known
`binary Gallager codes are irregular codes whose parity check matrices have
`nonuniform weight per column.” Id. at 41 (quoting Ex. 1102, 1449)
`(emphasis in original).
`
`Petitioner reasons that, “[b]ecause MacKay teaches that irregular
`codes perform better than regular codes, one of ordinary skill would have
`been motivated to incorporate irregularity into Ping.” Id. at 41. Petitioner
`maintains:
`It would have been straightforward for a person of ordinary skill
`to change Ping’s generator Hd matrix such that not all columns
`had the same weight – e.g., setting some columns to weight 9 and
`others to weight 3, as taught by MacKay. (Ex. 1002, p. 1451.)
`This change would result in some information bits contributing
`to more outer LDPC parity bits than others, and would have made
`Ping’s outer LDPC code irregular. . . . Moreover, MacKay’s
`teaching that the best performing LDPC codes are irregular
`would also have made this modification obvious (and desirable)
`to try. (Ex. 1002, pp. 1449, 1454, “The excellent performance of
`irregular Gallager codes is the motivation for this paper….”)
`(Ex. 1004, ¶116.)
`Pet. 42. Petitioner notes that Ping credits a reference written by the author
`of MacKay as having creating “revived interest in the low density parity
`
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`check (LDPC) codes originally introduced in 1962 by Gallager.” Id. at 39
`(quoting Ex. 1003, 38).
`
`Petitioner further contends that, “even if Ping standing alone is not
`understood to teach, or render obvious, repeating information bits, doing so
`would have been obvious in view of Divsalar’s explicit teaching of repeating
`bits.” Id. at 44. Petitioner also argues that “[o]ne of ordinary skill would
`have been further motivated to implement Ping using the repeater of
`Divsalar because this implementation would be both cost-effective and easy
`to build,” and that the similarities between Ping and Divsalar provide
`additional motivation to combine the references teachings. Id. at 44–45.
`
`Thus, argues Petitioner, the combination of Ping, MacKay, and
`Divsalar teaches an irregular repeat accumulate code where message bits are
`repeated and at least two different subsets of message bits are repeated a
`different number of times. Id. at 52 (citing Ex. 1004 ¶ 139).
`
`Lastly, Petitioner contends that Ping teaches the Tanner graph
`requirement of “[2] check nodes, randomly connected to the repeated
`message bits, [which] enforce constraints that determine the parity bits.” Id.
`at 54–57. Petitioner points to Ping’s Equation (4)
`
`
`as teaching check nodes constraining the relationship between information
`bits and parity bits. Id. at 54–56. Petitioner further maintains that Ping,
`using Divsalar’s repetition, teaches that the check nodes are randomly
`connected to repeated message bits. Id. at 56–57.
`
`We now turn to Patent Owner’s arguments. Patent Owner first argues
`that MacKay fails to disclose the irregularity of claim 11, namely
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`irregularity in the number of message (information) bits repeated in a coding
`operation. See Prelim. Resp. 8–9. Specifically, Patent Owner asserts that
`Petitioner fails to identify any “instance of nonuniform weight per column
`among information bits.” Id. Petitioner’s articulated ground, however, is
`based at least on the application of MacKay’s irregularity into Ping’s
`generator Hd matrix making the outer LDPC code irregular. Pet. 41–42
`(citing, inter alia, Ex. 1004 ¶¶ 114–116); see also Pet. 34 (Petitioner arguing
`“MacKay’s nonuniform weight per column ensures that some information
`bits contribute to more parity bits than others.”). Patent Owner’s argument
`that MacKay standing alone lacks the irregularity of claim 11 does not
`persuade us that Petitioner incorrectly asserts that the combination of
`references would result in that subject matter.
`
`Patent Owner also argues “the petition incorrectly addresses only a
`portion of Ping’s parity check matrix Hd, rather than the parity check matrix
`H.” Prelim. Resp. 9. Accordingly, Patent Owner argues “Ping’s parity
`check matrix H already includes nonuniform weight per column—i.e., the
`‘irregularity’ of MacKay.” Id. Based on Patent Owner’s interpretation of
`the structure of parity check matrix H as being [Hp, Hd], and Patent Owner’s
`allegation regarding Hd that “[t]he only value of t disclosed by Ping is 4”
`(Prelim. Resp. 10–11), Patent Owner contends that matrix H has column
`weights as shown in a diagram from page 11 of the Preliminary Response,
`which is reproduced below.
`
`17
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`
`
`Id. at 11, 14. Patent Owner concludes “Ping discloses a parity check matrix
`with different numbers of ones per column—i.e., different column weights
`[weight 2, weight 1, and weight t = 4].” Id. at 11. Thus, Patent Owner
`argues that there would be no motivation to modify Ping to include
`“irregularity” when Ping “already includes the aspects identified in
`MacKay.” Id. at 14–15.
`
`Patent Owner’s argument does not address directly Petitioner’s
`articulation of the ground. Petitioner does not utilize Ping’s entire parity
`check matrix H in its analysis; rather, Petitioner notes that the Hd matrix is
`part of Ping’s “parity check” matrix H. Pet. 42. Petitioner maintains that,
`“[b]ecause Ping’s Equation (4) uses the Hd matrix to produce parity bits
`from information bits, it is a ‘generator matrix.’” Id. (citing Ex. 1003, 38).
`Petitioner asserts that “Ping’s outer LDPC code is regular because each
`column in Ping’s generator matrix Hd contains the same number of 1s –
`exactly ‘t’ 1s,” and notes that “Ping thus states that matrix ‘Hd has a column
`weight of t . . . .’” Id. at 41 (quoting Ex. 1003, 38). As such, we do not
`agree that matrix Hd from Ping, as cited by Petitioner and as forming the
`basis of the articulated ground, already includes “irregularity” in the manner
`suggested by Patent Owner. We understand Petitioner’s combination as
`relating to the specific application of MacKay’s “non-uniform column
`weight” to Ping’s matrix Hd (see Pet. 42–43), not a generic application of
`
`18
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`IPR2017-00700
`Patent 7,421,032 B2
`
`“irregularity” to Ping’s teachings as a whole. Accordingly, Patent Owner’s
`arguments do not undermine Petitioner’s stated motivation to combine
`MacKay with Ping.
`
`Patent Owner additionally argues “nothing in the references teach
`such a specific modification” of only Ping’s “submatrix Hd” and that
`“MacKay says nothing about modifying a specific portion of a parity check
`matrix to provide a subset of columns with nonuniform column weights, let
`alone doing so for a portion specifically corresponding to information bits.”
`Prelim. Resp. 12; see also id. 15–16. Nevertheless, Petitioner shows
`persuasively, on this record, that MacKay “teaches how to make LDPC
`matrices ‘irregular’ by implementing a ‘nonuniform weight per column.’”
`Pet. 41 (quoting Ex. 1102, 1449). Petitioner cites a specific example in
`MacKay where a matrix “has columns of weight 9 and of weight 3.” Id. at
`41–42 (quoting Ex. 1102, 1451 and citing Ex. 1004 ¶ 115). In light of this
`evidence, we agree that an ordinarily skilled artisan would have known how
`to add nonuniform column weights from MacKay to the uniform column
`weights in Ping’s matrix Hd.
`
`Having considered Petitioner’s and Patent Owner’s arguments and
`evidence, we determine Petitioner has established sufficiently at this stage
`that Ping, MacKay, and Divsalar teach every limitation of claim 11.
`Petitioner also has provided, on the current record, a sufficient rationale for
`its proposed combination. Thus, for the foregoing reasons, Petitioner
`demonstrates a reasonable likelihood of prevailing in showing that claim 11
`would have been obvious over Ping, MacKay, and Divsalar.
`
`19
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`5. The Alleged Obviousness of Claims 12 and 14–16 Over Ping,
`MacKay, and Divsalar
`The remaining claims subject to Petitioner’s first ground, claims 12
`
`and 14–16, each depend directly or indirectly from independent claim 11.
`
`Dependent claim 12 recites that “the encoder [of claim 11] is
`configured to generate the collection of parity bits as if a number of inputs
`into nodes vi was not constant.” Ex. 1001, 9:35–37. Petitioner relies on
`MacKay for the teaching of this limitation, equating nonuniform column
`weight with the “not constant” aspect of the claim. Pet. 58–62. Petitioner’s
`analysis, including the reasoning to combine the references’ teachings, is the
`same or similar to that regarding claim 11 and the application of MacKay’s
`teaching of “nonuniform column weight” in the combination of Ping,
`MacKay, and Divsalar and specifically to make Ping’s matrix Hd
`nonuniform. Id. at 60. Patent Owner again argues that Petitioner’s reference
`to only Ping’s matrix Hd, rather than H, is flawed. Prelim. Resp. 21
`(“Petitioner’s attempt to apply MacKay’s ‘nonuniform row weights’ to Hd
`(see Pet. at 61-62) repeats the errors discussed above in Section III.A.2, and
`so should be disregarded for similar reasons.”). Patent Owner also argues
`that Petitioner fails to provide a reason to modify the references with regard
`to this claim but does not acknowledge Petitioner’s statements on pages 60–
`61 of the petition. We again do not find Patent Owner’s arguments
`persuasive, and determine, on the record before us, that Petitioner has
`demonstrated a reasonable likelihood of prevailing in showing that claim 12
`would have been obvious over Ping, MacKay, and Divsalar.
`
`Patent Owner does not address separately Petitioner’s explanations
`and supporting evidence regarding claims 14–16. See Prelim. Resp. 21–22.
`
`20
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`Based on the record before us, Petitioner has demonstrated a reasonable
`likelihood that it would prevail on its assertion that claims 14–16 would
`have been unpatentable over Ping, MacKay, and Divsalar. See Pet. 62–64.
`
`C. The Alleged Obviousness
`of Claim 13 Over Ping, MacKay, Divsalar, and Luby97
`Dependent claim 13 specifies that the encoder comprises a
`
`low-density generator matrix (LDGM) coder and an accumulator. Ex. 1001,
`9:38–45. Petitioner, relying on Luby97 for the teachings of receiving
`message bits in a stream (Pet. 69), provides citations to the prior art and
`declaration testimony to support the contention that Ping, MacKay, Divsalar,
`and Luby97 teach the limitations of claim 13 and would have rendered
`obvious the subject matter of the claim. Id. at 64–71 (citing Ex. 1004
`¶¶ 172–187). For example, Petitioner provides testimony that Ping’s matrix
`Hd is a low-density generator matrix as recited in dependent claim 13. Id. at
`67–68; Ex. 1004 ¶¶ 179–181. Although Patent Owner argues that this
`evidence is not sufficient as “Ping never identifes [sic] Hd as a generator
`matrix,” Prelim. Resp. 22, at issue is whether Petitioner likely is to prevail in
`showing that the references teach the limitation to a person of ordinary skill
`in the art, and not whether the reference expressly uses the term low-density
`generator matrix or identifies matrix Hd as such.
`
`We determine, on the record before us, that Petitioner has presented
`sufficient argument and evidence to support the finding that it will prevail in
`showing that Ping teaches the low-density generator matrix limitation of
`claim 13, and that Petitioner has met its burden of demonstrating a
`likelihood of success in showing that claim 13 would have been obvious in
`view of Ping, MacKay, Divsalar, and Luby97.
`
`21
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`D. The Alleged Obviousness
`of Claim 17 Over Ping, MacKay, Divsalar, and the Pfister Slides
`Petitioner’s argument for dependent claim 17, which adds the
`
`requirement of a second accumulator, relies on the Pfister Slides (Ex. 1022)
`to teach the additional limitation. Pet. 71–72. Patent Owner argues that
`Petitioner has failed to establish that the Pfister Slides qualify as prior art.
`Prelim. Resp. 24–27.
`
`Petitioner contends that Paul Siegel presented the Pfister Slides at the
`Allerton Conference in September 1999. Pet. 37–38 (citing Declaration of
`Paul Siegel, Ex. 1023, 3). Patent Owner correctly argues that the Petition is
`devoid of any explanation or argument as to why or how the Pfister Slides
`qualify as prior art. Prelim. Resp. 24–25. Indeed, the Petition makes no
`attempt to show how the Pfister Sl
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