/2/ '>Y°>'
`
`EESEECTRU
`
`
`
`M,
`
`E'MI\II.
`PERVASIVE N§SlIAS|VEI
`
`
`
`
`
`
`
`R:T:I::Icr:RI:tI QR-RT-SQ
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`‘F... 1,
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` A
`ENGINEERING
`PERIODICAL
`
`
`
`QDISPI-AV
`"?
`
`
`
`CCTOBER 1992
`
`THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS. INC.
`
`SONY EX. 1011
`SONY EX. 1011
`Page 1
`Page 1
`
`

`
`SONY EX. 1011
`SONY EX. 1011
`Page 2
`Page 2
`
`

`
`—
`3 Newsrog
`6 Forum
`
`
`
`anPmpullimlummm
`
`7 Calendar
`
`8 Graphics
`
`11 Innovations
`
`12 Books
`
`19 legal aspects
`74 Software reviews
`
`78 EEs’ tools & toys
`90 Technically speaking
`
`92 Scanning THE lNS'i‘l'I'UTE
`
`92 Coming in Spectrum
`
`COVCTZ Electronic messages travel over a global
`network unbounded by time zones, distance or political
`entities in Gus Sauters conceptual illustration. With email.
`an engineer can communicate with a colleague halttmy
`around the world as easily as with a co-worlrer down the
`hall. The technology, still in its lnlancy. is changing society
`as well as business. Spectrum's Special Report on e-mail
`begins on p 22.
`
`IEEE SPECTRUM (ISSN lI01&9235}ls published nlonthly tu The
`Institute or Electrical and Electronics Engineers Inc All rights
`reserved. © 1992 by The Institute of Electrical and Electronics
`Enoirroo'slnc.345East4ittiSt..NewhJrlt.ttlr! reorrusacaue
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`theMapazlnePublishersotArnerica.andttte5or:letyol National
`Association Publications
`
`66 The art of architecting
`complex projects
`By EBEHHARDT RECHTIN
`
`How a system is created, designed. and
`built blends an and engineering. NASA's
`Deep Space Network is the product of
`such a process. Here, great antennas
`peer into space from its Canberra.
`Australia, station. The article describes
`the architecting process and provides
`additional etramples
`
`SPECTIIAL LlNE‘3.
`
`21 Challenges to
`management
`By DONALD CHRTSTIANSEN
`"Scientilic managernent“ gives
`ambiguous guidance today. Nevertheless
`managers have to select among
`traditional. perhaps outmoded, concepts
`and contemporary techniques. perhaps
`lads to develop a sell-consistent
`management process
`
`IEEE SPECTRUM OCTOBER 1952
`
`EDIIDR AND PUBUSHER7 Donald Chrisliansen
`MANAGING EDITOR: Athod Flosenblatt
`
`SENIOR TECHNICAL EDIFDR.‘ Gadi Kaplan
`SENIOR EDITORS: ‘tinny E. Bell. Richard
`Cornerlord. Tekla 8 Perry. Mishael .1
`Riemnman. George E Watson
`SENIOR ASSOCIATE EDIIDRS John A. Adam.
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`HE.4DOUAI?TE3S.' New tbrlr City 212705355
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`tfltisseldorllr Robert lngersol (Bonn); John Mann
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`(Tokyo): Krnr Nair-Hleon (Seoult Chris Brown
`ltarlterlz Peter Iswrmegtltorro Toner Tow
`Heaty (Sydney. Australia Christopher Trump
`(Toronto): Axel de Tristan (Rio de Janeiro):
`ltevtrt L. Sell (Houston)
`
`CHIEF COPY EDITOR: Margaret Eastman
`GOP! EDITOR: Sally Cahur
`EDITORIAL RESEARCHER: Alan Gardner
`
`CONTRIBUTING EDITORS: Karl Esch. Ronald It
`Jurgen. Michael F. Weltt
`EDITORIAL SUPPORT SERVICES:
`Rita Holland (Mana
`)
`EDITORIAL ASSIS
`: Ramona Foshr. Desiree Noel
`DESIGN CONSULIJANI.‘ Gus Sauter
`
`OPEIWTONS DIRECIDH.‘ Fran Zapptllla
`BUSINESS MANAGER.‘ Robert T. Ross
`Pfl'.lDUCIl'0N AND UUALITY CONTROL:
`Carol L. White (Director)
`EDITORIAL PRODUCHON:
`Marcia Meyers (Manager)
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`ASSOCIATE PUBLISHER: \Nlllam R. Saunders
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`MAIL UST SALES: Shelly Newman (Manaoatl.
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`Theresa Fitzpatrick (Manager). Francasm Siltestrl
`MARKETING DIRECTOR: Arthur C. Nico
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`MARIGEIWG SERVICES‘ Eric Sortrttg (MrnI'llstr'm')
`ADMINISIRANVE IGSISKNT ID THE EDIIDR
`AND PUBLISHER’ Nancy 1'. Harrtrrlan
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`Advisory Board
`CHAIRMAN.‘ G.P. Rodrigue
`Charles IL Alaander. 3 Leonard Carlson, Donald
`Flacltenstein. Ruben W, Lucky. Irene B. Peden. Gary
`R Spltmr. Jerome .1 Sarah. William R Tartltabary
`
`Editorial Board
`CHAIRMAN: Donald Christiansen
`Robert A Bell. Dennis Bodson. Kjell Carlson. W.
`t3err1ardcarlson.JarnesE. Ca*nes.PalatrltCtiahr-
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`Ft Currie. Robertl’.Darirlson.llIurrayEdert.Altarrltlt5.
`RobertR.Johrtsorr.TedCttenis.tl'licttaelS|’.l.rrcas
`Isugio Malrimoto. Edith W. Martin. Bruce C Mather.
`M. Granger Morgan. Dand It Ratterson. Altred R.
`Potvin.W.DaridPricer.BeltyPri1oe.lilbA.FlIeroa
`Bruce I1 Shriver. Stephen [1 welnstein
`
`SONY EX. 1011
`Page 3
`
`

`
`Fast computer memories
`
`Designers are searching
`for new DRAM technologies
`to reduce memory access
`time and so unleash
`computer performance
`
`I the price-to-performance
`ratio of computer systems
`is to keep improving. the
`gap in speed between pro-
`cessors and memory must
`be closed. Processors per-
`form at their peak only
`when the [low of instruc-
`tionsanddatairornrnemoryisfastandum
`faltering.
`An ever-flowing stream is particularly
`necessary to reduced-instruction—set com-
`puting (RISC) processors. which have be-
`come very popular clilrirg the last few years
`A heavily pipelined RISC processor can ex-
`ecute an instruction every clock cycle,
`demanding a lot of the memory syste.
`Both superscalar processors. with their mul-
`tiple functional units, and multiprocessor
`' machines make even greater demands on
`memory systems.
`Nor is the centml processing unit (CPU)
`the only consumer of memory band-
`width. Computers now are expected to
`beeasiertouseandmorecapablethan
`their predecessors. and some of the
`new capabilities will require speedier
`memory. Examples include the rapid
`display of high-resolution graphics in
`true color. the recognition of speech
`
`back video and audio. and, ultimately,
`support of a
`environ-
`........ 1.. M... ..... .... ......
`buffer memory for messages moving
`over the mirltigigabit-per—second net-
`workseirpectedinthenearfuture.
`These lofty I/0 ambitions all
`involve
`processing and moving large amounts of
`data. On topofeverrfaster CPUs, they will
`strainbothrnernorycapacityandmemory
`bandwidth.ButtbeaooepteddynamicRAM
`(DRAM)architecturesandsolution.shave
`beenpushedtotbeirtirnits.Abasicclrange
`inarchitectureseernstheonlywaytoob-
`tainanurgentlyneededincreaseinrnenw
`rvspeed-
`'l'heneedforclrangehasslruckanumher
`
`Ray Ng Sun Microiystems Inc
`
`of chip makers. beunrse innovative architec-
`tures distinguish a variety of recent high-
`speed DRAMS. which go by such names as
`synchronous. cached, and Rarnbus DRAMs.
`The newcomers may be usefully surveyed
`froma system perspective. tosee how they
`may solve dedflfl lJl'0b|ems. particularly with
`regard to main memory.
`in the familiar
`IEIIII LIIE. Till now,
`stored-program computer described by von
`Neumann, the processor has been connect-
`ed direetly to memory (as well as to
`inputloutput). From this model, a hierarchi-
`cal memory system has evolved in which a
`little. very fast memory is placed very close
`to the processor and fed by lots of slower
`memory farther away from the processor
`[Fig.1]. This hierarchy, which is used in al-
`most all computer systems today. reflects
`one of computer desigrfs truisms, “fast
`memory is expensive and slow memory is
` .Il
`Attbefiratleveloftlrehierarehyare the
`processor-'s internal registers. Access to
`these registers is very fastbecause they are
`on the processor chip. However, their num-
`ber is lirnited by the available chip area. or
`“real estate."
`At the second level, between the proces-
`sor and slower main memory. is a cache-a
`small, very fast memory. The cache is load-
`
`Processors can perform
`their best only if
`the supply of instructions
`and data is fast
`'
`and unfaltermg
`
`edwithcopiesoitboseblocksofdatastored
`inmain memory that the processorismost
`likelytowantfortheoperationitiscurrently
`
`from 16to64 bytes.)
`lftheprocessoriindstbedataitwantsin
`thecache (referredtoasacache hit). their
`totheprucessoritwilllookasifrnainmem
`oryisasfastascache. Butiithe processor
`doesnotfindwhatitneedsirrrnchdacacbe
`miss), then the block containing the miss-
`ingdatamustbebroughtinfromrrrair1rnen1-
`ory. slowing down the system.
`Cachesusualiyprovideaspeedupberzuse
`
`they exploit a general characteristic of pro-
`grams: locality in space and time. Spatial lo-
`cality indicates that ii a location in memory
`is accessed. then others nearby will proba-
`bly be accessed soon;
`temporal locality
`means that if a location in memory is ac-
`cessed once. then it will probably be ac-
`cessed again soon.
`One problem with caches is that. in order
`to be effective. they require very fast RAM:
`tbatrunataboutthesamespeedasthepro-
`cessor; and win}: static RAMS (SRAMS) can
`deliver the required speed, they are expen-
`sive. Also. caches must keep track of which
`memory blocks are in the cache and what
`their state is. and therefore require a spe-
`cial controller and a tag memory that add
`complty and take up precious board real
`estate. All the same, caches are popular.
`It is possible. too. to build systems with
`more than one level of caching. using on- and
`off-chip memory. Many modern pmcessors
`have on-chip caches, for both program irr-
`structions and data, that are closer than an
`extemal cache and so faster to access. But
`like the number of registers. the (aches have
`to be small because chip real estate is limit-
`edandinmanysystemstheyaresup-
`plemented with an external cache. The in-
`ternal cache is referred to as first-levelcache
`and the external as second-level.
`The third level of the hierarchy is
`main memory itself. Main memory is
`used to store programs and data, and
`as a source of input and destination for
`output. Typically, this memory is much
`larger than cache and is constructed of
`DRAMs. which are slower than the
`SRAMs but also less expensive.
`Tire fourth level of the hierarchy is
`mass storage. Today magnetic-disk
`storage is ubiquitous. lt is used to im-
`plement a technique called virtual
`memory, which fools the processor into
`thinking the main memory '3 much larg-
`erthanistbecase. Withviru.1almemory, the
`processor’s address space is divided into
`blocks of fixed size. calledpages. Pages are
`much larger than cache blocks. usually 4-
`8K bytes.
`Disk bears much the same relationship to
`main rrremory as main memory does to
`cache. P8863 are called from disk and placed
`in main memory when they are needed or
`returriedtodiskwhenttieyarenot. mwith
`cache. the principle otlocality is basic. To
`mairrtainorderinthe system, arnernory
`management unit (MMU) keeps track of
`which pages are in main memory and what
`
`0018-9235I'92.’$3.00©i992 IEEE
`
`IEEE SPECTRUII OCTOBER 1992
`
`SONY EX. 1011
`Page 4
`
`

`
`Level 1
`
`Level 2
`
`Level 4
`
`Level 3
`
`[1]Inmostconrputers)stenrsbday.thetolul
`memory consists afa hierarchy ofm_edr'a.
`Passmgfromtlreiaplobottamoftlrchuemr
`chy, thedensityoftlwmedmm (theamount
`ofdataitmn storzperumitana) increases,
`whilailsmadindelinenirgdataaudriscost
`per bit decrease. Some new dynamic RAM
`(DRAM) teclrnologies aim atsinrplajrjrivvgtlris
`himzrchy by speeding upnmin memory to the
`point where theneedjbra separate, external
`cache is moot.
`
`their status is.
`As with a cache miss, performance falls
`off whenever a page is not in main memory
`when needed (a page fault). The penalty is,
`however. higher because mechanical disks
`are much slower than semiconductor main
`memory. Butdisksareverycheap.inl:erms
`of cost per hit, and can store vast amounts
`of data; hard disks today commonly store
`hundreds of megabytes, and the use of
`magneto-optical and optical discs capable of
`storins sisabvtes is smwins-
`Strictly speaking, there is a fifth level of
`storage. fordatathatwillnothe usedforan
`extended period of lime or whose impor-
`tance demands its preservation. This ar-
`chival storage oflaen consists of magnetic
`tape; of course, removable magietic and op-
`tical discs are also used for long-term stor-
`ageofprogramsanddsta. Thisstnragelevel
`has no impact onrun-time system operation
`and so will be ignored for now.
`IIII EIHT. Main memory is almost always
`implemented using DRAMS. which in both
`speed and price lag behind the SRAMs
`generallyusedfior cache. DR.AMsuse one
`transistor-tzpscrilnrpainreferredtoasacell,
`tostoreonehitat’iniormation.whi|eSRAMs
`useafour-orsix-transistorflip-floptostore
`eachbit.BecauseeachDRAMcellisvery
`small,DRAMscsnbemadeverydense;the
`densest DRAM now svailableisa 16M-bit
`part,whilethedensestSRAMisahout4M
`bits. The per-bit cost of SRAM. depending
`
`iv’
`
`3§—F&uoIIumtnnml'bI
`
`units speed, is 5-10 timesthatof DRAM.
`Howevenhecarnediechargeleaksaway
`£rorntheDRAM cell's capacitor, it musthe
`restoredbyperiodicrefreshiIig.Alsqtheact
`ofreadingaDRAMinvolvestransfer'ringand
`sensingmeredribblesofchargusinceeach
`readoperationdisturhsthecelloontentsit,
`toqrequiresthatthedatareadberestored.
`Forthesereasons.DRAMsarenotespec'nl-
`ly fast.
`ADRAMishuiltasasquareorrectangu—
`lar array ofcells [Fig. 2]; to read or write
`data.theprocessorsendsanaddresstothe
`DRAM, which typically it multiplexes, sup-
`plyimfi1sttherowaddresa.thentheoohmm
`address. For currently available DRAMs,
`thetimeittakesarowaddresstosocessa
`oellisaboutlo-80ns,foracoh1mnadd:ess.
`about 20-40 ns, andtheprecharge timeis
`ahout30-50ns.Thusthecycletime(the
`minimumamountof time between memo-
`ryaoce-ssesbytheproeessor)isahaut]10—
`150ns.lnoontrsst,thecellsinsmallCMOS
`SR.A.Msmaybeaccessedevery8ns;larg-
`er SRAMs have a longer access time of
`about l5ns.
`’lbraisetheiroperal:ing speed. DRAM:
`haveaspecialopers1.ingmodetlmtlakesad-
`vantage of their internal row-and-column
`structure.lcnownaspagemode.Inthis
`mode,wl1enanentirerow(orachippage,
`hutnottoheeonfirsedwiththevirtuaimem-
`ory psgefisreadintothesense amplifiers,
`theuseramkeeptherowacti'veandmere-
`
`lychanaeoolumnaddressestoaooessallthe
`data.AsIongastheaccessesremainintl:e
`P308. the DRAM can work faster. For cur-
`re_rrt.DRAMs,thepage-modecycletime(or
`rmmmum time between column addresses)
`isahout_40-50 ns [Fig. 3].
`IPEBIII lfllll IEHIY. A main memo-
`rysystemhasthreecrucial attributes: size,
`latency,andthroughput.Sizeisaffectedby
`density. orthenumberofbitsthatcanhe
`paclaedinlanagivenarea;thehigi'nertheden-
`sity‘,tl'rebetter. latencyishowlongittakes
`ford:rtatohedelivetedafterithasheenre-
`quested,andiscloselyrelatedtoaDRAM's
`access time; the shorter the latency. the
`fastertheDRAM.Througliputisarneasure
`othowmuchdstaranbedc-Jiveredinagiven
`periodoitime,andiscloselyrelatedtothe
`DRAM cycle time; a higher throughput
`meansthataDRAMde1ive1smo1edataper
`tin1einterval.WhilethedensityofDRAMs
`hasheenquadruplingmughlyeverythree
`years. neither theiraooessnortheircycle
`tirneshaveimpmvedssrapidly.Impmv'mg
`thelatencyandthmughputol'mainmemo-
`ryistliefocusofattenlionamongmemory
`systemdesigners.
`Pagemodemay reducelatencyandin-
`ctessethroughput.butonlyifthereisslot
`of sequentiality in the memory reference
`stream;iornnrltiprocessorsystems,thisis
`notlruecacheadoagoodjobofisolaiing
`the processor from relatively sluggish main
`memory,butthereisonlysomuchaesche
`
`
`
`A
`
` Source. Touhitll COTDWBWJ"
`
`[2]Inat3pimIDRAM,suchasth¢4M-hy4-bufbshabacornflafi. fluadualmcnwflaflflll
`inthebnmnightisamessedflrmugrhpatudwecesmcmwandwiumnaddnsscs. Thertiw
`addnssmusesthedaminthcmwmbemadruhthesnrse-anrplrjiuf/Oyztefimu which
`thewlumnaddnudewdarsekdstheLh?mrd.mmhbk.wb¢pMcediuHwdamowbufl&x
`
`37
`
`SONY EX. 1011
`SONY EX. 1011
`Page 5
`Page 5
`
`

`
`l
`
`cando.‘I‘hetimeittalrestoserviceacache
`miss is directly rehted to the main memory’s
`latency so, with increasing processor
`speeds, cache misses have an ever greater
`impact on system performance, even when
`the hit-to-miss ratio is high.
`IAIIIIII Ilfllllll. The most common
`method of increasing memory system
`throughput is interleaving [Fig. 4]. The idea
`here is to use not one. but several identical
`arrays of memory, or banks.
`in its simplest form. interleaving spreads
`out the memory addresses so that adjacent
`addresses occupy adjacent banks. The mnn-
`berofbanksused, N, isa powerof2. Ifan
`address yields a remainder of 0 when divid-
`edbyN(oraddressmoduloN- 0), then
`itresidesirrbanlm; ifaddressmodulo N -=
`1, then it resides in bank 1, and so forth.
`The net effect at interleaving is to increase
`the memory bandwidth. or throughput. by
`afactorofllf: Nwordsarereadeachmem-
`ory cycle instead of only one. The N words
`are stored in a teflifier. freeing the memo-
`ry banks to process the next access. If the
`memory addresses accessed are mostly se-
`quential. this form of interleaving works
`well; if they are not, it does poorly.
`Anotberformof while more
`
`Normal mode
`
`complex. worlrsbetteriornonsequential ac-
`cesses. kwiththesimplease, rnemoryis
`dividedintoNmodu1esand addressesare
`assigned to banks in the same way. In this
`case. however, the memory controller takes
`on the additional responsibility of schedul-
`ing accesses. It looks at each separate re-
`questsndschedulesitinsuchawayasto
`make maximum use of the data bus. The
`controller's objective is to overlap operation
`between memory banks as much as
`possible.
`Even though interleaving is popular and
`helplul. it runs irlto several problems. For
`one, filling a wider bus may require too much
`memory. Also, to maintain the interleave,
`memory has to be upgraded in increments
`ofN.Iastly.interleavingcanresultinbullry,
`complex memory systems.
`While all these techniques have been used
`to improve systems perfomrnnce. they will
`not be able to cope with the faster pro-
`cessors in the offing. A new memory ar-
`chitectnre is needed, and in addition. the
`physics d the interconnections must he lrept
`in view.
`
`Designers of truly high-speed memory
`systems have to treat memory paths as
`transmission lines: their impedance has to
`
`- Valid data
`.How
`-WW“
`- Don't care
`RT5=mwamess sIrobe_;_CAS=coturnnaccesssrrooe;VTE=wrhsenab|e.
`D0 = data inpulfoutpul; OE = output enable.
`
`I Undefined
`
`/3}I'|0fl0"'W1DRAM_'lfldO|31¢. d¢fi!b¢00!!I¢$tAflh'dmI1yafl¢rbothmwaudcoIumnad-
`dressesIranebeensu1:,0lred.Ho:veae:; wheualltiwdatamededissloredinthesammw,a
`pagenwdespaerismatkrshychangirtgthe column address only: aflereach change, the newly
`nquesteddatawouifiidmdmmoinsualidunfiltkenutwlumnaddmssrsnceived.
`
`38
`
`be carefully controlled and paths have to be
`correctly terminated to reduce reflections.
`As for the parasitic capacitance and induc-
`tance of the U0 drlverlreceiver, the device
`packaging. and the printed-circuit board's
`traces, they have to be minimized and their
`effects taken into account.
`High throughput demands high transmis-
`sion rates. Since traditional TTL- and
`CMOS-level drivers and receivers cannot
`achieve the speeds necessary. new IIO
`drivers with low-voltage swings. carefully
`controlled slew rates, and the abilityto drive
`a tenninated bus are required.
`In selectinga high-speed interlace. amm-
`berofrelatedfactorshavetobec--nsidered:
`the interface should be simple. effective,
`economical, widely supported, and easy to
`use, and should conserve power.
`As speed increases. so. too, does the sig-
`nificance of schemes for distributing clock
`signals. Sophisticated techniques will have
`tobe usedto control clock skew—the differ-
`ent times of arrival of the same clock signal
`at scattered points in the system. Also, the
`delay introduced by the clock distribution
`network within each chip has to be con-
`trolled. Both skew and delay should be kept
`as low as possible.
`New clock architectures should also be
`considered. Instead of distributing a central
`clock to all the chips in the system (global
`synchronization), it may pay to ship a copy
`of the clock along with the data ( source syn-
`chronization).
`DIE OITIIIS. Several new high-speed
`DRAMs solve some of the foregoing prob-
`lems. Synchronous DRAMs resemble con-
`ventional DRAMs, and so are merely an
`evolutionary step in DRAM technology.
`They differfrom earlyparts in that allinputs
`and outputs are referenced (synchronized)
`to the rising edge of a clock pulse. Another
`difference is that, when a read operation is
`performed. more than one word is loaded
`intoahigh-speedshiftregister; thesewords
`are shifted out, one word per clock cycle.
`As a result, synchronous DRAMS can have
`very high burst rates. (Note that some early
`synchronous DRAM designs use an inter-
`nallypipelined design that operatesonasin-
`gle word only.)
`A synchronous DRAM running at 100
`MHZ has four times the bandwidth at’ page-
`mode DRAMs. However. access times are
`no faster than for convenfional DRAMS.
`Some synchronous DRAMs do have a
`“wrap" feature, for servicing cache miss-
`es. They deliver a burst of perhaps four or
`eightcyclesofdata, withtheaddressedword
`appearing first, followed by the remainder
`of the blodr. and then wrap back around to
`the beginning of the block.
`A memory system built out of syn-
`chronous DRAMS has a peak GdeaD band-
`width equal to the system's clock frequen-
`cy multiplied by the number of data hnes in
`the system's bus. While the bandwidth ac-
`tuafly delivered will. of course, be less than
`this,
`the memory bandwidth is directly
`
`IBEE SPECTRUM OCTOBER 1992
`
`SONY EX. 1011
`Page 6
`
`

`
`'M]I:deri¢aw'1rgdiuid¢sarar'nareurorgH'ntrr
`b'IocIcsontIrebasiso_faddress rnoduleswre
`reanoiaderwhcutlraaddmsrkdioidadbytlu
`nunrberofbanks,N, IoheuNr'srrpowerof
`2).‘b¢causeflrrbaukscanb¢accesud£uocer-
`lapfivgfirslfion, flcmugirpur caubcgreatcr
`iilaarjaronsbrmkbyafirdbrof N.In!Iresr'nr-
`plcstschomr.alIbanlrsa1sacn'r:aiodsr'mui-
`trurwus1ylurocrnruuorrcavrtrolir'rrc.!ircirorrt-
`[m!saresiarodinrqgr'sters,avrdrIrcrqvisren’
`caadrvdsowcanseartirelynmlfipleradmrnitire
`syotuubrrslfdatarlmotsirrudaordacccssed
`fromcorrs¢cutiraeaddnss¢s,amoreoompla:
`firnnafwrtdavhefbadmujaflmosaodrbark
`bbecovrhnilcdseprrraielysoriratflrescquance
`inwhichthebanksdeliwrdamwthesskm
`busarnbahiloradlooflirniutkmrqghput.
`
`licensedtornanuiacturerscfDRAMsand
`applicanon-specificlCs (AS109). ‘Ibslfiba,
`Fujitsu. and NEC are currently sampling
`Rambus DRAMS. The Rambus interface
`cellisavailahlefromatewnslcvendors,
`and'Ihshiba|:lanstomakeASICversionsof
`the Rarnhusoontrnlleravailable.
`RamI.inlr'uanatternpttotahsorneot'lhe
`work done forthe Scalable Coherent Inter-
`face(SCl)andadaptittoruseasaDRAM
`
`requiredregisters, andtl1eelectr1'.calinter-
`face. whichisadi£fer'entialinter'lace.M1ile
`Ramlinlrdoesnotspecifydevicepinonisor
`boardlayout,itisinma.nywayssimilarto
`Rambus; thechiefdifferenceiatlratkanr
`Linlrisbasedonar'ing,ratherthanhus.to-
`
`to point—antl
`RAM are therefore point
`point-to-point connections can run faster
`thanbusedcomrections/I‘hedisadvantage
`of a ring topology is that the request and
`replypacketsmusttraversethcentirering.
`Eachnodeontlleringaddssomeannntd
`delay,sothe|atencycanbeveryhigh:Rs1n—
`Linlrallowsuptosdnodes.
`ItisanticipatedthattheRamLinkspecifi-
`cation will be an IEEE standard G’1596A)
`whenworlr'naoomplete.Novendorsourrert-
`lyofferaRaml.inlrpart.
`HITH llli. Main memory is the Sillsle
`rnostexpensiveiteminacomputersystern.
`'l'hecurrentcostofDRAMisaboutUS$30
`amegabyte.AtypicalPCtodayoomeswith
`ab0nt4Mbytese.:pandabletoperhaps16M
`bytesntypiarlhidr-endworkstationcornes
`withabout32Mbytes,andcanholduptn
`5l2Mbytes.DRAMsarecommodityparta
`whose price is driven by volume. Any
`DRAMenlmnoernemnn.1stofleraclearben—
`efitatasmallprice difference.
`AnyDRAMsolurionthatcanelirm'natethe
`needforacsche,yetoostlitt|eornomore .
`thanoonverrtionalDRAMs.oouldbeotuse
`in personal computers. low-end worksta-
`
`lIII‘l'IElIlII.RayNgisamemberof
`thetscim'n:alstatfofSunMicrosysternsInc..
`McuntzrinView,Calif..whueheisinvolved
`withthedevelopmentoimernorysystems
`for RISC-based workstations and future
`computer systems.
`9
`
`39
`
`SONY EX. 1011
`SONY EX. 1011
`Page 7
`Page 7
`
`proportional to the clock frequency.
`To derive the rnaxirnum benefit from
`these DRAMs. therefore, acomputerrnust
`be designed to run the memory system at
`ahighcloclrrate.'I'hisrequiresverycareful
`design. bntthehighburstrateofsomesym
`chrnnous DRAMs makes it possible to use
`narrower memory paths than would be re-
`quired for conventional DRAMs.
`At present, some vendors are sampling
`parts based on a synchronous DRAM ar-
`chitecture, and theloint Electron Device En-
`gineering Council Oedec) is preparing a stan-
`dardforthemthatwillbeavailsbletoany
`interested party.
`II TIEII III. The cached DRAM is a pro-
`prietary development of 'Iblryo's
`Corp.,fromwhichsamplesareavai1able. Be-
`causeacachedDRAMl:asasrnallSRAM
`cache inserted between its external pins and
`an internal DRAM. accesses that hit aloca-
`tioninthe cacbearemuchfastert.‘lmntypi-
`cal DRAM accesses. Also, the cache-fill
`bam‘lwidthisveryhiglrbecausethebuscon-
`treating the SRAM and DRAM is very wide.
`In system configurations where memory
`is connected directly to the processor.
`cached DRAM may replace the external
`cache. However.
`the memory controller
`mustperformthefunctionsofacachecon-
`troIlerandmaintainasetof12gR.I\Ms.
`Another proprietary scheme. Rambus
`from Rarnbus Int‘... Mountain View. Calif.,
`offers a complete and radical solution to
`building a memory system. Its specification
`describes the protocol, electrical interface.
`clocking scheme, the register set, device
`packaging and pinout. and board layout.
`
`Although its peak transfer rate is 500
`rnegabytes per second. actual memory
`bandwidthislessbocauseaddress.contrnl.
`anddataarealltransnritted overthesame
`setofwires.Tbebandwidthtbatisinfact
`achieved depends on two factors:
`the
`amount of data transferred during each
`transaction.and(sincethescherneinvolves
`cacl1ing)thehitrate.Thearnotnrtoiover-
`headforeachtr1msferisfin:d,sohuseffi-
`
`inga100percenthitrate,thepealrread
`handw-idtl1torthe4.5M-hitpartisabout360
`MbytesIsfior64-bytetranderB;fiorthe1BM-
`bit part. which is faster. it is about 400
`Mbytes/s. Bandwidth decreases if the hit
`rate or transfersizedecreases.
`WhatdoesRambusmeanforthesystem
`designer?Becauseeachchipisaninr:lepen-
`dententity.veryfewareneededtobuilda
`memorysysternanmbecauseeadrchiphas
`built-irrdeoodingandlritdetectionlogicthe
`memorycontrollercanbesimplenlfthehit
`rateishighenougir. itInayevenhepossi—
`ble to connect the processor directly to
`mernoryandeliminatethecache.Aspecial
`Rambus interface. containing the 1/0
`drivers. phase-locked loop, and miscella-
`neous logic.
`is needed to interface to
`Rambus.
`SinceRambusiatheoretica|lyacoolrbook
`solutiomthedesignerneednotworryahout
`
`issuesnhedetailshaveallbeentakencare
`of. But because each device does much
`more than an everyday DRAM. Rambus
`DRAMs may oostmore.
`Rambus is a proprietary technology
`
`M-Futoornpuurrrrunnriu