`Ex. 1017 / Page 1 of 5
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`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1017, p. 1
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`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1017, p. 2
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`Ex. 1017/Page 2 of5
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`Ex. 1017 / Page 2 of 5
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`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1017, p. 2
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`inteI®
`THE PENTIUM® FAMILY-A TECHNICAL OVERVIEW
`This article begins by presenting an overview of the
`Intel’s Pentium® processor family combines the per-
`Pentium processor. It then details the key technological
`formance traditionally associated with minicomputers
`features that enable the Intel solution to meet the mar-
`and workstations with the flexibility and compatibility
`ket's evolving requirements for high performance, con-
`that characterize the personal computer platform. De-
`tinued software compatibility, and advanced function-
`a.Iity.
`signed to meet the needs of today’s and tomorrow’:
`sophisticated software applications, the Pentium proc-
`essor extends the range of Intel’s microprocessor archi-
`tecture to new heights, blurring previous distinctions
`between hardware platforms and creating an entirely
`new realm of possibilities for notebook computers,
`desktop PCs, and servers.
`
`THE WORLD'S BEST PERFORMANCE
`FOR ALL PC SOFTWARE
`The Pentium processor family includes the highest per-
`forming members of Intel’s family of microprocessors.
`
`.
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`ICOMP®Index
`External BusInterface
`1110
`66 MHz
`1000
`60 MHZ
`815
`66/50 MHZ
`735
`60 MHz
`610
`50 MHz
`the system bus frequencies range from 50 MHZ to 66
`MHz, allowing cost effective system designs.
`
`P
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`F
`
`Pentium® Processor
`75/90/we/120/133coreFrequency
`133 MHz
`120 MHZ
`100 MHZ
`90 MHz
`75 MHZ
`
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`While incorporating new features and improvements
`made possible by advances in semiconductor technolo-
`gy, the Pentium processor is fully software compatible
`with previous members of the Intel microprocessor
`family-thereby preserving the value of users‘ software
`investments. The Pcntium processor meets the de-
`mands of computing in a number of areas: advanced
`operating systems, such as DOS‘. Windows‘, OS/2',
`and UNIX“; computing-intensive graphics applica-
`tions, such as 3-D modeling, computer-aided design/
`engineering (CAD/CAE), large scale financial analysis,
`high-throughput client/server, handwriting, and voice
`recognition; network applications; virtual reality; elec-
`tronic mail that combines many of the above areas; and
`new applications yet to be developed.
`
`The Pentium processor family was designed using an
`advanced process technology and has features that are
`less than a micron (one-millionth of a meter) in size.
`The Pentium processor (S10\60, 567\66) was devel-
`oped utilizing 5V, 0.8 micron technology, while the
`Pentium processor
`(6l0\75,
`735\90,
`815\lOO.
`l000\120, lll0\l33) was designed using 3.3V, 0.6 mi-
`cron and 3.3V, 0.35 micron technology.
`
`The increasingly improved Pentium processor family
`brings the users CPUs with higher frequencies, while
`
`November B95
`Order Number: 24323.-E02
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`F
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`1
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`THE PENTIUM® PROCESSOR:
`TECHNICAL INNOVATIONS
`A number of innovative product features contribute to
`the Pentium processor’s unique combination of high
`performance, compatibility, data integrity and upgrad-
`ability. These include:
`0 Superscalar Architecture
`0 Separate SK Code and Data Caches
`'5 Writeback MESI Protocol in the Data Cache
`0 Dynamic Branch Prediction
`0 Pipelined Floating-point Unit
`0 Improved Instruction Execution Time
`9 64-Bit Data Bus
`3 Bus Cycle Pipelining
`9 Address Parity
`0 Internal Parity Checking
`' Functional Redundancy Checking
`5 Execution Tracing
`0 Performance Monitoring
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`Ex.1017IPage 3 of5
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`Ex. 1017 / Page 3 of 5
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`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1017, p. 3
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`THE PENTlUl‘vil@ FAMlLY-A TECHNlCI-AL OVERVEEW
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`
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`inté®
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`0 IEEE 114-9.1 Boundary Scan
`0 System Management Mode
`* Virtual Mode Extensions
`' Upgradable With a Future Pentium OverDrive®
`Processor
`*' Multiprocessor Support
`
`In addition to the features listed above, the Pentium
`processor 75/90/ 100/120/ 133 offers the following en-
`hancements overlthe Pentium processor 60/66'
`° Dual Processing Support
`0 SL Power Management Features
`0 Fractional Bus Operation
`° On-chip Local APIC Device
`
`This improves performance without affecting compati-
`bility. In the case of more complex instructions, the
`Pentium processor’s
`enhanced microcode
`further
`boosts performance by employing both dual
`integer
`pipelines to execute instructions.
`
`Separate SK Code and Eats Caches
`Pentium processors include separated code and data
`caches integrated on-chip to meet performance goals.
`On-chip caches increase performance by acting as tem-
`porary storage places for commonly—used instructions
`and data, replacing the need to go off-chip to the sys-
`tem’s main memory to fetch information. The separate
`caches reduce bus conflicts and are available more often
`when they are needed.
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`Superscalar Architecture
`The Pentium prooessor’s superscalar architecture en-
`ables the processor to achieve superior performance by
`executing more than one instruction per clock cycle.
`The term “superscalar" refers to a microprocessor ar-
`chitecture that contains more than one execution unit.
`These execution units, or piplines are where the CPU
`processes the data and instructions that are fed to it by
`the rest of the system.
`
`The Pentium processor’s superscalar implementation
`represents a natural progression from previous genera-
`tions of processors in the 32-bit Intel architecture. The
`Intel486TM processor for instance, is,able to execute
`many instructions in one clock cycle, while previous
`generations of Intel microprocessors require multiple
`clock cycles to execute a single instruction.
`
`The ability to execute multiple instructions per clock
`cycle is due to the fact that the Pentium processor has
`two pipelines that can execute two instructions simulta-
`neously. The Pentium processor’s dual pipelines exe-
`cute integer instructions in five stages: prefetch, de-
`code], decode2, execute and writeback. This permits
`several instructions to be in various stages of execution,
`thus increasing processing performance.
`
`The Pentium processor also uses hardwired instruc-
`tions to replace many of the microcodecl instructions
`used in previous microprocessor generations. Hard-
`wired instructions are simple and commonly used, and
`can be executed by the processor’s hardware without
`requiring microcode.
`
`The Pentium processor’s code and data caches each
`contain 8 Kbytes of information and both are organized
`as two-way set associative caches—meaning that they
`save time by searching only pre-specified 32—byte seg-
`ments rather than the entire cache. Each cache has a
`dedicated Translation Lookaside Buffer (TLB) to trans-
`late linear addresses to physical addresses.
`
`The Pentium processor’s data cache is configurable to
`be “writeback” or “write throug ” on a line-by-line ba-
`sis and follows the MESI (Modified, Exclusive, Shared,
`Invalid) protocol. The “writeback” method transfers
`data to the cache without going out to main memory.
`Data is written to main memory only when it is re-
`moved from the cache. In contrast, the “write through"
`method transfer data to the external memory each time
`the processor writes data to the cache. The “writeback”
`technique increases performance by reducing bus utili-
`zation and preventing unnecessary bottlenecks in the
`system.
`
`To ensure that data in the cache and in main memory
`are consistent,
`the data cache implements the MESI
`protocol during reads and writes. This is especially im-
`portant in a multiprocessor environment.
`
`Dynamic ranch Prediction
`Branch prediction is an advanced computing technique
`that boosts performance by keeping the execution pipe-
`lines full. It is accomplished by predetermining the
`most likely set of instructions to be executed.
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`Ex.1017IPage 4 of5
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`Ex. 1017 / Page 4 of 5
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`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1017, p. 4
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`intel.
`To understand the concept better, consider a typical
`application program. After each pass through a soft-
`ware loop, the program performs a conditional test to
`determine whether to return to the beginning of the
`loop or to exit and continue on to the next execution
`step. These two paths are called branches. Dynamic
`branch prediction forecasts which 'oranch the software
`will require, based on the assumption that the previous
`taken branch will be used again. Pentium processors
`make prediction by using a Branch Target Buffer
`(BTB). Pentium processors also implement two pre-
`fetch buffers, one to prefetch code in a linear fashion
`and the other to prefetch code according to the address-
`es in the BTB. As a result, the needed code is always
`prefetched before it is required for execution. In addi-
`tion, the Pentium processors support more sophisticat-
`ed algorithms by using two level branch prediction.
`
`Pipe-lined Floating-Point Unit
`The 32-bit compute-intensive software applications re-
`quire a high degree of floating-point processing power
`to handle mathematical calculations. As the floating-
`point requirements of personal computer software have
`steadily increased, advances in microprocessor technol-
`ogy have been introduced to satisfy these needs. The
`Intel4S6 DX processor, for example, was the first Intel
`microprocessor to integrate math coprocessing func-
`tions on-chip; previous-generation Intel processors used
`off-chip math coprocessors when floating-point calcula-
`tions were required.
`
`The Pentium processor family takes math computation-
`al ability to the next performance level by using an
`enhanced on-chip floating-point unit that incorporates
`sophisticated eight-stage pipeline and hardwired func-
`tions. A three-stage floating—point instruction pipeline
`is appended to the integer pipelines. Most floating-point
`instructions begin execution in one of the integer pipe-
`lines, then move on to the floating-point pipeline. In
`addition, common floating-point functions; such as,
`add, multiply and divide, are hardwired for faster exe-
`cution.
`
`
`
`eta Bus
`Enhancer! 54-Bi
`The data bus is the highway that carries information
`between the processor and the memory subsystem. Be-
`cause of its external 64-bit data bus, the Pentium proc-
`essnr can transfer data to and from memory at rates up
`to 528 Mbytes/second, a more than five-fold increase
`
`THE PENTlUM® FAMILY-A TECHNICAL OVERVIEW
`
`over the peak transfer rate of the 66 MHz Intel DXZTM
`microprocessor (105 Mbytes/second). This wider data
`bus facilitates high-speed processing by maintaining the
`flow of instructions and data to the processor’s supers-
`calar execution unit.
`
`In addition to having a wider data bus, the Pentium
`processor implements bus cycle pipelining to increase
`bus bandwidth. Bus cycle pipelining allows a second
`cycle to start before the first one is completed. This
`gives the memory subsystem more time to decode the
`address, which allows slower and less-expensive memo-
`ry components to be used, resulting in a lower overall
`system cost. Burst reads and writes, parity on address
`and data, and a simple cycle identification all contrib-
`ute to providing greater bandwidth and improved sys-
`tem reliability.
`
`The Pentium processor also has two write buffers, one
`corresponding to each pipeline,
`to enhance the per-
`formance of consecutive writes to memory. Write buff-
`ers improve performance by allowing the processor to
`proceed with the next pair of instructions, even though
`one of the current instructions needs to write to memo-
`ry while the bus is busy.
`
`Data integrity and Error Detection
`Features
`
`Protecting important data and ensuring its integrity has
`become increasingly important as mission-critical appli-
`cations continue to proliferate. To ensure the Pentium
`processors’ reliability, Intel ran millions of simulations
`and tests. In addition, designers have added significant
`data integrity and error detection capability. Data pari-
`ty checking is supported on byte-by-byte basis. Address
`parity checking, and internal parity checking features
`have been added along with a new exception, the ma-
`chine check exception.
`
`Internal error detection places parity bits on the inter-
`nal code and data caches, translation look aside buffers,
`microcode, and branch target buffer. This feature helps
`to detect errors in a manner that remains transparent to
`both the user and the system.
`
`Furthermore, the Pentium processors have implement-
`ed functional redundancy checking to provide maxi-
`mum error detection of the processor and the interface
`to the processor. When functional redundancy check-
`ing is used, two Pentium processors act as “master"
`and “checker” respectively. The “checker” is used to
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`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1017, p. 5
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`Ex. 1017IPage 5 of5
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`Ex. 1017 / Page 5 of 5
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`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1017, p. 5