United States Patent [19]
`Thomas et al.
`
`[11] Patent Number:
`[45] Date of Patent:
`
`5,001,625
`Mar. 19, 1991
`
`364/ 200
`364/200
`
`‘
`
`3,810, l 14
`4,040,028
`4,067,059
`4,085,448
`4,096,571
`4,204,208
`4,213,177
`4,271,466
`4,286,321
`
`US. PATENT DOCUMENTS
`5/1974
`8/1977
`l/1978
`4/1978
`6/1978
`5/1980
`7/1980
`6/1981
`8/1981
`
`.
`
`[$4] BUS STRUCTURE FOR ()VERLAPPED DATA
`4,547,845 10/1985 Ross .......... ..
`TRANSFER
`4,554,627 11/1985 Holland et a1. .
`[75] Inventors: James H. Thomas; Roystou L. Smith, mm”? Ex4mi'1e"-Da"'id Y- Eng
`both of plantation, Fla‘; wmim p_
`Attorney, Agent. or Firm-Fleit, Jacobson, Cohn, Price,
`Ward, Poway, Calif.
`Holman 8‘ Stem
`ABSTRACT
`[73] Assignee: Gould lnc., Ft. Lauderdale, Fla.
`[57]
`[211 App], NO“. 173,212
`An improved system bus structure for versatile use in
`_
`various digital computer architecture con?gurations,
`Mu’ 24’ 1988
`[22] ?led:
`particularly those of mini-supercomputers, and, de
`[51] Int. (31.5 ............................................ .. G06F 13/40
`signed to support high speed. high reliability, Parallel
`[52] US. Cl. .................................. .. 364/200; 364/240;
`processing of bi-directional signal transfers in a multi
`364/240.2; 364/242.92
`port and multiple central processor unit (CPU) commu
`364/200 MS File, 900 MS File
`nication environment as between system bus units or
`[58] Field of Search
`[56]
`References and
`devices. The system bus structure may be sized for a
`compact encasement and may carry as many as 129
`simultaneous signals to and from various units’ con
`nected to it. The system'bus structure includes enabling
`structure for a centralized arbitration system, a central
`ized clock and synchronized transfer system, a central
`ized transfer monitor, a centralized parity error assessor
`and signalling system including transfer termination,
`and, a memory/inter-system inhibit system.
`
`Derchak .... ..
`
`Yamadat et al. _. ................. .. 364/200
`Pauker et a1.
`364/200
`364/200
`364/900
`Kogge
`364/200
`Mey ....... ..
`364/900
`McCarthy
`364/200
`.
`.
`Schmidt
`.. 364/200
`Yamamoto et a1.
`Baker ................................ ., 364/200
`
`11 Claims, 34 Drawing Sheets
`
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`251/ x 'to' 26!
`
`Apple Inc. v. Parthenon
`Ex. 1007 / Page 1 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 1
`
`

`

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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 2
`
`Ex. 1007 / Page 2 of 51
`
`Ex. 1007 / Page 2 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 2
`
`

`

`US. Patent
`
`Mar. 19, 1991
`
`Sheet 2 of 34
`
`5,001,625
`
`5YS7EV BUS
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`Ex. 1007 / Page 3 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 3
`
`

`

`US. Patent
`
`Mar. 19, 1991
`
`Sheet 3 of 34
`
`5,001,625
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`Ex. 1007 / Page 4 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 4
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 4 of 34
`
`5,001,625
`
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 5
`
`Ex. 1007 / Page 5 of 51
`
`Ex. 1007 / Page 5 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 5
`
`

`

`se)ateheae]aesessane]e|aveaveave
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`U.S. Patent
`
`Mar.19, 1991
`
`Sheet 5 of 34
`
`5,001,625
`
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`
`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 6
`
`Ex. 1007 / Page 6 of 51
`
`Ex. 1007 / Page 6 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 6
`
`
`
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 6 of 34
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`5,001,625
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 7
`
`Ex. 1007 / Page 7 of 51
`
`Ex. 1007 / Page 7 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 7
`
`

`

`US. Patent
`
`Mar. 19, 1991
`
`Sheet 7 of 34
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`5,001,625
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`Ex. 1007 / Page 8 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 8
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 8 of 34
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`5,001,625
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 9
`
`Ex. 1007 / Page 9 of 51
`
`Ex. 1007 / Page 9 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 9
`
`

`

`US. Patent
`
`Mar. 19, 1991
`
`Sheet 9 of 34
`
`5,001,625
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`Ex. 1007 / Page 10 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 10
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 10 of 34
`
`5,001,625
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 11
`
`Ex. 1007 / Page 11 of 51
`
`Ex. 1007 / Page 11 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 11
`
`

`

`US. Patent
`
`Mar. 19, 1991
`
`Sheet 11 of 34
`
`5,001,625
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`G
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`Ex. 1007 / Page 12 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 12
`
`

`

`US. Patent
`
`Mar. 19, 1991
`
`Sheet 12 of 34
`
`5,001,625
`
`FIG.I3B
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`Ex. 1007 / Page 13 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 13
`
`

`

`US. Patent
`
`Mar. 19, 1991
`
`Sheet 13 of 34
`
`5,001,625
`
`FIG.I4A
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`Ex. 1007 / Page 14 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 14
`
`

`

`US. Patent
`
`Mar. 19, 1991
`
`Sheet 14 of 34
`
`5,001,625
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`Ex. 1007 / Page 15 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 15
`
`

`

`US. Patent
`
`Mal-.19, 1991
`
`Sheet 15 of 34
`
`5,001,625
`
`FIG.|5A
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`Ex. 1007 / Page 16 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 16
`
`

`

`US. Patent
`
`. 19, 1991
`
`Sheet 16 of 34
`
`5,001,625
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`{120
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`Ex. 1007 / Page 17 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 17
`
`

`

`U.S. Patent
`
`Mar, 19, 1991
`
`Sheet 17 of 34
`
`5,001,625
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 18
`
`Ex. 1007 / Page 18 of 51
`
`Ex. 1007 / Page 18 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 18
`
`

`

`US. Patent
`
`Mar. 19, 1991
`
`Sheet 18 of 34
`
`5,001,625
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`Ex. 1007 / Page 19 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 19
`
`

`

`Sheet 19 of 34
`
`5,001,625
`
`US. Patent
`
`Mar. 19, 1991
`
`KOADGAIO'A! >
`
`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 20
`
`Ex. 1007 / Page 20 of 51
`
`Ex. 1007 / Page 20 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 20
`
`

`

`U.S. Patent
`
`Mar.19, 1991
`
`Sheet 20 of 34
`
`5,001,625
`
`[DWENO130-886|
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`EICODE
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`1B
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 21
`
`Ex. 1007 / Page 21 of 51
`
`Ex. 1007 / Page 21 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 21
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 21 of 34
`
`5,001,625
`
` REF T
`g [Bea]KOENeLADMi [P_>7|
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 22
`
`Ex. 1007 / Page 22 of 51
`
`Ex. 1007 / Page 22 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 22
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 22 of 34
`
`5,001,625
`
`220
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 23
`
`Ex. 1007 / Page 23 of 51
`
`Ex. 1007 / Page 23 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 23
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 23 of 34
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 24
`
`Ex. 1007 / Page 24 of 51
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`Ex. 1007 / Page 24 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 24
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 24 of 34
`
`5,001,625
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 25
`
`Ex. 1007 / Page 25 of 51
`
`Ex. 1007 / Page 25 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 25
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 25 of 34
`
`5,001,625
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`FIG. 20A
`
`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 26
`
`Ex. 1007 / Page 26 of 51
`
`Ex. 1007 / Page 26 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 26
`
`

`

`U.S. Patent
`
`Mar.19, 1991
`
`Sheet 26 of 34
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`5,001,625
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`FIG. 20B
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 27
`
`Ex. 1007 / Page 27 of 51
`
`Ex. 1007 / Page 27 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 27
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 27 of 34
`
`5,001,625
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 28
`
`Ex. 1007 / Page 28 of 51
`
`Ex. 1007 / Page 28 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 28
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 28 of 34
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`5,001,625
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 29
`
`Ex. 1007 / Page 29 of 51
`
`Ex. 1007 / Page 29 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 29
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 29 of 34
`
`5,001,625
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`
`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 30
`
`Ex. 1007 / Page 30 of 51
`
`Ex. 1007 / Page 30 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 30
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 30 of 34
`
`5,001,625
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 31
`
`Ex. 1007 / Page 31 of 51
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`Ex. 1007 / Page 31 of 51
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`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 31
`
`€
`

`

`U.S. Patent
`
`Mar.19, 1991
`
`Sheet 31 of 34
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`5,001,625
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 32
`
`Ex. 1007 / Page 32 of 51
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` FIG. 23A
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`Ex. 1007 / Page 32 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 32
`
`

`

`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 32 of 34
`
`5,001,625
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`FIG. 23B
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 33
`
`Ex. 1007 / Page 33 of 51
`
`Ex. 1007 / Page 33 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 33
`
`

`

`U.S. Patent
`
`Mar, 19, 1991
`
`Sheet 33 of 34
`
`5,001,625
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 34
`
`Ex. 1007 / Page 34 of 51
`
`Ex. 1007 / Page 34 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 34
`
`

`

`U.S. Patent
`
`Mar.19, 1991
`
`Sheet 34 of 34
`
`5,001,625
`
`FIG. 248
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`
`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 35
`
`Ex. 1007 / Page 35 of 51
`
`Ex. 1007 / Page 35 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 35
`
`

`

`1
`
`$,001,625
`
`BUS STRUCTURE FOR OVERLAPPED DATA
`TRANSFER
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`This application is related to applications for:
`“System For Monitoring and Capturing Bus Data In
`A Computer” to Smith et al. Ser. No. 173,222 filed on
`the same day as this application and assigned to the
`assignee ofthis application. The disclosure of the Smith
`et al. application is incorporated by reference herein;
`“Cache Memory with Interleaved Storage” to Ward
`et al. Ser. No. 173,405 filed on the same day as this
`application and assigned to the assignee of this applica-
`tion;
`“Advance Polling Bus, Arbiter for Use In Multiple
`Bus System” to Ward Ser. No. 173,211 filed on the same
`day as this application and assigned to the assignee of
`this application; and
`“Cache Memory Address Modifier For Dynamic
`Alteration of Cache Block Fetch Sequence” to Ward et
`al. Ser. No. 173,406 filed on the same dayas this applica-
`tion and assigned to the assignee of this application.
`BACKGROUND OF THE INVENTION
`
`This improved system bus structure relates generally
`to computers, and more particularly,
`to system bus
`structures for parallel signal transfers between devices
`as in multi-application mini-supercomputer systems of
`the type including at least one general purpose system
`bus structure for carrying as many as 128 simultaneous
`signals to and from various units connected to the sys-
`tem bus.
`In the past those skilled in the art have achieved high
`performance parallel computational power, by using
`one or more architectural classes of supercomputers:
`pipelined computers, array processors, vector proces-
`sors and multiprocessor systems. A pipelined computer
`performs overlapped computations to exploit temporal
`parallelism, while an array processor uses multiple
`arithmetic/logic units to achieve spatial parallelism. A
`vector processor uses large vectorregisters to facilitate
`repetitive arithmetic operations on groups or vectors of
`numeric operands, A multiprocessor system has multi-
`ple instruction streams over a set of interactive proces-
`sors with shared resources (memories, databases, etc.).
`Each ofthe systems is designed to offer improved per-
`formance for particular applications over a non-pipe-
`lined single processor digital computer, but not in other
`applications. Furthermore, the expense of supercomput-
`ers is very high in termsofinitial cost, maintenance, and
`space.
`There is a need for a lower cost computer having
`supercomputer capabilities and there is a further need
`for such a computer with a substantial capability to be
`utilized in many diverse applications.
`One of the most crucial impediments to improved
`performance of the super minicomputer has been the
`system bus structure design and methods for transfer-
`ring signals over the system bus structure. During the
`past few years, there have been a number ofattempts to
`solve the problems associated with the methods of com-
`municating in multi-unit and multi-processor environ-
`ments, but, generally speaking, they have only solved
`limited problems in limited applications.
`Forinstance, U.S. Pat. No. 4,233,366 to Levy teaches
`a synchronous system bus structure that requires each
`
`2
`of the system bus units connected to the system bus to
`sample each of the request signals and to conductits
`own arbitration, rather than to have a centralized arbi-
`tration and control unit, and further does not discuss
`any enablement for a system network.
`The instant assignee and its predecessor in interest
`have produced and sold a digital computer having a
`system bus structure with a two-board design, referred
`to as the Conceptseries, which transferred data as 32-bit
`words but lacked the capability of transferring 64 or
`128-bit words at one time. The prior Concept comput-
`ers also employed independent unit arbitration rather
`than centralized arbitration.
`Accordingly, there is a need for a system bus struc-
`ture for use in a variety of inexpensive mini-supercom-
`puter architectures including diverse applications and
`that is designed to support high speed, high reliability,
`parallel processing of bi-directional 64 and 128-bit sig-
`nal transfers in a multi-port and multiple central proces-
`sor unit (CPU) environment.
`SUMMARYOF THE INVENTION -
`
`A system bus structure includes up to seven ports for
`each ofa pair of CPUs; a controller port including lines
`for centralized clock distribution and centralized arbi-
`tration or access to the bus lines; three inter-system bus
`link (ISBL) ports for linking up to four system bus
`structures into a system network; a’ snapshot port for
`including a means for monitoring bustransfers, testing
`transfers for parity, and issuing parity error signals; a
`substantial number of general ports for connection of
`various bus units, such as a System Integrated Memory
`(SIM) unit, a Universal
`Input/Output Microengine
`(UIOM) unit, and, an Intelligent Peripheral Interface
`(IPT) unit, depending on the desired computer architec-
`ture.
`The system bus is organized into a total of forty-two
`general ports or bus ports. Each general port is com-
`prised of a primary port and a secondary port. Two of
`the ports are dedicated to the bus controller unit and’
`bus snapshot unit, and 14 others are reserved for the
`CPU board sets. The rest of the ports, referred to as
`general ports and comprising a primary port and a sec-
`ondary port pair, are for the memory boards, ISBLs,
`and UIOMs.
`The bus structure is organized into several major
`fields of multiple lines which carry message and data
`transfers, and control signals for intra and inter-system
`control. These fields include the memory address bus,
`data bus, expanded data bus, and individual control
`signals bus. Parity bits are associated with address and
`data bus fields.
`A primary object of the present invention is to pro-
`vide a system bus structure which can support a high
`speed, low cost mini-supercomputer with supercom-
`puter capabilities.
`A further object of the present invention is to provide
`a system bus structure which can support a high speed,
`low cost mini-supercomputer capable of being utilized
`on many diverse applications.
`A further object of the instant invention is to provide
`a system bus structure that supports high speed, high
`reliability, parallel processing of bi-directional signal
`transfers in a multi-port and multiple central processor
`unit (CPU) communication environment.
`A further object of the present invention is to provide
`a system bus structure that may carry as many as 128
`
`40
`
`50
`
`0
`
`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 36
`
`Ex. 1007 / Page 36 of 51
`
`Ex. 1007 / Page 36 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 36
`
`

`

`3
`simultaneous word signals to and from various units
`connected toit.
`A further object of the present inventionis to provide
`a system bus structure that is operable with a central-
`ized arbitration system.
`A further object of the present invention is to provide
`_a system bus structure that is operable with a central-
`ized clock and synchronized transfer system.
`A further object of the present inventionis to provide
`a system bus structure that is operable with a central-
`ized transfer monitor and a centralized parity error
`assessor and signalling system.
`A further object of the present invention is to provide
`a system bus structure that is operable with a memory-
`/inter-system inhibit system.
`A further object of the present inventionis to provide
`a method for transferring information between a pair of
`system units connected to the system bus structure.
`Other objects and uses of the present invention will
`become obvious to one skilled in the art upon a perusal
`of the specification and claimsin light of the accompa-
`nying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`§,001,625
`
`4
`FIG. 16A and 16B are logic diagrams of a portion of
`the logic of the request comparator;
`FIG. 17A and 17B are logic diagramsof a portion of
`the logic of the request comparator;
`.
`FIG. 18A and 18B are logic diagrams ofa portion of
`the logic of the bus select unit of FIG. 10;
`FIG. 19A and 19Bare logic diagrams of a portion of
`the logic of the bus select logic;
`FIG. 20A and 20B are logic diagrams of a portion of
`the bus select logic;
`FIG. 21A and 21B are logic diagrams of a portion of
`the bus select logic.
`FIG. 22A and 22B are logic diagrams of a portion of
`the bus select logic;
`FIG. 23A and 23B are logic diagramsof a portion of
`the bus select logic; and
`FIG. 24A and 24B are logic diagrams of the bus link
`priority unit of FIG. 10.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`
`Referring now to the drawings and especially to FIG.
`1, a mini-supercomputer 10 includes a high speed sys-
`tem bus structure embodying the present invention is
`shown therein and is generally identified by numeral
`FIG. 1 is a plan view of a system bus structure em-
`101. As may best be seen in FIGS. 1 and 2, a plurality of
`bodying the present invention and including a plurality
`system bus units generally referenced by numeral 215 is
`of signal processing lines and a preferred digital com-
`connected to the system bus structure 101 by attach-
`puter architecture;
`mentof said units 215 to respective desired ports, and,
`FIG.2 is a block diagram view of the preferred multi- _
`particulariy designed to support high speed, high reli-
`processor digital computer architecture of FIG. 1 in-
`ability, parallel processing of bi-directional signal trans-
`cluding the system bus structure;
`fers in a multi-port and multiple central processor unit
`FIG.3is an isolation view, in partial cutaway, of a
`(CPU) environment communication as between system
`port side of a backplane incorporated as part of the
`bus units or devices 215. One embodiment of a system
`system bus structure of FIG.1 and displaying a primary
`bus architecture 100 utilizing the system bus structure
`port, a secondary port, and, a CPU port includinga slot
`101 as contemplated is shown in FIGS. 1 and 2. This
`and a pin configuration;
`embodiment comprises a first Vector Processing Cen-
`FIG. 4 is a timing diagram displaying a latch signal
`tral Processing Unit (CPU) 201 connected to up to
`and a trigger clock signal, a plurality of related signals,
`seven ports respectively numbered 01-07, three Inter-
`and corresponding clock signal cycles over which bus
`System Bus Link Units (ISBLs) respectively numbered
`transfer operations are distributed.
`221, 231 and 241 connected to ports, respectively num-
`FIG.5 is a more detailed timing diagram ofthe latch
`bered 19, 23 and 25, a bus controlier unit 251 connected
`signals and trigger clock signals of FIG.4;
`to a port 20, a snapshot unit 261 connectedto a port, and
`FIG.6 is a broad plan view showingthe location of
`a second Vector Processing Central Processing Unit
`the system bus structure of FIG. 6 in a rearward loca-
`(CPU) 211 connecting to up to seven ports respectively
`tion of a mini-supercomputer housing or casing having
`numbered 36-42. A number of additional general ports
`a width of less than thirty inches and showing in block
`08-17 and 26-35 are provided for connection of other
`form a plurality of power connections for the system
`system bus units 215, such as a System Integrated Mem-
`bus structure from the casing;
`ory (SIM) unit, a Universal Input/Output Microengine
`FIG.7 is a representation of a plurality of serial bus
`(UIOM) unit, and an Intelligent Peripheral Interface
`signals including a plurality of fields into which the
`(IPI) unit.
`plurality of serial bus signals are organized for a serial
`Upto three Inter-System Bus Link Units 221, 231 and
`bus transfer;
`241 may be connected to a given system bus structure
`FIG.8 is a representation of the main and expanded
`101 in order to provide a means for developing a system
`data bus transfer fields including the addressable fields;
`network. A system network is created by connecting a
`FIG.9 is a representation of the various bus fields for
`given ISBL from a first system bus structure 101 to a
`bus transfers on the system bus structure.
`second ISBL from a second system bus structure 101.
`FIG. 10 is a block diagram of the logic of the bus
`By creating this interconnection of system bus struc-
`arbiter on the bus control board shown in FIG.1;
`tures 101, the various system bus units 215 from thefirst
`FIG. 11A and 11B are logic diagramsofa portion of
`system bus structure 101 may communicate with vari-
`a request in logic module of the bus arbiter of FIG. 10;
`ous system bus units 215 from the second system bus
`FIG. 12A and 128 are logic diagrams of a portion of
`structure 101. The result is that the overall memory
`the request in logic of the bus arbiter of FIG. 11;
`space of one system bus architecture 100 utilizing the
`FIG. 13A and 13B are logic diagrams of portion of
`system bus structure 101 may be doubled, tripled, or
`the request in logic;
`increased four-fold with up to four system bus struc-
`FIG. 14A and 14B are logic diagrams of a portion of
`tures 101 inter-connected into a system network.
`the request comparator logic of FIG. 10;
`The system bus structure 101 includes several sets of
`FIG. 15A and 15Bare logic diagrams of a portion of
`multiple lines, buses or bus lines, referred to generally
`the logic of the request comparator,
`
`45
`
`60
`
`65
`
`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1007, p. 37
`
`Ex. 1007 / Page 37 of 51
`
`Ex. 1007 / Page 37 of 51
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1007, p. 37
`
`

`

`5
`by numeral 121, which may be implemented onto a
`backplane 119 as with external layer printed wiring
`having an unloaded characteristic impedance of approx-
`imately 50 ohms. The major buses 121 include a main
`system bus 141, a main data bus 103, an expanded data
`bus 145, a serial bus 147, and, a plurality of intraport
`busses 149.
`The main system bus 141 is comprised of one hundred
`eleven lines organized into several major fields of multi-
`ple lines, the signals of which are separately interpret-
`able for providing desired message transfer characteris-
`tics under which the system bus structure 101 operates
`andis discussed more particularly hereinafter. The main
`system bus 141 also includes a numberof controlsignal
`lines which carry individual contro! signals used for
`general system control including global stop request,
`powerfail, and stop clock lines.
`The ma