United States Patent [19]
`Macko et al.
`
`[54] MESSAGING PERIPHERAL WITH SECURE
`MESSAGE DATA FUNCTION
`
`[75]
`
`Inventors: William J. Macko, West Palm Beach;
`Greg Cannon, Delray Beach, both of
`Fla.
`
`[73] Assignee: Motorola, Inc., Schaumburg, Ill.
`
`[21] Appl. No.: 84,905
`
`[22] Filed:
`
`Jul. 2, 1993
`
`Int. Cl.6 .......................... H04Q 7/18; G08B 5/22
`[51]
`[52] U.S. Cl ........................... 340/825.44; 340/825.27;
`340/825.34
`[58] Field of Search ...................... 340/825.44, 825.34,
`340/825.31, 825.27, 311.1; 379/59
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,806,906 2/1989 Oda et al. ....................... 340/825.44
`4,839,628 6/1989 Davis et al. ...................... 340/311.1
`4,857,883 8/1989 Mama ............................... 340/311.l
`5,012,234 4/1991 Dulaney et al. ................ 340/825.31
`5,043,721 8/1991 May ................................ 340/825.44
`5,060,263 10/1991 Bosen et al. .................... 340/825.31
`5,073,767 12/1991 Holmes et al. ................. 340/825.44
`5,146,217 9/1992 Holmes et al. ................. 340/825.34
`5,151,694 9/1992 Yamasaki ....................... 340/825.44
`5,281,962 1/1994 Vanden Heuvel et al .... 340/825.27
`5,302,947 4/1994 Fuller et al ..................... 340/825.44
`
`I lllll llllllll Ill lllll lllll lllll lllll lllll 111111111111111111111111111111111
`5,436,621
`Jul. 25, 1995
`
`US005436621A
`[11] Patent Number:
`[45] Date of Patent:
`
`FOREIGN PATENT DOCUMENTS
`90/13213 11/1990 WIPO .
`
`OTHER PUBLICATIONS
`PC Card Standard Release 2.0, Personal Computer
`Memory Card International Association, Sep. 1991.
`Primary Examiner-Donald J. Yusko
`Assistant Examiner-Mark H. Rinehart
`Attorney, Agent, or Firm-Gregg E. Rasor
`[57]
`ABSTRACT
`A messaging peripheral (100) includes a processor (106)
`for executing a microcode program that controls opera(cid:173)
`tion of the messaging peripheral (100), and a PCM CIA
`memory only interface (119) that allows communica(cid:173)
`tion of communication of at least one message and a
`user selectable password between an electronic infor(cid:173)
`mation processing device (200) and the messaging pe(cid:173)
`ripheral (100). The PCMCIA memory only interface
`couples to a secure memory access interface that is
`controlled by the processor (106). The secure memory
`access interface (703) allows the electronic information
`processing device (200) to access the at least one mes(cid:173)
`sage when a memory protection mode is selected and
`the processor (106) receives a user entered password
`and performs a correlation between the user entered
`password and the user selectable password.
`
`18 Claims, 8 Drawing Sheets
`
`ELECTRONIC
`INFORMATION
`PROCESSING
`DEVICE
`
`200
`_./
`
`'
`DATA
`
`ADDRESS
`
`+cny1.cc:y
`
`106
`
`I
`J
`PROCESSOR
`
`7J2
`r
`'
`I euFFERsT
`
`DATA
`.---------'-A=D=DR~E=S=S--.:i MEMORY
`
`'PASSWORD I
`ADDRESS I I
`I MULTIPLEXERi--____________ _,
`
`703
`
`DATA
`
`DATA
`
`ADDRESS
`
`RAM L.-35
`
`PCMCIA MESSAGING PERIPHERIAL
`
`IPR2017-00430
`UNIFIED EX1015
`
`

`
`102
`\ 7 ~
`,-
`
`I
`
`-
`
`l
`
`I BATTERY
`
`101_.J
`
`-
`-
`
`BIT SYNC
`DETECTOR
`
`WORD SYNC
`DETECTOR
`
`-
`.
`-
`-
`-
`-
`ADDRESS
`...
`- CORRELATOR
`I
`
`BATTERY
`SAVER
`J
`
`-
`
`,
`
`I
`. RECEIVER
`DEMODULATOR
`- I
`_______ J::.~o: _____
`-...
`~, _______ , _____________________
`' '
`,
`: MICROCONTROLLER
`,
`'
`,
`'
`,
`'
`,
`'
`- ,
`'
`'
`- ,
`'
`,
`'
`,
`'
`,
`'
`,
`'
`,
`'
`,
`'
`,
`'
`,
`'
`,
`'
`,
`'
`,
`'
`,
`'
`,
`'
`,
`'
`,
`,
`,
`,
`,
`'
`,
`'
`,
`'
`,
`.
`'
`,
`113'
`TIMING
`,
`:
`CONTROL LJ
`NONVOLAT~E114 ----------~ii2mmnn. ·r·--------j·---~::~ 'jf6
`
`~7
`
`1ir
`
`,111
`
`108
`[..)
`
`~9
`...._
`
`DECODER::
`
`.,
`
`(
`110
`
`BAUD RATE
`DETECTOR
`
`I I
`
`'ir• ·1•,106·
`
`ir
`
`PROCESSOR
`
`~
`
`~
`
`' •
`
`I 0
`
`I
`
`'
`
`-
`
`.
`
`.
`
`.
`-
`
`-
`
`-
`
`r-119
`
`PCM CIA
`INTERFACE
`
`r11B
`
`ALERT
`
`,115
`
`RAM
`MEMORY
`
`/"117
`
`DISPLAY
`
`FIG. I
`100
`
`L: •
`rJ'J.
`•
`
`~ a. ('t) = ~
`
`~
`~
`N
`"'fJI
`t..i.
`~
`fJI
`
`rJl
`~
`~
`t..i.
`0 ....,
`00
`
`01
`....
`~
`CJ,)
`~ ....
`~ .....
`
`MEMORY
`
`CONTROLS
`
`

`
`U.S. Patent
`
`July 25, 1995
`
`Sheet 2 of 8
`
`5,436,621
`
`200
`-------------_ J_ _ ----------._ -------------
`' '201
`'
`
`TIMING
`CLOCK
`
`CENTRAL
`PROCESSING
`UNIT
`
`I
`I
`
`DISPLAY ,.__..r..-. .. "'
`DRIVER
`
`I
`I
`
`I
`
`I
`
`'208
`
`202
`PCMCIA 1/0 .,._ _ __. .___ ____ ...:i
`INTERFACE
`
`206
`
`~~tA OTHER 1/0 " " - - -
`
`RAM
`
`207
`
`~01r
`~! iJ
`
`MASS
`STORAGE
`
`" -__ ....,
`
`ROM
`
`203
`
`204
`
`I
`I
`
`-----------------------------------------
`FIG.2
`
`I
`I
`I
`
`

`
`U.S. Patent
`
`July 25, 1995
`
`Sheet 3 of 8
`
`5,436,621
`
`Pin Signal
`1
`GND
`2
`D3
`3
`D4
`4
`D5
`D6
`5
`D7
`6
`7
`CE1
`8
`A10
`9
`OE
`10
`A11
`11
`A9
`12
`AS
`13
`A13
`14
`A14
`15 WE/PGM
`16
`RDY/BSY
`17
`Vee
`18
`Vpp1
`
`A16
`19
`A15
`20
`A12
`21
`22
`A7
`A6
`23
`24
`AS
`A4
`25
`A3
`26
`A2
`27
`A1
`28
`AO
`29
`DO
`30
`D1
`31
`D2
`32
`33 WP
`34 GND
`
`VO
`
`Function
`Ground
`VO
`Data bit 3
`VO
`Data bit 4
`VO
`Data bit 5
`VO
`Data bit 6
`VO
`Data bit 7
`I
`Card enable
`I
`Address bit 10
`I
`Output enable
`I
`Address bit 11
`I
`Address bit 9
`I
`Address bit 8
`I
`Address bit 13
`I
`Address bit 14
`I Write enable
`0
`Ready/Busy
`Power Supply
`Programming and
`Peripheral Supply
`I
`Address bit 16
`I
`Address bit 15
`I
`Address bit 12
`I
`Address bit 7
`I
`Address bit 6
`I
`Address bit 5
`I
`Address bit 4
`I
`Address bit 3
`I
`Address bit 2
`I
`Address bit 1
`I
`Address bit O
`VO
`Data bit O
`VO
`Data bit 1
`VO
`Data bit2
`0 Write protect
`Ground
`
`FIG. 3
`
`+/-
`
`-
`
`-
`
`-
`+/-
`
`-
`
`

`
`U.S. Patent
`
`July 25, 1995
`
`Sheet 4 of 8
`
`5,436,621
`
`Pin Signal
`35 GND
`CD1
`36
`37
`D11
`D12
`38
`D13
`39
`40
`D14
`41
`D15
`42
`CE2
`43
`RFSH
`44
`RFU
`45
`RFU
`46
`A17
`47
`A18
`48
`A19
`49
`A20
`50
`A21
`51
`Vee
`52
`Vpp2
`
`A22
`53
`54
`A23
`A24
`55
`A25
`56
`57
`RFU
`RESET
`58
`59 WAIT
`60
`RFU
`61
`REG
`62
`BVD2
`BVD1
`63
`64
`D8
`D9
`65
`D10
`66
`67
`CD2
`68 GND
`
`+/-
`-
`
`-
`
`+
`-
`-
`-
`
`-
`
`VO
`
`0
`VO
`VO
`VO
`VO
`VO
`I
`I
`
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`
`I
`0
`
`I
`0
`0
`VO
`VO
`VO
`0
`
`Function
`Ground
`Card Detect
`Data bit 11
`Data bit 12
`Data bit 13
`Data bit 14
`Data bit 15
`Card enable
`Refresh
`Reserved
`Reserved
`Address bit 17
`Address bit 18
`Address bit 19
`Address bit 20
`Address bit 21
`Power Supply
`Programming and
`Peripheral Supply 2
`Address bit 22
`Address bit 23
`Address bit 24
`Address bit 25
`Reserved
`Card Reset
`Extend bus cycle
`Reserved
`Register select
`Battery voltage detect 2
`Battery voltage detect 1
`Data bit 8
`Data bit 9
`Data bit 10
`Card detect
`Ground
`
`FIG. 4
`
`

`
`U.S. Patent
`
`July 25, 1995
`
`Sheet 5 of 8
`
`5,436,621
`
`START
`
`NO
`
`~--+----~1( RETURN y
`
`505
`
`YES
`
`NO
`
`504
`
`TOGGLE CARD DETECT
`LINE OR TOGGLE
`READY/BUSY LINE
`
`FIG.5
`
`

`
`U.S. Patent
`
`July 25, 1995
`
`Sheet 6 of 8
`
`5,436,621
`
`START
`
`YES
`
`SET FLAG
`
`START TIMER
`
`605
`
`CHECK FOR MESSAGES IN
`RECEIVING DEVICE
`
`FIG. 6
`
`NO
`
`ALLOW MESSAGES
`TOBE READ.
`
`614
`
`

`
`U.S. Patent
`
`July 25, 1995
`
`Sheet 7 of 8
`
`5,436,621
`
`ELECTRONIC
`INFORMATION
`PROCESSING
`DEVICE
`
`200
`L/
`
`'
`
`•
`
`DATA
`
`ADDRESS
`
`+RDY/-B~Y
`
`106
`l
`J
`PROCESSOR
`
`, , 702
`
`I
`
`I BUFFERS
`
`T
`
`PASSWORD
`MEMORY
`
`DATA
`ADDRESS
`
`-
`
`- DATA
`
`. ' .
`-ADDRESS I I
`I MULTIPLEXER: .... _ --------o1111--------l
`••
`'I
`
`703
`
`I I
`
`,1
`DATA' I
`
`I I ADDRESS
`
`RAM us
`
`PCMCIA MESSAGING PERIPHERIAL
`
`FIG. 7
`
`\ 100
`
`

`
`U.S. Patent
`
`July 25, 1995
`
`Sheet 8 of 8
`
`5,436,621
`
`--------------- 801
`OTHER SCHEDULING
`ACTIVITIES
`
`811
`
`y
`
`SET'DEVICE
`PROTECTED' FLAG
`
`y
`
`RECEIVE
`PASSWORD
`
`806
`
`N
`
`808
`
`809
`
`DENY ACCESS TO
`DEVICE
`
`ALLOW ACCESS TO
`DEVICE
`
`FIG. 8
`
`

`
`1
`
`5,436,621
`
`MESSAGING PERIPHERAL WITH SECURE
`MESSAGE DATA FUNCTION
`
`FIELD OF THE INVENTION
`This invention relates in general to a Personal Com(cid:173)
`puter Memory Card Interface Association (PCMCIA)
`peripheral and more particularly to a PCMCIA periph(cid:173)
`eral with selective call messaging capability.
`
`5
`
`2
`ture stored within the peripheral. This severe shortcom(cid:173)
`ing limits the usefulness of a memory-only PCMCIA
`interface peripheral to situations where relatively static
`data is needed, e.g., as a ROM card or the like.
`A final consideration is that the messaging informa(cid:173)
`tion received by a memory-only PCMCIA interface
`peripheral may be proprietary in nature. In this case,
`one may simply remove the memory-only PCMCIA
`interface peripheral from a first host and insert it into a
`10 second host, then read the messaging information. This
`possibility would allow an unauthorized person to
`"steal" one's private messages without their knowledge.
`Similarly, if the memory-only PCMCIA interface pe-
`ripheral is left in the first host and the owner has left the
`area, leaving the host unprotected, the unauthorized
`user may read the authorized user's confidential messag(cid:173)
`ing information.
`Consequently, what is needed is a standardized com(cid:173)
`munication interface for state of the art selective call
`receiver systems that provides a capability to effec(cid:173)
`tively communicate received information between a
`microcomputer or the like. Additionally, the memory(cid:173)
`only PCMCIA interface peripheral should be able to
`either manually or automatically protect received mes(cid:173)
`sages from unauthorized access.
`
`BACKGROUND OF THE INVENTION
`Selective call communication (paging) systems typi(cid:173)
`cally comprise a radio frequency transmitter/encoder
`(base station) that is accessed via a link to the Public
`Switched Telephone Network (PSTN) and a radio 15
`receiver (e.g., a selective call receiver or the like) that
`has at least one unique call address associated therewith.
`Operationally, the selective call receiver receives and
`decodes information transmitted from the base station,
`the information including an address and possibly a data 20
`or voice message. When the selective call receiver de(cid:173)
`tects its address, it may alert a user and present message
`information received.
`To implement messaging capability in a paging sys(cid:173)
`tem, the address and message information referred to 25
`are encoded and subsequently transmitted using a pro(cid:173)
`tocol such as GSC (Motorola's Golay Sequential Code)
`or POCSAG (a code from Great Britain's Post Office
`Code Standardisation Advisory Group). These proto(cid:173)
`cols are adapted to reliably communicate messages to at 30
`least one selective call receiver and are well known to
`one of ordinary skill in the art of paging systems. A
`typical selective call message may consist of an address
`signal if the message is a tone only message, or an ad(cid:173)
`dress signal and a data packet if the message is a data 35
`message.
`Present selective call receivers operate almost exclu(cid:173)
`sively in a standalone fashion, that is, received messages
`can only be presented by the receiver's display. Some
`conventional selective call receivers include a serial 40
`data interface for communicating a single received mes(cid:173)
`sage to an alternate presentation device such as a printer
`or possibly an electronic advertising sign. Presently,
`state of the art selective call receiver serial communica(cid:173)
`tion systems use a three wire serial interface operating 45
`at data rates from 300 to 9600 baud. This serial architec(cid:173)
`ture inherently limits the data bandwidth (speed and
`information content) between the receiver and a data
`device. Moreover, since the three wire interface has
`only transmit data, receive data, and ground connec- 50
`tions, any control signals must be encoded as serial data
`symbols, further slowing response time and limiting the
`data bandwidth. Lastly, since these interfaces are pro(cid:173)
`prietary in nature, that is, there is no standard for signal
`levels, data rates, or protocols, data interchange be- 55
`tween devices of different manufacturers is all but im(cid:173)
`possible because of a lack of convention.
`Even if a parallel or memory bus scheme is adopted
`for communicating data between the selective call re(cid:173)
`ceiver and the data device, there is still a problem when 60
`this is implemented using the PCMCIA memory-only
`interface standard. By definition, PCMCIA memory(cid:173)
`only interface peripherals don't include any means for
`generating a signal for notifying the data device of a
`need for service. Moreover, PCMCIA memory-only 65
`interface peripherals don't have a native mode that
`allows for the execution of configuration or service
`commands useful to interrogate data of a dynamic na-
`
`SUMMARY OF THE INVENTION
`Briefly, according to the invention, there is provided
`a messaging peripheral capable of communicating with
`an electronic information processing device, the mes(cid:173)
`saging peripheral comprising: a processor for executing
`a microcode program that controls operation of the
`messaging peripheral; a PCMCIA memory only inter(cid:173)
`face coupled to and controlled by the processor, the
`PCMCIA memory only interface serving to allow com(cid:173)
`munication of at least one message and a user selectable
`password between the electronic information process(cid:173)
`ing device and the messaging peripheral, and a secure
`memory access interface controlled by the processor
`and coupled to the PCMCIA memory only interface,
`the secure memory access interface allowing the elec(cid:173)
`tronic information processing device to access the at
`least one message when a memory protection mode is
`selected and the processor receives a user entered ·pass(cid:173)
`word and performs a correlation between the user en(cid:173)
`tered password and the user selectable password.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of a messaging peripheral
`having a PCMCIA memory only interface configured
`for operation in accordance with the preferred embodi(cid:173)
`ment of the present invention.
`FIG. 2 is a block diagram of an electronic informa(cid:173)
`tion processing device having a PCMCIA memory only
`interface configured _for operation in accordance with
`the preferred embodiment of the present invention.
`FIG. 3 illustrates a first portion of a PCM CIA mem(cid:173)
`ory only interface table listing signals used for commu(cid:173)
`nication between the messaging peripheral and elec(cid:173)
`tronic information processing device in accordance
`with the preferred embodiment of the present inven(cid:173)
`tion.
`FIG. 4 illustrates a second portion of a PCMCIA
`memory only interface table listing signals used for
`communication between the messaging peripheral and
`electronic information processing device in accordance
`
`

`
`5,436,621
`
`3
`with the preferred embodiment of the present inven(cid:173)
`tion.
`FIG. 5 is a flow diagram illustrating a procedure for
`the messaging peripheral to notify the electronic infor(cid:173)
`mation processing device of a received message.
`FIG. 6 is a flow diagram illustrating a procedure for
`the electronic information processing device to respond
`when notified of the received message by the messaging
`peripheral in accordance with the preferred embodi(cid:173)
`ment of the present invention.
`FIG. 7 is a block diagram of a messaging peripheral
`having a secure memory access interface that facilitates
`password protection of received messages in accor(cid:173)
`dance with the preferred embodiment of the present
`invention.
`FIG. 8 is a flow diagram illustrating a procedure
`embodied in the messaging peripheral for protecting
`and accessing the password protected messages stored
`in the messaging peripheral in accordance with the
`preferred embodiment of the present invention.
`
`20
`
`4
`lator 104, thereby conserving power and extending
`battery life. The interval between like frames is known
`in the art as a "sleep" period. Preferably, the system
`protocol operates such that pages targeted for a specific
`5 group identifier, and pages intended for a particular
`messaging peripheral, are sent only during the transmis(cid:173)
`sion of that peripheral's designated paging group, there(cid:173)
`fore, no pages are missed during the sleep period. A
`peripheral that operates in this fashion is said to be in a
`10 "battery saving" mode.
`In determining the selection of the particular messag(cid:173)
`ing peripheral, a correlation is performed between a
`predetermined address associated with the messaging
`peripheral and a received address. To accomplish this,
`15 the address correlator 109, which comprises a signal
`processor, performs a comparison between the address
`signal recovered from the received information signal
`and a predetermined address associated with the mes-
`saging peripheral, generating a detection indicating
`selection of the messaging peripheral when the recov(cid:173)
`ered address is substantially equivalent to the predeter-
`mined address. The predetermined address or addresses
`associated with the messaging peripheral are preferably
`stored in the non-volatile memory 114 or code plug.
`Optionally, the non-volatile memory 114 may reside
`inside a support integrated circuit (not shown) or in the
`microcontroller 105. The non-volatile memory 114 typ(cid:173)
`ically has a plurality of registers for storing a plurality
`of configuration words that characterize the operation
`of the messaging peripheral. When a detection is gener(cid:173)
`ated, the microcontroller 105 may generate an alert
`responsive to a selected alerting mode, e.g., a tone alert
`would be generated when a tone-only mode is selected.
`Alternatively, in response to a valid data address corre(cid:173)
`lation and a corresponding detection, the decoder 111
`operates to decode at least one message from the re-
`ceived information signal and couples message informa(cid:173)
`tion to the RAM memory 115.
`In accordance with the recovered information, the
`programmed operating parameters stored in the non(cid:173)
`volatile memory 114, and settings associated with the
`user controls 116, the messaging peripheral may present
`at least a portion of the message information, such as by
`a display 117. Alternatively, the user may be alerted
`that a message has been received by an alert transducer
`118 that generates an audible, visual, or tactile alert.
`The user may view received message information on
`the display 117 by manually activating an appropriate
`user control 116 such as a message read control 116.
`The microcontroller 105 may also include items such
`as a conventional signal multiplexer, a voltage regulator
`and control mechanism, a current regulator and control
`mechanism, environmental sensing circuitry such as for
`light or temperature conditions, audio power amplifier
`circuitry, control interface circuitry, and display illumi(cid:173)
`nation circuitry. These elements are arranged in a
`known manner to configure the messaging peripheral as
`requested by a customer.
`In the preferred embodiment, upon receipt or storage
`60 of a message, the microcontroller 105 may communi(cid:173)
`cate the received message to an electronic information
`processing device (e.g., a host microcomputer or the
`like as illustrated in FIG. 2) via a PCMCIA interface
`119. When coupled to the electronic information pro-
`65 cessing device 200, the messaging peripheral 100 may
`operate to automatically deliver received messages in
`real time, or transfer stored messages to the electronic
`information processing device for storage, presentation,
`
`DESCRIPTION OF A PREFERRED
`EMBODIMENT
`Referring to FIG. 1, a battery 101 powered messag(cid:173)
`ing peripheral 100 operates to receive an information 25
`signal via an antenna 102. A receiver 103 couples the
`received information signal to a conventional demodu(cid:173)
`lator 104 that is capable of recovering analog or digital
`information. Received digital information is recovered
`as a serial bit stream that is then coupled to a microcon- 30
`troller 105 for interpreting and decoding the serial bit
`stream as address, control, and data signals. In the pre-
`f erred embodiment, the microcontroller 105 may com(cid:173)
`prise a processor 106, a bit synchronization detector
`107, a word synchronization detector 108, an address 35
`correlator 109, a baud rate detector 110, a data decoder
`111, a battery saving control circuit 112, and a timing
`control 113, implemented in hardware, software, or a
`combination thereof. Examples of commercially avail(cid:173)
`able microcontrollers suitable for implementing the 40
`preferred embodiment of the present invention are Mo(cid:173)
`torola's MC68HC05xx or M68HC1 ixx. Complete de(cid:173)
`scriptions of these devices are available in Motorola's
`data book set entitled "Microprocessor, Microcon(cid:173)
`troller, and Peripheral Data," volumes I and II, Series 45
`A, @ 1988 by MOTOROLA, INC.
`More specifically, in the microcontroller 105 the
`serial bit stream is coupled to the baud rate detector 110
`that determines a receiving data rate associated with the
`recovered information. When the receiving data rate is 50
`determined, the bit synchronization detector 107 estab(cid:173)
`lishes synchronization between the microcontroller's
`105 data decoding components (106, 109, and 111) and
`the individual signals (e.g., address, control, and data
`signals) in the recovered information. Once bit synchro- 55
`nization is established, the word synchronization detec(cid:173)
`tor 108 searches the serial bit stream for information
`indicating the beginning of a batch or frame. When the
`microcontroller 105 has established both bit and word
`synchronization, the recovered information may be
`searched for a group identification code associated with
`the messaging peripheral. When a group identification
`code is found corresponding to the messaging periph(cid:173)
`eral, it will search only those code frames associated
`with it's group for pages intended for the messaging
`peripheral. During the period between like frames, the
`microcontroller 105 will preferably activate the battery
`saver 112 to "shut-down" the receiver 103 and demodu-
`
`

`
`5,436,621
`
`5
`archival, or the like. Alternatively, a user may via a
`program executing on the electronic information pro(cid:173)
`cessing device, download any messages previously re(cid:173)
`ceived and stored by the messaging peripheral 100
`while in the standalone operating mode (separated from 5
`the electronic information processing device). In this
`way, the messaging peripheral 100 gives a paging sub(cid:173)
`scriber the option of operating as a conventional standa(cid:173)
`lone selective call paging receiver, that is, receiving,
`storing and displaying messages. It is for this reason that IO
`the messaging peripheral 100 includes a message read
`control for recalling the at least one message from the at
`least one electronic memory 115 for presentation. This
`allows a user to present the at least one message recalled
`from the at least one electronic memory 115 on the 15
`display 117 in response to activating the message read
`control 116.
`As can be appreciated by one of ordinary skill in the
`art, this invention can be realized in a number of em(cid:173)
`bodiments of which the disclosed embodiment is only 20
`one of many equivalent alternatives.
`Referring to FIG. 2, the illustration shows a elec(cid:173)
`tronic information processing device 200 having a
`PCMCIA interface configured for operation in accor(cid:173)
`dance with the preferred embodiment of the present 25
`invention. As illustrated, the electronic information
`processing device 200 comprises a system timing clock
`201, central processing unit 202, random access memory
`(RAM) 203, read only memory (ROM) 204, mass stor(cid:173)
`age (e.g., a disk drive or the like) 205, display driver 30
`206, general I/O interfaces 207, and a PCMCIA mem(cid:173)
`ory only interface 208. In the preferred embodiment,
`the
`electronic
`information processing
`device's
`PCMCIA memory only interface 208 couples to the
`messaging peripheral's 100 PCMCIA interface 119. 35
`After coupling, messages received by the messaging
`peripheral 100 may be communicated to the electronic
`information processing device 200 via the PCMCIA
`memory only interface 208 and directed to the elec(cid:173)
`tronic information processing device's RAM 203, mass 40
`storage 205, display driver 206 for presentation on an
`external display (not shown), or possibly to one of the
`general 1/0 interfaces 207 for routing to a printer or the
`like.
`The system formed by coupling the elements de- 45
`picted in FIG. 1 and FIG. 2 via a PCMCIA memory
`only interface realizes many advantages over prior art
`selective call messaging systems. Since the PCMCIA
`interface is a standard, the messaging peripheral 100
`need not be customized for operation with dissimilar 50
`host computers supporting the PCM CIA standard. This
`eliminates the problems associated with proprietary
`interface standards such as no standard for signal levels, -
`data rates, or protocols, making data interchange be(cid:173)
`tween devices of different manufacturers is all but im- 55
`possible. Another advantage of the PCM CIA interface
`implemented in the messaging peripheral 100 over the
`conventional three wire serial communication systems
`is data throughput. Since the PCMCIA interface can
`accommodate 16 bit parallel data transfers, and includes 60
`DMA (direct memory access) capability, there is a sig(cid:173)
`nificant increase in data bandwidth as opposed to a 9600
`baud, 8 bit, asynchronous serial data link. Moreover, the
`PCMCIA interface implements dedicated control sig(cid:173)
`nals, and may even provide power for the selective call 65
`messaging peripheral 100.
`Referring to FIG. 3 and FIG. 4, the illustrations show
`a first and a second portion of a PCM CIA memory only
`
`6
`interface table listing signals used for communication
`between the PCMCIA messaging peripheral and elec(cid:173)
`tronic information processing device.
`The tables illustrated in FIG. 3 and FIG. 4 detail the
`PCMCIA memory only interface pinout and signal
`definitions. The PCMCIA memory only interface stan(cid:173)
`dard includes provisions for reading 16-bit data on the
`low-order 8 bit data bits (useful in conventional 8-bit
`host systems) and for the interpretation of status infor(cid:173)
`mation returned by a PCMCIA peripheral card. The
`principal aspects of the PCMCIA card interface are
`byte addressability, random access to bytes of data, and
`the existence of a separate "register" attribute memory
`space selected by a REG signal. This allows an elec(cid:173)
`tronic information processing device to obtain highly
`detailed peripheral card information such as its manu(cid:173)
`facturer or a chip-type. The PCMCIA standard also
`allows access to control registers in configurable types
`of cards.
`The standard PCMCIA interface depicted has a 64-
`Mbyte addressing capability and numerous hardware
`provisions to support the various memory technologies,
`including ROM, OTPROM, UV-EPROM, FLASH,
`SRAM and PSRAM. 1/0-card support is provided in
`the PCMCIA 1/0 interface (not shown) by Interrupt,
`16-bit cycle, IOread/IOwrite, INput ACK, Reset, Wait,
`Status Change, Enable and Power signals, some of
`which are dynamically redefined to these uses once an
`1/0 card is recognized by the host.
`All signals in the PCMCIA interface are grouped
`under four classifications: I (Input), 0 (Output), I/O
`(Bidirectional), and R (Reserved). Input signals are
`those driven by the electronic information processing
`device and output signals are those driven by the pe(cid:173)
`ripheral card.
`The Memory-Only Interface supports memory cards,
`but does not contain signals which support 1/0 Cards.
`The preferred embodiment of the present invention
`implements the Memory-Only Interface as defined by
`PCMCIA. The signals +RDY/-BSY, WP, BVD1
`and BVD2 are present on the Memory-Only Interface
`but are replaced by other signals when the I/0 Inter(cid:173)
`face is selected. The Memory-Only Interface is selected
`by default in both the socket and the card whenever a
`card is inserted into a socket, and immediately follow(cid:173)
`ing the application of V cc (power) or the RESET signal
`to a card. After a card's Card Information Structure
`(CIS) has been interpreted, the card and the socket may
`be configured, if appropriate, to use the 1/0 Interface.
`PCM CIA peripheral cards may be configured by the
`electronic information processing device to change the
`way that their address space is accessed. Before config(cid:173)
`uring a card, the electronic information processing de(cid:173)
`vice must examine the card's CIS to determine the ad(cid:173)
`dress space and other requirements of the possible card
`configurations. The electronic information processing
`device uses this information to select the best configura(cid:173)
`tion from those available in the card, as determined by
`the electronic information processing device's hard(cid:173)
`ware and software capabilities, as well as the require(cid:173)
`ments of other cards installed concurrently. Both the
`electronic information processing device and peripheral
`card may play a role in determining when the latter is
`selected. The card includes information in the CIS
`which tells the host the address decodings the card may
`be configured to perform. The host then programs the
`card to perform a particular decoding using the card's
`Configuration Registers.
`
`

`
`5,436,621
`
`7
`The PCMCIA memory only interface signals illus(cid:173)
`trated in FIG. 3 and FIG. 4 are detailed in the following
`text along with their functions. Signals AO through A25
`are address-bus-input lines which enable direct address
`of up to 64 megabytes of memory on the card. Signals 5
`DO through D15 constitute the bidirectional data bus.
`The -CEl signal enables even-numbered-address bytes
`and -CE2 enables odd-numbered-address bytes. A mul(cid:173)
`tiplexing scheme based on AO, -CEl and -CE2 allows
`8-bit microcomputer hosts to access all data on DO 10
`through D7 if needed. The -OE line is used to gate
`Memory Read data from the memory card. The
`- WE/-PGM input signal is used for strobing Mem(cid:173)
`ory Write data into a PCMCIA memory card. This line
`is also used for memory cards employing programmable 15
`memory technologies. A Ready/Busy function is pro(cid:173)
`vided by the +RDY/-BSY signals when the periph(cid:173)
`eral card and the microcomputer host socket are config(cid:173)
`ured for the Memory-Only Interface. The -CDl and
`-CD2 signals provide for proper detection of memory- 20
`card insertion. Their signal pins are located at opposite
`ends of the connector to ensure a valid detection (i.e.,
`ensuring both sides of the card are firmly inserted). In a
`conventional implementation of the PCM CIA memory
`only interface, the -CDl and -CD2 signals are con- 25
`nected to ground internally on the memory card and
`will be forced low whenever a card is placed in a host
`socket. The present invention implements grounding of
`the -CDl and -CD2 signals using electronic means such
`as an open collector transistor, an integrated circuit 30
`driver, or the like. This implementation allows the mes(cid:173)
`saging peripheral 100 to request service from the elec(cid:173)
`tronic information processing device 200 by toggling
`the state of the -CDl and-CD2 lines, thereby "tricking"
`the
`electronic
`information
`processing
`device's 35
`PCMCIA interface driver into thinking that the mes(cid:173)
`saging peripheral was temporarily removed (discon(cid:173)
`nected) from the electronic information processing de(cid:173)
`vice 200. Since the PCMCIA interface driver as defined
`in the PCMCIA specification must interrogate a 40
`PCMCIA card when inserted (e.g., when ground is
`detected on the -CDl and -CD2 lines), this procedure
`essentially allows a PCMCIA memory only interface
`card to request service from a host device in a fashion
`similar to an interrupt as defined in the PCMCIA 1/0 45
`interface standard. The WP output signal is used to
`reflect the status of the card's Write Protect switch. The
`- REG signal is kept inactive for all Common Memory
`access. The signals BVDl and BVD2 are generated by
`the memory card as an indication of the condition of its 50
`battery. The VPPl and VPP2 signals supply program(cid:173)
`ming voltages for programmable-memory operation, or
`additional supply voltages for peripheral cards. The
`Vee and GND input pins are located at symmetrical
`positions on the memory card to provide safety in the 55
`case of an inverted-card insertion. The Refresh signal is
`intended for pseudostatic SRAMS (PSRAM). Several
`pins have been identified as Reserved for Future Use
`(RFU). The +RESET signal clears the Card Configu(cid:173)
`ration Option Register thus placing a card in an uncon- 60
`figured (Memory-Only Interface) state. It also signals
`the be