(12) United States Patent
`lkehashi et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,643,180 B2
`Nov. 4, 2003
`
`USU06643180B2
`
`SJEUULII Kitagawa
`6,065,141 A *
`TIZUDCI Saito
`5_.(t94_.373 A "
`912000 Tsuji
`6,ll8_.'."l|T| A ’5‘
`9.32002 Doislii
`6,449,182 B1 *
`6_.462_.93S B2 "‘ 1012002 Ilosono et. al.
`
`
`
`?l4;’711
`3fi5;‘l85.22
`3651200
`365,163
`3G5x'.lS5.09
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`2000-149 588 A
`
`532000
`
`* cited by examiner
`
`Pn'mor_y Emtrtmer—Davitt Nelms
`A.s'.3'i.\'tnrtt Exantt'ner—Gene N. Anduong,
`(74) AIt‘ome)g Agent, or Ffrm—Banner 8: Witcolf, Ltd.
`
`(57)
`
`ABSTRACT
`
`ln a method of testing a nonvolatile semiconductor memory
`integrated on a semiconductor chip oomprising a memory
`cell array, 3: Iirst register that stores an address of at defective
`region in the memory cell array, 3 plurality of internal
`voltage generator circuits, and a second register, the second
`register storing, a trimming value for selling an internal
`voltage value generated by each of the internal voltage
`generator eireuits, the testing method eanies out resetting
`the address of the defective region stored in the tirst register
`and the trimming value stored in the second register, and
`setting the address of the defective region stored in the first
`register and the trimming value stored in the second register
`to £1 value according to 21 property of each of the semiann-
`ttuctor chips, wherein the testing,
`is carried out without
`turning a power supply off after the power supply has been
`turned on.
`
`(54) Sl:lMlC()NDUC'l'()R MEMORY DEV [CE
`WITH 'l‘EST MODE
`
`(75)
`
`Inventors: Tnniio lkeliaslii, Yokohama (JP); Ken
`Takeuchi, Tokyo (JP); Toshihiko
`Himeno, Yokohama (JP)
`
`('13) Assignee: Kahushiki Keisha Toshiba, Minato-Ku
`(JP)
`
`{ * } Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C‘. l54{b) by 0 days.
`
`(21) Appl. No: 09t'968,7lJ6
`
`(3.
`
`Filed:
`
`Oct. 2, 2001
`
`(65)
`
`Prior Publication Data
`
`US 2I'J02;"0'04819] A] Apr. 25, 2002
`
`Foreign Application Priority Date
`(30)
`Oct. 3, 2000
`(JP)
`.................................
`2000-303854
`
`Int. Cl." .............................................. .. G11C 16106
`(51)
`(52) U.S. C].
`.......................... .. 365118522; 365118509;
`365.-“189.12; 3651200
`(58) Field of Search ............................... .. 3651200, 201,
`365_.t230.D3, 230.06, 221, 189.02, 189.05,
`189.12, 185.22, 185.19, 185.09; 714-1710,
`711, 713, 42
`
`(56)
`
`References Cited
`U.S. PATENT DOCTUMEN IS
`
`5,8t|8,94:t A ‘-‘
`
`911008 Yoshitake et at.
`
`365E200
`
`7 Claims, 23 Drawing Sheets
`
`!'CE
`0
`
`IRE ME ALE
`o
`o
`
`CLE
`
`V004
`
`
`
`1
`
`NVIDIA 1004
`
`NVIDIA 1004
`
`

`
`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 1 of 23
`
`US 6,643,180 B2
`
`/cs
`
`/RE /we ALE
`
`CLE
`
`:/00-7
`
`
`
`17
`
`Address
`Buffer
`
`I Bad Column
`
`Add. Register
`
`
`
`Column Gate
`
`14
`
`Generators
`
`Trim. Data
`Register
`
`
`
`Trim. Data
`Register
`
`
`
`FlG.1
`
`2
`
`

`
`US. Patent
`
`Nov. 4,2003
`
`Sheet 2 of 23
`
`Us 6,643,180 B2
`
`I
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`I
`I
`
`3
`
`

`
`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 3 of 23
`
`US 6,643,180 B2
`
`Wafer Test Sequence
`
`DC Test
`
`Default Reset
`
`Timer & Voltage Trimming
`
`Bad Col. Detect & Repair
`
`Good Block Search
`
`Vpgm Initial Value
`Trimming
`
`Bad Block Detection
`
`Option Set
`
`ROM—fuse Program
`
`Power Off. On
`Verification of Register State
`
`F|G.3
`
`4
`
`

`
`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 4 ms
`
`US 6,643,180 B2
`
`-__ _ _ _ . _ _ -____....¢-...._..
`
`
`
`TMCLK
`
`3% '
`
`
`
` Reference Clock
`Generator Circuit
`
` Register inc
`
`- Trimming Data
`rst
`
`F I G. 4
`
`F I
`
`5
`
`TMRST
`
`TMINT
`TMCLK
`
`:
`
`:
`
`TINT :
`
`:
`
`I
`100:1:-pulse
`
`r’
`
`|—D§-
`
`H
`
`DEN1
`
`PULSE
`
`Trimming—.—+—:
`45 TMRSTI1
`E
`signal
`:
`J‘
`45
`,9;
`5
`:
`I H
`‘43 T : D. I
`542
`43
`35A"-J"""""""""""""“l U 47
`,_______________________ _, D‘ | 95””
`:
`-
`41
`-
`E
`Trimming—i=-— "B H 1 ETMRS-In
`Signal
`4
`C :
`TMRSTn
`H I
`353 42*‘
`*43 T
`\ 223
`
`:
`
`F I G. 6
`
`5
`
`

`
`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 5 of 23
`
`US 6,643,180 B2
`
`
`
`
`
`In-Inn
`
`6
`
`
`
`

`
`U.S. Patent
`
`Nuv.4,2003
`
`Sheet 6 of 23
`
`US 6,643,180 B2
`
`Repeat 8 times
`
`
`
`Test mode is estabtished
`
`A:Testing Start Command
`B : Register Control Command
`FF* : Testing End Command
`
`FIG.10
`
`TlNT<TE)(T
`
`TMEXT
`
`TMINT
`
`TMCLK
`
`FLAG
`
`F I G. HA
`
`F|G.11B
`
`TMRST
`
`T|NT>TEXT
`
`TMEXT
`
`TMINT
`
`TMCLK
`
`TMR ST
`
`FLAG
`
`7
`
`

`
`.mE
`
`WN
`
`0
`
`3
`
`.6
`
`6...,
`
`MW
`
`1.
`
`2
`
`Bnwso_m
`
`
`
`_.T___H_.T_=H_.I..I"
`
`
`
`
`
`..__.m..._..Hmafia..__.m.._._n83.0._.mmmn__.Hwasm
`
`
`
`
`
`n33._2..,_§_.._8Em.ac_EmmaE23.
`
`
`
`
`
`M TM_o._Eoo._Bm_mmw_.5.so_n_
`
`Wmm3me,oz
`
`%mmmmm
`3oz.33.:u33.25m”.;
`
`8
`
`5
`
`
`

`
`BGR
`
`Vbgr
`
`Circuit >
`
`55
`
`biasn
`
`US. Patent
`
`Nov. 4, 2003
`
`Sheet 3 0:23
`
`US 6,643,180 B2
`
`64
`
`VREFTEST
`
`V
`'
`
`m\
`
`F’ 65
`
`-
`>
`
`M _t
`3%”
`
`%
`
`5‘
`
`; x5,
`
`uutnutwref)
`
`-I—TVREFO"3
`FLAG 2]
`
`
`
`
`53
`
`52".
`FLAG
`
`63f
`
`F I G. 13
`
`9
`
`

`
`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 9 0f23
`
`US 6,643,180 B2
`
`Repeat 16 times
`
`
`
`____ ,_
`
`Voftage Input
`
`Voltage Input
`
`
`
`Test mode is established
`
`A : Testing Start Command
`B : Register Control Command
`FF* :Testing End Command
`
`F|G.15
`
`Vread
`Charge Pump
`
`
`
`
`
`10
`10
`
`

`
` U.S.Patent
`
`Nov. 4, 2003
`
`Sheet 10 of 23
`
`US 6,643,180 B2
`
`355.B.3532
`
`S_.B__u_a
`
`_m_u._:_
`
`s_§_£_o
`
`_mcE
`
`.-:........................................................:_§_>
`
`
`
`Q33Em.a._.
`
`11
`
`
`

`
`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 11 of 23
`
`US 6,643,180 B2
`
`Main PBs
`C01. Redundancy
`(1 02-4+32Byte)
`(8Byte)
`
`
`I.fl'fl.fl'I.fl' M:
`fljflffljfl
`
`BLTR
`
`Cell
`Army 11
`
`
`I Memory
`
`F—.fl—.K—. W,
`1.53.515‘ W
`IZHIEZI gnd
`
`12
`12
`
`

`
`P3U
`
`4|.mt
`
`m4.,
`
`nmS
`
`SU
`
`aEs_8E
`
`3mm”.pa:
`
`s....£m+§:
`
`13
`13
`
`2B
`
`
`
` .0IH2o_mM,,._%._533.Na%e_omm6.a_m_§
`
`

`
`US. Patent
`
`Nov. 4, 2003
`
`Sheet 13 of 23
`
`US 6,643,180 B2
`
`Column
`Address
`
`Register
`I0-bus Address
`
`Register i(i=0--T)
`
`
`
`14
`14
`
`

`
`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 14 of 23
`
`US 6,643,180 B2
`
`\-
`
`-—————-u-——-«-nn-nnu_——_..---on-an--’
`
`Open Check Read
`
`————————————————————————— --"I
`
`g
`
`5
`:
`E
`
`‘E
`
`E
`:
`E
`
`Bad R/D Col. Detect
`exp.vaJ. = NI '1“
`
`Bad R/D Col. Detect
`exp.val. =Al| '0'
`
`
`
`m
`
`(2)
`
`(3)
`
`(4)
`
`(53
`
`(6)
`
`
`
`
`
`
`
`Isolation Latch Set
`
`
`
`F|G.21
`
`15
`15
`
` Bad Column Detection and Repair
`
`
`Colum R/D
`Register Reset
`
`
`W0 Area Col. Check
`
`R/D Area
`P/B Din/Dout Check
`
`Main Area Col. Check
`
`M ~
`pfugn f;fi‘f[i_,0m check
`
`
`
`
`

`
`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 15 0f 23
`
`US 6,643,180 B2
`
`Bad R/D Column Detection
`
`
`
`Input R/D Access
`Command
`
`
`
`Input Test Command
`TRO or TR!
`
`TRO : exp-val = Ali '0'‘
`TR1 :exp-val =AI|"1"
`
`R/Bn="L"
`Co|.Add. = “D001 1...} I”
`Register Counter Reset
`
`S11
`
`S12
`
`S13
`
`
`
`
`
`
`
`P/B—data = "exp-val“ ?
`(Byte by Byte
`comparison)
`
`
`
`315
`
`Insert. Col. Add. to Register
`Set Index = "1"
`
`
`
`Note:
`Column Address:
`(A0.AI,A2,I,....1]
`does not extist.
`
`
`
`Column Add. Increment
`Register Counter Increment
`
`S17
`
`Register Col. Add}?
`
`
`
`FlG.24
`
`16
`16
`
`

`
`U.S. Patent
`
`New. 4, 2003
`
`Sheet 16 of 23
`
`US 6,643,180 B2
`
`._33_QE5385:28am
`
`..._Hxm
`
`mm»93
`
`..§.<.8E:
`
`my,
`
`mm.0_n_
`
`
`
`.._aM_____rumw_“.m%am.3
`
`mm
`
`mumam
`
`mUE.._=8#_w.m_mm.mM.,9u.32.E3.
`
`
`
`....._§-es.umafia
`
`€85.582;3£3
`
`17
`17
`
`
`
`L__=4"_m>uaxm_FE.EH.522...
`
`__o....pn.%<._8
`
`_.._._u5».
`
`
`
`
`
`EmmaEcsoo,§_m$_
`
`
`
`
`
`.9.__<u_a>ue$”QE.u§EE¢ou.8._...__._n__.__
`
`
`
`
`
`
`
`
`
`
`
`

`
`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 17 of 23
`
`US 6,643,180 B2
`
`Good Block Search
`
`"”,§3,[,l",_.e',l"nir|t,-i,i‘:’at}f,‘::“"
`
`Vpgm_ini
`Register Reset
`
`Program Loop #
`Input
`
`Input Register
`Control Command
`
`Input Register
`Control Command
`
`FlG.27
`
`Repeat This
`
`fixed number
`
`Input Initial
`Block Address
`
`Block Erase
`
`
`
`
`Manual All "0"
`Program (Vpem fix)
`
`Input Address Register
`Control Command
`
`
`
`
`
`
`
`
`
`Manual All "0"
`Program (Vpgm fix]
`
`Central Command
`
`Input Address Register
`
`F|G.26
`
`18
`18
`
`Repeat This
`Sequence for
`fixed number
`
`

`
`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 13 of 23
`
`US 6,643,180 B2
`
`Status
`
`Status
`
`Status
`Fai!
`
`P355
`
`Pass
`/\
`
`I ’ f
`
`o n ¢ u - 0
`
`I I,
`
`F
`
`2
`
`3
`
`4
`
`5
`
`Sequence
`
`Bad Brock Detection
`
`
`
`
`
`
`Read All "1" Check
`
`
`
`
`
`
`Phys. "/ Program
` Read "/C" Check
`
`19
`19
`
`WET?!
`
`E E
`
`-
`
`
`
`I
`
`Auto
`Sequence‘
`
`Program
`
`Step-Up
`
`F |
`
`(3)
`
`W <
`
`5’
`
`(7)
`
`FlG.30 ‘8’
`
`

`
`US. Patent
`
`Nov. 4, 2003
`
`Sheet 19 0f23
`
`US 6,643,180 B2
`
`101
`
`Bad Block #
`
`Counter
`
`Row Adwess
`Buffer
`
`14
`
`13
`11
`
`C°'“m" Gate
`
`Nemonr Cell Array
`
`106
`
`L
`
`173
`B|k.Add.PreDecoder
`
`1 U3
`
`102
`
`E RowDecoder
`
`
`
`
`10
`
`
`
`“*4
`
`
`
`
`
`V
`
`4
`r /4' a ,. / Selected7
`mm
`
`
`108
`
`Bad Block
`
`Ffag Register I07
`
`109
`
`5
`
`1%
`
`20
`20
`
`

`
`U.S. Patent
`
`Nov. 4,2003
`
`Sheet 20 of 23
`
`US 6,643,180 B2
`
`Read A“ "1' Check
`
`Simul. Verify
`Read of All "1"
`
`Page Add. = 0
`
`EVEN
`
`Page
`
`odd
`D339
`
`even
`
`DREE
`
`Simul. Verify
`Read of All '1"
`
`Page Add. =
`
`Simul. Verify
`Read of All '1 "
`
`\-.4.__.--ov
`
`Increment Block Add.
`and Repeat Above Sequence
`\ _ , . . _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____..___—_____-._.___._..______u
`
`—_.—..—_..../
`
`;
`
`21
`21
`
`

`
`US. Patent
`
`Nov. 4, 2003
`
`Sheet 21 M23
`
`Us 6,643,180 B2
`
`Read All "C" Check
`
`Simul. Verify
`Read of All “I”
`
`Input Fiag Set
`Command
`
`Simu!.Verify
`Read of Al!'U'
`
`Input Flag Set
`Command
`
`Simul. Verify
`Read of All "1"
`
`Input Flag Set
`Command
`
`
`
`Simul. Verify
`Reed of All "0"
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page Add. =0
`
`Page Add. = 1
`
`even
`
`Page
`
`D333[
`
`9388
`
`t
`
`
`
`________—..\’—__—-—_--.-___........---..—...._._—----_----.._----—..----_.—..___-.----_.._..-...-.-..--___—-___---_..-.-_-..‘
`
`Input Flag Set
`Command
`
`Refieétt Untill Page Add.=31 5
`
`Increment Block Add.
`and Repeat the Above Sequence
`_ _ _ _ . _ _ _ _ _ . _ _ . _ _ . _ _ . . _ _ _ _ . _ _ _ _ _ _ _ _ _ _ _ . _ _ _ _ _ _ _.-
`
`22
`22
`
`

`
`US. Patent
`
`Nov. 4, 2003
`
`Sheet 22 of 23
`
`US 6,643,180 B2
`
`Baci_Qlock Flag if Count
`
`
`
`Command Input
`
`R/Bn = "L."
`Blk. Add. Reset
`Bad Blk Counter Reset
`
`Status Register Reset
`
`Blk Flag ="Bad Blk“?
`
`
`
`Bad Blk Counter Increment
`
`
`
`Colurm Add. increment
`Register Counter Increment
` Bad Block
`
`Counter Max .?
`
`
`
`
`
`
`
`Block Address Increment
`
`Set Status="FA|L"
`
` Block Add. Max?
`
`FlG.33
`
`23
`23
`
`

`
`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 23 0f 23
`
`US 6,643,180 B2
`
`Third Bit
`
`Second Bit
`First Bit
`_\ i /.' Register State
`
`100
`
`.
`First Test
`
`Pass
`
`no
`
`Pass
`
`Fail
`
`01 0
`
`/Second Test
`Fad
`
`Pass
`
`no
`
`my ‘ail
`
`100
`
`Pasy \Fai|
`
`010
`
`Pasy {ail
`
`Third Test
`000 /
`
`Patsy \FaiI
`
`I11
`
`110
`
`101
`
`100
`
`011
`
`010
`
`001
`
`000
`
`F|G.34
`
`
`
`
`
`
`
`
`
`
`
`
`FlG.35
`
`24
`24
`
`

`
`US 6,643,180 B2
`
`SEMICONDUCTOR MEMORY DEVICE
`WITH TEST MODE
`
`CROSS—REFERENCE TO RELATED
`APPLICATIONS
`
`'Ihis application is based upon and claims the benefit of
`priority from the prior Japanese Patent Application No.
`ZILIOUI-303854, filed Oct. 3, 2000, the entire contents of which
`are incorporated herein by reference.
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`"the present invention relates to a semiconductor device
`having a pulse generator circuit and an internal voltage
`generator circuit, the semiconductor device being capable of
`adjusting values of a pulse width of the pulse generated by
`these circuits and a value of an internal voltage. More
`particularly, the present invention relates to a nonvolatile
`semiconductor memory that internally generates a reference
`voltage, a writing voltage, a erasure voltage, and a readout
`voltage.
`2. Description of the Related Art
`An NAND type flash memory that is one type of non-
`volatile semiconductor memory is announced by literature
`such as K. Imamiya et. al. “A 130-mm” 256-Mb NAND
`Flash with Shallow Trench Isolation Technology”, IEEE. J.
`Solid State Circuits, Vol. 34, pp. 1536-1543. Novetnher
`1999” or the like.
`
`In such a nonvolatile semiconductor memory, voltage
`trimming and defective cell redundancy replacement are
`carried out in a wafer test process.
`FIG. 35 is a flowchart showing an outline of a conven-
`tional wafer testing process. The operating contents of each
`process are as follows.
`In a DC test, DC checks such as contact check and
`standby current are made.
`In Vref (reference voltage)
`trimming, Wref of each chip on a wafer is monitored, and
`then, it is computed as to what a trimming value should be
`determined inn order to correct these to a target value.
`Next, Vpgm (writing voltage) initial value trimming is
`carried out.
`In a NAND type flash memory,
`there is
`employed Incremental Step Pulse Programming Scheme
`that increments a writing voltage Vpgm from an initial value
`in a stepwise manner. This method is described in “K. D.
`Suh et. 31., “A 3.3 V 32 Mb NAND Flash Memory with
`Incremental Step Pulse Programming Scheme", “ISSCC
`Digest of Technical Papers, pp. 123-129, February 1995",
`for example. In this writing method, it is required to opti-
`mize an initial value of Vpgm in order to ensure that a write
`time (or write loop count] is included within a predeter-
`mined time (count). For that purpose, it is required to find a
`block (good block} that can be written and erased from the
`inside of a memory cell array. This is because redundancy
`replacement of a defective cell is not carried out at this step.
`If a good block is found, writing is carried in that block
`while an initial value of Vpgm is changed, and an optimal
`value is determined.
`
`Subsequently, voltage trimming fuse cutting is carried
`out. At this step, a wafer is moved to a laser blow unit, and
`fuse cutting is carried out according to the above Vrel‘
`trimming and a trimming value determined by Vpgnt initial
`value trimming.
`Subsequently, defective columnfrow detection is carried
`out. Here, for redundancy replacement, some data patterns
`
`10
`
`15
`
`BL’!
`
`35
`
`40
`
`2
`are written into a memory cell array, and a defective
`column,-“row is detected.
`
`Next, redundancy fuse cutting is carried out. Here, a wafer
`is moved to a laser flow unit again, and fuse cutting of
`redundancy replacement is carried out.
`In this flowchart, voltage trimming fuse cutting is carried
`out before detecting a defective colum n.-‘row because there is
`a possibility that, if defective columnirow detection is car-
`ried cut in a state in which an internally generated voltage
`such as Vpgm is shafted, a defect cannot be found.
`A testing time at the above described wafer testing step is
`reflected in chip cost. Therefore, in order to reduce a chip
`cost, it is required to reduce a test time to the minimum while
`required wafer testing is carried out.
`there are two
`At
`the above described wafer test step,
`factors that a test time is increased. One lies in the existence
`of a fuse cut step itself. In order to carry out fuse cutting by
`means of laser blowing, it is rcq uircd to remove a wafer from
`a tester, and move the wafer to a laser blow unit. Here, a time
`overhead is produced. At
`the above described wafer test
`step, in particular,
`it is required to carry out fuse cutting
`separately twice, thus making the overhead more significant.
`The second factor lies in a tester computation time, in
`order to reduce a test time. commands are assigned to about
`100 chips at the same time at the wafer test step, and a tester
`is used such that an output can be measured at the same time,
`However, such a tester cannot carry out completely in
`parallel an operation for computing a trimming value from
`a monitored voltage or an operation for detecting a defective
`column row from a readout data pattern. A maximum of 10
`chips can be processed in parallei. Therefore, even ifdata for
`100 chips can be acquired at the same time, operational
`processing for such data must be canied out by being
`divided by 10 times, and here, a time overhead occurs.
`A method for reducing a time for the fuse cutting step of
`the above two factors is described by the invention relating
`to application of Japanese Patent Application Publication
`No. l1-351396 made by the Applicant. The outline is given
`below.
`
`in a nonvolatile semiconductor memory, a memory cell
`can store information in a nonvolatile manner. Thus, if a
`voltage trimming value or redundancy information is stored
`in a memory cell array, fuse and fuse cutting step can be
`eliminated. ‘When a nonvolatile semiconductor memory is
`placed in a normal operation state, although it is required to
`store the previous trimming value or redundancy informa-
`tion in a predetermined register, the storage operation, i.e.,
`an operation for acquiring information from the inside of a
`memory cell array,
`thereby storing the information in a
`register may be carried out at a time when a power is
`supplied to a nonvolatile semiconductor memory.
`BRIEF SUMMARY OF THE INVENTION
`
`According to an aspect of the present invention, there is
`provided a semiconductor device comprising:
`a bit line;
`a plurality of memory cells connected to the bit line; and
`a sense amplifier connected to one end of the bit line; and
`a defect detector circuit configured to read out data by the
`sense amplifier while setting a plurality of memory
`cells connected to the bit line all to a nonvselected state,
`and the other end of the bit line being connected to a
`predetermined potential via a switch, and an open-
`circuit defect of the bit line being detected according to
`a readout data by the sense amplifier.
`
`60
`
`65
`
`25
`25
`
`

`
`US 6,643,180 B2
`
`‘4:
`
`.16
`
`3
`invention,
`According to another aspect of the present
`there is provided a semiconductor device comprising:
`El memory cell array in which programmable and erasable
`nonvolatile memory cells are arranged in column and
`row directions of a matrix;
`an address register that can store an address of a unit of
`memory cells which are programmed and erased simul-
`taneously in the memory cell array; and
`a co-ntro] circuit that carries out an erase verify operation
`C0liiiEUTfdi0°'1iPUi3"P355”Dr“i3i1”5igi1f|1ficcfiidilig 10
`to whether or not all the memory cells targeted for
`erasing are *:r3S'5d: 3___""'riie
`rjPera1ir(in_"fr~‘1g_ig1“red
`""
`‘O °'“P”l
`L
`‘3
`Pnsi’
`"’
`""3nn
`‘"'°°r 'nb_ in
`whether or not all the memory cells targeted for writing
`are written, and an operation activated upon receipt of 1,
`a first command, for, when either of results of the erase
`'
`verify and write verify operations is “fai1“, changing
`data of the address register, and when the results are
`“pass"', disabling change of data of the address register.
`According to a further aspect of the present invention,
`there is provided a semiconductor device comprising a
`register activated by a command input, the register having
`plural types of test operations configured to output a “pass"
`or “fail” signal, wherein,
`if a result of an immediately
`preceding test that has been carried out of the test operations
`is "pass". no data is changed, and if the result is "fail”, data 25
`is set in El predetermined signal state.
`According to a further aspect of the present invention.
`there is provided a semiconductor device having erase verify
`and write verify functions comprising:
`memory cells;
`an address register that can store an address of a unit of
`memory cells which are programmed and erased simul-
`l&l1€D115iY in the IDCIIIOF)’ 0611 aria)’;
`alirst rc-gisterthat storcsa"pass"' and “fail” result after an
`erase verify operation;
`asecoud register that stores a "pass” and "fail” result after
`a write vcrify operation;
`:1 third register provided for each erase unit, the third
`register configured to store a first or second signal state 40
`according to whcthcr or not
`the memory Cells in the
`erase um} aw wn'w_c,-asabte or not; and
`a control circuil activated upon receipt of a first command
`input,the control circuit making an operation such that,
`when at least one of the first register data and second 4,
`register data is“fail", a third register corresponding to
`.
`an address Selected by the addmss regisier is Set to a
`firs, Signal slaw’ and when both of [ht firs, mg]-Ste, dam
`and second register data are “pass", the third register is
`Sci [0 3 wconcl Signal Sum
`According to a further aspect of the present invention,
`there is provided a semiconductor device comprising:
`an internal circuit whose operation or function changes
`basgd an dam Smrcd in a mgistcr; and
`a control circuit that repeatedly makes 2: first operation to 55
`carry out a self-judgment test for the internal circuit
`such that a result of either of “pa.ss" and “fail” is
`outputted and a second operation to carry out a diiferent
`control for the register according to the "pass” or"fail"’
`result in the setf—judgmcnt test, wherein data refiecting so
`the characteristics of each semiconductor device is set
`
`3“
`
`35
`
`Sn
`
`to the register.
`According to a further aspect of the present invention,
`there is provided a semiconductor device comprising:
`an internal circuit in which an output is trimmed in 2”
`different schemes by a register capable of holding N-bit
`data ("where N denotes a positive integer); and
`
`as
`
`26
`26
`
`4
`a data setting circuit that judges in a first test the output
`of the internal circuit while the N-bit data is placed in
`a lirst state, to determine most significant bit data of the
`N-hit data; judges, in a kth test [k-2, 3, _
`_
`. N), while
`data from the most significant hit to a [k—t)th hit is
`maintained to a value determined in a first to (Ii-—1]Ii‘l
`test, the output of the internal circuit with the remaining
`bit being placed in a predetermined value to determine
`a kth bit data; and sets data refiecting characteristics of
`each semiconductor device to the register by the N
`test;
`According‘ to a further aspect of the present ‘invention,
`there is provided a semiconductor device comprising:
`H
`h
`.
`1
`.
`d
`3 m'm.:'°r5i C6
`.may “mg 3 C0 um“ nigh)" in 3 row
`E310" 1" Whlcll m°m,°ry C6“? are “Hanged m Column
`and 70”’ d1r°"'n°n’5 ‘n “ nnnnxi
`a redundancy column region having M redundancy col-
`umns for replacement with a defective column in the
`memory cell array;
`M registers configured to store column addresses to be
`replaced with the redundancy columns, each of the M
`registers including a latch placed to a first or second
`signal state according to whether or not a correspond-
`ing redundancy column can be used:
`a sense amplifier;
`a counter that selects the M registers sequentially;
`a judgment circuit that makes a judgment on wliether or
`not data of a selected column outputtcd from the sense
`amplifier coincides with a predetermined expected
`Value 3115‘ 0niP'-U5 3 “P355” or "rail" Signal ancnrding to
`8 l“¢Sllil Di lilfi judgment; ItIJCi
`a control circuit that sets a column address and the counter
`to a start address, when a defective column in the
`memory cell array is to be detected; makes, if an output
`Di “'16 judgment Cifcllil is “1J-'15-S", all il1Cl'€l11€l'l1
`0i H16
`column address, and,
`if the output of the judgment
`Circllilirs “r‘5l_ii"3Udir1_3i3“«'h Orin? register Selecind by
`‘he Connler '5 Pinned in inn fir“ Slgrial 5'-31¢» Sivnrfin ‘he
`column address in the register and thereafter making an
`increment‘ of the column address and the counter;
`makes an ll'ICl'C'I']'I€1']l oi the counter until the counter has
`rifncncd 3 rci_="5tcr whnnn latch inlplnccd '" inc lnrnl
`nlgnil Sun“ If ‘n‘’ nninnl of in‘? Judgment ‘nrnnn ‘5
`"fnni and the lnicn nt
`the rennin” Selected by inn
`counter is placed in the second signal state, thereafter,
`stores the column address in the register, and thereafter,
`makes an Increment nf ‘ne Cnlnmn adnress and ‘he
`counter, and performs the operations until the counter
`nag nan‘-'n‘*‘:l "‘n_ end ‘""n"'rnn “‘n‘lr“5*"-
`,
`,
`Ac°:0"‘nn3_ ['3' 3 llllilhnr aniiccl Dr in‘: Prcscnl _1nVnn“'nn'
`mam '5 primdcd a Sc”:"mmi"cmr dcvwc mnnmmngi
`a memory cell array in which programmable and erasable
`niinvolallln memory mun are amlnged In Column and
`row d"°°“_°m of & maul)“
`3 5°n5‘3 3rnPl1fi‘*r?
`a bit line extending in the column direction, configured to
`transmit data of the memory cell array to the sense
`amplifier; and
`a column defect detecting circuit that detects a defective
`column of the memory cell array, without carrying out
`writing and erasing operation for the memory cells.
`According to a further aspect of the present invention,
`there is provided a method of testing a semiconductor
`device , the semicoriductor device comprising: El memory cell
`array in which programmable and erasable nonvolatile
`
`

`
`US 6,643,180 B2
`
`5
`memory cells are arranged in column and row directions of
`a matrix; an address register that can store an address of a
`unit of memory cells which are programmed and erased
`simultaneously in the memory cell array; and a control
`circuit that carries out an erase verify operation for output-
`ting a “pass” or "Fail" signal according to whether or not all
`the memory cells targeted for erasing are erased, a write
`verify operation for outputting the “pass" or “fail" signal
`according to whether or not all the memory celts targeted for
`writing are written, and an operation activated upon receipt
`of a first comniand, for, when either of results of the erase
`verify and write verify operations is "fail”, changing data of
`the address register, and when the results are "pass", dis-
`abling change of data of the address register, wherein in the
`method of testing a semiconductor device, series of opera-
`tions comprising an erasing operation, an erase verify
`operation, a writing operation, a write verify operation and
`the first command input are repeated a plurality of times, to
`find a write-erasable region in a memory cell array.
`According to a further aspect of the present invention,
`there is provided a method of testing a semicondttctor
`device,
`the semiconductor device comprising a register
`activated by a command input, the register having plural
`types of test operations for outputting a “pass" or “fail”
`signal. wherein. if a result of an immediately preceding test
`that has been carried out of the test operations is "‘pass", no
`data is changed, and if the result is "fail”, data is set in a
`predetermined signal state, wherein in the method of testing
`a semiconductor device, plural types of the test operations
`are carried out, and thereafter, it isjudged whether or not the
`register data is set to a predetermined signal state to judge
`whether the semiconductor device is nonnal or defective.
`According to a further aspect of the present invention,
`there is provided a method of testing a semiconductor device
`integrated on a semiconductor chip,
`the semiconductor
`device comprising a memory cell array that comprises
`nonvolatile memory cells; a first register that stores an
`address of a defective region in the memory cell array; a
`plurality of internal voltage generator circuits; and a second
`register provided corresponding to each of the plurality of
`internal voltage generator circuits, the second register stor-
`ing a trimming value for setting an internal voltage value
`generated by each of the internal voltage generator circuits,
`the semiconductor device being integrated on a semicon-
`ductor chip, the method of testing a semiconductor device,
`comprising:
`resetting the address of the defective region stored in the
`first register and the trimming value stored in the
`second register; and
`setting the address of the defective region stored in the
`first register and the trimming value stored in the
`second register to a value according to a property of
`each of the semiconductor chips, wherein the testing is
`carried out without turning a power supply oft’ after the
`power supply has been turned on.
`According to a further aspect of the present invention,
`there is provided a method of testing a semiconductor device
`integrated on a semiconductor chip,
`the semiconductor
`device comprising a.n internal circuit in which an operation
`or function is changed based on data stored in a register, the
`method of testing a semiconductor device, comprises:
`a first operation configured to cause the internal circuit to
`carry out a sell’-judgment test such that a result indi-
`cating either “pass" or “fail" is outputted, and
`a second operation configured to carry out for the register
`at control that is t.lllI6l't:l'l[ depending on the result oi‘
`“pass“ o-r " fail“ in the self-judgment test, wherein the
`
`10
`
`15
`
`iii
`
`35
`
`40
`
`50
`
`60
`
`65
`
`6
`first operation and second operation are repeated alter-
`nately in a predetermined nutnber of times to set for the
`register data reflecting characteristics of each of the
`semicondttctor chips.
`According to a further aspect of. the present invention,
`there is provided a method of testing a semiconductor
`device, the semiconductor device having an internal circuit
`in which an output is trimmed in 2” different schemes by a
`register capable of holding N-bit data (where N denotes a
`positive integer), the method of testing a semiconductor
`device comprising:
`the output of the internal circuit
`test
`judging in a first
`while the N—hit data is placed in a
`first state,
`to
`determine most significant bit data of the N-bit data;
`judging, in a kth test (lr==3. 3. .
`.
`. N). White data from the
`most significant bit to a (k—1)th bit is maintained to a
`value determined in a first to (k—t)th test, the output of
`the internal circuit with the remaining bit being placed
`in a predetermined value to determine a kth bit data;
`and
`
`setting data reflecting characteristics of each semiconduc-
`tor device to the register by the N tests.
`According to a further aspect of the present invention,
`there is provided a method of testing a semiconductor
`device, the sem iennductor device comprising a memory cell
`array in which programmable and erasable nonvolatile
`memory cells are arranged in column and row directions of
`a matrix; a sense amplifier; and a bit line extending in the
`column direction, configured to transmit data of the memory
`cell array to the sense amplifier, wherein,
`the method of testing a semiconductor device, comprises
`determining whether or not an open-circuit, shon-
`circuit or leak is presented in the bit
`line and sense
`amplifier to detect a defective column of the memory
`cell array, without carrying out writing and erasing
`operation for the memory cells.
`According to a tttrther aspect of the present invention,
`there is provided a method of detecting and replacing a
`defective column in a semiconductor device, the semicon-
`-ductor device comprising a memory cell array having a
`column region and a row region in which memory cells are
`arranged in column and row directions of a matrix; a
`redundancy column region having M redundancy columns
`for replacement with a defective column in the memory cell
`array; M registers configured to store column addresses to be
`replaced with the redundancy columns, each of the M
`registers including a latch placed to a first or second signal
`state according to whether or not a corresponding redun-
`dancy column can he used; a sense amplifier; a counter that
`selects the M registers sequentially; and a judgment circuit
`that makes a judgment on whether or not data of a selected
`column outputted from the sense amplifier coincides with a
`predetermined expected value and outputs a “pass” or “fail”
`signal according to a result of the judgment, wherein,
`the method of detecting and replacing a defective column
`in a semiconductor device comprising:
`setting a column address and the counter to a starting
`address, when a defective column in the memory cell
`array is to be detected;
`making, if an output of the judgment circuit is “pass”, an
`increment of the column address, and, if the output of
`the judgment circuit
`is “fail” and the latch of the
`register selected by the counter is placed in the first
`signal state, storing the column address in the register
`and thereafter making an increment of the column
`address and the counter after;
`
`27
`27
`
`

`
`US 6,643,180 B2
`
`7
`making an increment of the counter until the counter has
`reached a register whose latch is placed in the first
`signal state,
`if the output of the judgment circuit
`is
`“fail" and the latch of the register selected by the
`counter is placed in the second signal state, thereafter,
`storing the column address in the register, and
`thereafter, making an increment of the column address
`and the counter; and
`
`‘4:
`
`carrying out the almve operations; until the counter has
`reached an end coiumn address.
`
`10
`
`BRIEF DESCRIPTION OF THE SEVERAL
`VIEWS OF THE DRAWING
`
`FIG. I is a block diagram showing a schematic configu-
`ration of a NAND type flash memory according to the
`present invention;
`FIG. 2 is a circuit diagram showing a configuration of a
`part ol'a memory cell array ofthe rnernory shown in FIG. 1;
`FIG. 3 is a flowchart showing a wafer test step of the
`memory shown in FIG. 1;
`FIG. 4 is a circuit diagram showing a specific configura-
`tion of a timer circuit 22 shown in FIG. 1, a trimming data
`register 23, and a circuit in a control circuit 25 relating to
`these circuits;
`FIG. 5 is a timing chart showing an example ofop-eralion
`of the circuit shown in FIG. 4;
`FIG. 6 is a circuit diagram showing a specific example of
`a reference clock generator circuit 22B shown in FIG. 4;
`FIG. 7 is a circuit diagram showing an exemplary specific
`configuration of a variable resister circuit R shown in FIG.
`6;
`
`FIG. 3 is a circuit diagram showing a detailed configu-
`ration of a trimming data register 23 shown in FIG. 4;
`FIG. 9 is a view showing a relationship between data in
`the register 23 shown in FIG. 8 and a deviation (ATint) of a
`time TINT;
`FIG. 10 is