(12) United States Patent
`Tanaka et al.
`
`I lllll llllllll Ill lllll lllll lllll lllll lllll 111111111111111111111111111111111
`
`US007000160B2
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,000,160 B2
`Feb.14,2006
`
`(54) SEMICONDUCTOR INTEGRATED CIRCUIT
`AND A METHOD OF TESTING THE SAME
`
`(75)
`
`Inventors: Toshihiro Tanaka, Akiruno (JP);
`Yutaka Shinagawa, Iruma (JP);
`Masahiko Kimura, Kodaira (JP); Isao
`Nakamura, Fussa (JP)
`
`5,760,599 A * 6/1998 Ehiro
`......................... 324/765
`5,886,657 A * 3/1999 Ahuja ........................ 341/144
`6,114,920 A * 9/2000 Moon et al. ................ 331/179
`6,529,247 B2 * 3/2003 Tagomori et al. ........... 348/657
`6,819 ,596 B2 * 11/2004 Ikehashi et al.
`. ... ... 365/185.22
`2004/0042331 Al * 3/2004 Ikehashi et al.
`............ 365/232
`
`(73) Assignees: Renesas Technology Corp., Tokyo
`(JP); Hitachi ULSI Systems Co., Ltd.,
`Tokyo (JP)
`
`GB
`JP
`
`FOREIGN PATENT DOCUMENTS
`
`2 197 554
`5-265579
`
`* 5/1988
`10/1993
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 659 days.
`
`* cited by examiner
`
`(21) Appl. No.: 10/083,399
`
`(22) Filed:
`
`Feb.27,2002
`
`(65)
`
`Prior Publication Data
`
`US 2002/0153917 Al Oct. 24, 2002
`
`(30)
`
`Foreign Application Priority Data
`
`Apr. 24, 2001
`
`(JP)
`
`(51)
`
`Int. Cl.
`GOIR 31/28
`
`(2006.01)
`
`2001-125275
`
`(52) U.S. Cl. ........................................ 714/724; 324/765
`(58) Field of Classification Search ................. 714/724,
`714/819; 324/765, 771
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,261,082 A * 11/1993 Ito et al. ..................... 713/501
`
`Primary Examiner-Phung My Chung
`(74) Attorney, Agent, or Firm-Miles & Stockbridge P.C.
`
`(57)
`
`ABSTRACT
`
`A semiconductor integrated circuit (LSI) in which control
`information for determining a voltage or a width of a pulse
`produced itself can easily be set in parallel with other LSis,
`and set information can be corrected easily. From an external
`evaluation device, a voltage of an expected value is supplied
`in overlapping manner to a plurality of LSis each having a
`CPU and a flash memory. Each LSI incorporates a compari(cid:173)
`son circuit comparing an expected voltage value and a
`boosted voltage generated in itself. The CPU refers to a
`comparison result and optimizes control data in a data
`register for changing a boosted voltage. The CPU controls
`the comparison circuit and the data register and performs
`trimming in a self-completion manner, thereby making,
`trimming on a plurality of LSis easily in a parallel manner
`and a total test time reduced.
`
`23 Claims, 29 Drawing Sheets
`
`60
`
`BOOSTING SECTION
`
`64
`
`63
`\
`r-----------------.1.----,
`'
`'
`
`Vpp
`
`62
`
`61
`
`65
`
`VOLTAGE GENERATION
`CONTROL REGISTER
`
`FLASH
`MEMORY
`
`5
`
`2
`
`4
`
`EVALUATION
`DEVICE
`(TESTER)
`
`Vref
`
`18
`
`1
`
`NVIDIA 1003
`
`

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`?'
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`
`~ = ......
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`~
`•
`\JJ.
`d •
`
`------17
`
`16---
`
`1~
`
`1l1
`
`i---..--3
`
`2
`
`CONTROLLER
`
`SYSTEM
`
`4
`~
`
`12
`(
`
`FLASH MEMORY
`
`CONTROLLER
`
`CPU
`
`RAM
`
`BUS CONTROLLER
`
`·~
`
`PORT
`-OUTPUT
`INPUT/
`
`7
`i
`CIRCUIT
`TRIMMING
`VOLTAGE
`
`I
`
`I
`
`1 l
`
`11 c _____.,,.-
`
`1
`
`'
`
`l
`
`•
`
`l
`
`9
`(
`
`CIRCUIT
`TRIMMING
`
`DIVISION
`
`RATIO
`
`1
`
`j
`
`1~
`
`'
`,.
`
`10
`~
`
`14
`~
`
`1
`
`I
`
`1 •
`
`ll
`
`. -
`
`~
`6
`
`Vpp
`
`I BOOSTING
`
`CIRCUIT
`
`-~ FLASH MEMORY
`
`I
`
`~
`
`FREQUENCY
`
`CIRCUIT
`DIVIDING
`
`~
`
`<Pin
`
`~
`
`FIG. 1
`
`OSCILLATION
`
`CIRCUIT
`
`PERIPHERAL
`
`CIRCUITS
`
`I
`
`<P
`
`MICROCOMPUTER
`
`1
`
`2
`
`

`
`U.S. Patent
`
`Feb.14,2006
`
`Sheet 2 of 29
`
`US 7,000,160 B2
`
`FIG. 2
`
`5
`Vpp
`/
`r----- -------------------------------------------------~-----------,
`29
`
`I
`
`TCNT
`
`21
`
`24
`
`DLA
`
`' ' ' I ' I
`
`I
`I
`
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`
`I
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`I
`I
`I
`
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`
`$/n
`
`11C
`
`15C
`
`15
`
`150
`
`ABUF
`
`150
`
`28
`
`WDEC
`
`CDEC
`
`25
`
`20
`
`26
`
`I
`
`22
`
`27
`
`MEMORY CELL
`ARRAY
`
`------------------
`csw
`
`SAA
`
`DBUF
`
`I
`I
`I
`I
`~-------------------------------------------------------------------~
`
`3
`
`

`
`U.S. Patent
`
`Feb.14,2006
`
`Sheet 3 of 29
`
`US 7,000,160 B2
`
`FIG. 3
`
`REPAIR AND
`TRIMMING MAT
`
`BOOT MAT
`
`USER MAT
`
`1--- Rm at
`
`-- Tm at
`
`--- Mmat
`
`H' 00002008
`
`H' 00002000
`
`H' 00000000
`H'XXXXXXXX
`
`H' 00000000
`
`4
`
`

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`
`I 17
`
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`
`3
`~
`
`Vref
`
`4
`
`2
`
`5
`
`SIGNAL
`CONTROL
`START
`EXECUTION
`PROGRAM
`
`I
`
`11 RAM
`
`I FLASH I I CPU
`
`MEMORY
`
`15
`
`71
`
`REGISTER
`TRIMMING
`
`VOLTAGE GENERATION
`
`CONTROL REGISTER
`
`DECODER
`
`65
`
`61
`
`REFERENCE
`
`VOLTAGE
`
`EVALUATION
`
`(TESTER)
`DEVICE
`
`Vss
`
`70
`
`~
`
`I
`
`I
`
`I
`
`I
`
`62
`
`Vpp
`
`FIG. 4
`
`I L ___ J ___ 1 ___ L __ ::r:_ _____ J
`:+1TL_j
`i
`I
`I
`~
`I
`I
`r-----------------~----,
`
`\ ' f
`63
`
`f
`f
`
`64
`
`BOOSTING SECTION
`
`60--J
`
`1
`
`5
`
`

`
`U.S. Patent
`
`Feb.14,2006
`
`Sheet 5 of 29
`
`US 7,000,160 B2
`
`FIG. 5
`
`START
`
`TRANSFER TRIMMING
`PROGRAM TO INTERNAL
`MEMORY
`
`INPUT VOLTAGE OF
`EXPECTED VALUE
`(EVALUATION DEVICE)
`
`START EXECUTION OF
`TRANSFERRED TRIMMING
`PROGRAM
`
`S1
`
`S2
`
`S3
`
`SET VOLTAGE
`GENERATION CONTROL
`REGISTER
`
`DESIGNATE MINIMUM
`VOLTAGE IN TRIMMING
`REGISTER
`
`EXECUTE TRIMMING PROGRAM
`BY INTERNAL CPU
`
`,,..-._, -84
`
`S5
`
`S6
`
`DECISION BY INTERNAL
`DECISION CIRCUIT
`
`WAIT FOR STABILIZATION
`OF VOLTAGE
`.....-----+-··-··-··-··-··-··-··
`
`DECISION
`REGISTER=O
`
`DECISION
`REGISTER=1
`
`S7
`
`S8
`
`=1
`
`END
`
`UPDATE VALUE IN
`TRIMMING REGISTER
`
`6
`
`

`
`U.S. Patent
`
`Feb.14,2006
`
`Sheet 6 of 29
`
`US 7,000,160 B2
`
`FIG. 6
`
`WAFER OR
`~ EVALUATION BOARD
`
`-
`
`MICRO-
`1~
`COMPUTER
`
`1 ......_,_
`
`1 """--
`
`1--..__
`
`~
`
`~
`
`~
`uad
`13~
`)
`\
`3
`
`EVALUATION
`DEVICE
`(TESTER)
`
`"'---- 18
`
`7
`
`

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`
`DECODER
`
`CONTROL REGISTER
`
`GENERATION
`
`VOLTAGE
`
`EVALUATION
`
`(TESTER)
`. DEVICE
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`REFERENCE
`
`VOLTAGE
`
`VOLTAGE TO BE
`
`COMPARED
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`..._, ...... , -''-"' MESUREMENT
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`VOLTAGE
`
`l(STEP·DOWN) VOLTAGE
`
`•
`
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`BOOSTING CIRCUIT,
`
`TERMINAL
`MEASURING
`
`BOOSTED
`
`FIG. 7 PRIORART
`
`8
`
`

`
`U.S. Patent
`
`Feb.14,2006
`
`Sheet 8 of 29
`
`US 7,000,160 B2
`
`FIG. 8 PRIOR ART
`
`START
`
`SET VOLTAGE GENERATION
`CONTROL REGISTER
`(EVALUATION DEVICE)
`
`WAIT FOR STABILIZATION OF
`VOLTAGE (EVALUATION DEVICE)
`
`MEASURE BOOSTED (STEP-DOWN)
`VOLTAGE THROUGH MEASURING
`TERMINAL (EVALUATION DEVICE)
`
`OUT OF
`TOLERANCE
`COMPUTE TRIMMED VALUE FROM
`VOLTAGE DIFFERENCE
`(EVALUATION DEVICE)
`
`UPDATE TRIMMING REGISTER
`VALUE (EVALUATION DEVICE)
`
`WITHIN
`TOLERANCE
`
`END
`
`9
`
`

`
`U.S. Patent
`
`Feb.14,2006
`
`Sheet 9 of 29
`
`US 7,000,160 B2
`
`FIG. 9
`PRIOR ART
`
`WAFER OR EVALUATION
`BOARD
`
`LSl1
`
`LSl2
`
`LSl3
`
`LSl4
`
`EVALUATION
`DEVICE
`(TESTER)
`
`10
`
`

`
`U.S. Patent
`U.S. Patent
`
`Feb.14,2006
`Feb. 14, 2006
`
`Sheet 10 of 29
`InS
`M
`
`US 7,000,160 B2
`US 7,000,160 B2
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`VOLTAGE GENERATION' I TRIMMING 1------66
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`
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`
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`
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`
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`REFERENCE
`
`VOLTAGE
`
`65
`
`61
`
`73
`
`18
`
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`
`64
`
`BOOSTING SECTION
`
`60
`
`FIG. 11
`
`12
`
`

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`CONSTANT
`
`RESISTOR
`CONSTANT
`
`- CONSTANT
`
`CURRENT
`
`18
`
`RESISTOR
`CONSTANT
`
`TERMINAL
`
`RESISTOR
`CONSTANT
`
`TERMINAL
`
`4
`
`2
`
`EVALUATION
`
`(TESTER)
`DEVICE
`
`3'
`
`SIGNAL
`START CONTROL
`PROGRAM EXECUTION
`
`71
`
`13
`
`REGISTER
`DECISION
`
`Vss
`
`MICROCOMPUTER
`
`MICROCOMPUTER
`
`5
`
`bus
`
`VOLTAGE GENERATION
`
`CONTROL REGISTER
`
`Vbas
`
`,63
`
`--------------C---------
`
`64
`
`SECTION
`
`I
`---~
`I
`'-------------------140_,.-ll----l
`
`.. ·--..
`
`BIAS VOLTAGE tit:Nt:.KA 11v1'1
`...... "...
`
`-----------
`
`70
`
`FIG. 12
`
`;---------------•--------------c:-----1
`
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`
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`
`61
`
`60C
`
`13
`
`

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`
`TERMINAL
`
`.-----< VOLTAGE
`CONSTANT
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`
`620
`
`66
`
`) CONTROL REGISTER
`(!VOLTAGE GENERATION
`
`DECODER
`
`65
`
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`
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`
`VOLTAGE
`
`63
`
`64
`
`BOOSTING SECTION
`NEGATIVE VOLTAGE
`
`600
`
`10
`
`FIG. 13
`
`14
`
`

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`
`VOLTAGE
`REFERENCE
`POSITIVE
`
`Pad
`
`Pad
`
`1-1-REFERENCE
`
`NEGATIVE
`
`VOLTAGE
`
`66
`
`REGISTER
`TRIMMING
`
`VOLTAGE GENERATION
`
`CONTROL REGISTER
`
`Vss
`
`I
`REFERENCE
`
`VOLTAGE
`
`65
`
`61
`
`63
`
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`
`64
`
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`POSITIVE VOLTAGE
`
`60
`
`REGISTER
`TRIMMING
`
`VOLTAGE GENERATION
`
`CONTROL REGISTER
`
`70
`
`65
`
`61
`
`VOLT AGE ___,____.___..____,_
`
`REFERENCE
`
`18
`
`63
`
`64
`
`BOOSTING SECTION
`NEGATIVE VOLTAGE
`
`600
`
`FIG. 14
`
`15
`
`

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`
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`
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`
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`
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`
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`
`SYSTEM
`
`4
`
`i------2
`15
`
`RAM
`
`REFERENCE
`
`PULSE
`
`EVALUATION
`
`DEVICE
`
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`
`CIRCUIT) TCNT
`
`(WRITE DATA LATCH) DLA
`
`I
`
`I
`
`COMPARISON
`PULSE WIDTH I •
`
`CIRCUIT
`
`REGISTER
`DECISION
`
`TRIMMING REGISTER
`
`DIVISION RATIO
`
`78
`
`COMPARE PULSE
`
`29
`
`21
`
`WRITE CONTROL
`
`CLOCK
`
`77
`
`<Pim
`
`<Pin
`
`80
`
`START
`
`81
`
`FREQUENCY
`
`SECTION
`DIVIDING
`
`5
`
`18
`
`1
`
`10
`
`FIG. 15
`
`16
`
`

`
`U.S. Patent
`
`Feb.14,2006
`
`Sheet 16 of 29
`
`US 7,000,160 B2
`
`FIG. 16
`
`OSCILLATION
`FREQUENCY (f)
`
`SMALL
`
`LARGE
`
`Lg
`
`17
`
`

`
`U.S. Patent
`U.S. Patent
`
`Feb. 14, 2006
`Feb.14,2006
`
`92f071teehS
`Sheet 17 of 29
`
`US 7,000,160 B2
`US 7,000,160 B2
`
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`
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`
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`
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`
`78
`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
`19
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`
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`
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`
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`
`FIG. 19
`
`512
`
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`
`START EXECUTION OF
`
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`TRANSFER TRIMMING
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`
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`
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`
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`
`RATIO
`
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`
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`
`RING OSCILLATOR
`
`FREQUENCY
`
`FIG. 20
`
`21
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`
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`
`FIG. 21A
`
`22
`
`

`
`U.S. Patent
`
`Feb.14,2006
`
`Sheet 22 of 29
`
`US 7,000,160 B2
`US 7,000,160 B2
`
`It\
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
`5
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`
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`
`1F
`
`FIG. 24
`
`25
`
`

`
`U.S. Patent
`
`Feb.14,2006
`
`Sheet 25 of 29
`
`US 7,000,160 B2
`
`FIG. 25
`
`1-------------------------------------------------------------1
`I '
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`
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`I
`
`64
`
`BOOSTING SECTION
`
`60---t
`
`FIG. 26
`
`5A
`
`27
`
`

`
`U.S. Patent
`
`Feb.14,2006
`
`Sheet 27 of 29
`
`US 7,000,160 B2
`
`FIG. 27
`
`START
`
`INPUT VOLTAGE OF
`EXPECTED VALUE
`(EVALUATION DEVICE)
`
`521
`
`SET VOLTAGE
`GENERATION CONTROL
`REGISTER
`
`DESIGNATE MINIMUM
`VOLTAGE IN TRIMMING
`REGISTER
`
`S22
`t.----CONTROL BY
`DEDICATED
`SEQUENCER
`
`$23
`
`DECISION BY
`INTERNAL DECISION
`CIRCUIT
`
`WAIT FOR
`STABILIZATION OF VOLTAGE
`.--------··-··-··-··-··-··-·· ··-··-··-··-··-·
`
`$24
`
`DECISION
`REGISTER=O
`
`DECISION
`REGISTER=1
`
`S25
`
`=1
`
`826
`
`END
`
`UPDATE VALUE IN
`TRIMMING REGISTER
`
`28
`
`

`
`N
`~
`Q
`O'I
`Q ;...
`Q
`Q
`""-l
`rJ'J.
`
`e
`
`\C
`N
`0 .....,
`QrO
`N
`~ .....
`'Jl =(cid:173)~
`
`N c c
`'"""'
`~,J;;..
`?'
`~
`"'!"j
`
`O'I
`
`~ = ......
`~ ......
`~
`•
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`d •
`
`18
`
`I
`
`I
`
`I
`
`5·1
`
`~
`!
`r-------------,------------------------------i
`
`I FLASH FUSE CIRCUIT ~52
`
`L--------------------------------------------~
`1
`I
`I
`I
`
`Pad1
`
`Vss
`
`70
`
`EVALUATION
`
`(TESTER)
`DEVICE
`
`71
`
`66
`
`REGISTER
`TRIMMING
`
`CONTROL REGISTER
`VOLTAGE GENERATION
`
`DECODER
`
`65
`
`61
`
`REFERENCE
`
`VOLTAGE
`
`______ ,
`
`I
`
`62
`
`----, 1
`
`~
`
`r _________________ l
`63
`
`I
`I
`I
`
`64
`
`BOOSTING SECTION
`
`60-----!
`
`FIG. 28
`
`58
`
`29
`
`

`
`U.S. Patent
`
`Feb.14,2006
`
`Sheet 29 of 29
`
`US 7,000,160 B2
`
`FIG. 29
`
`i.------ CONTROL BY
`EVALUATION DEVICE
`
`START
`
`INPUT VOLTAGE OF
`EXPECTED VALUE
`(EVALUATION DEVICE)
`
`SET VOLTAGE
`GENERATION CONTROL
`REGISTER
`(EVALUATION DEVICE)
`
`DESIGNATE MINIMUM
`VOLTAGE IN TRIMMING
`REGISTER
`(EVALUATION DEVICE)
`
`WAIT FOR STABILIZATION
`OF VOLTAGE
`(EVALUATION DEVICE)
`
`.---------<..i-··-··-··-··-··-··-··
`
`DECISION BY INTERNAL
`DECISION CIRCUIT
`
`DECISION
`REGISTER=O
`
`DECISION
`REGISTER=1
`
`=1
`
`END
`
`UPDATE VALUE IN
`TRIMMING REGISTER
`(EVALUATION DEVICE)
`
`30
`
`

`
`1
`SEMICONDUCTOR INTEGRATED CIRCUIT
`AND A METHOD OF TESTING THE SAME
`
`US 7,000,160 B2
`
`2
`between the voltage obtained by trimming and the target
`voltage value is simply stated but no notice is taken of the
`difference between the two cases. In contrast, the inventors
`of the present invention took note of the following points.
`5 That is, trimming on a plurality of LSis with one evaluation
`device is effective in reducing the time required for testing
`including a measuring operation for voltage trimming or the
`like, but this voltage trimming cannot be performed in a
`parallel manner because the external evaluation device mea-
`10 sures the voltage. Only a limited effect may be obtained by
`performing voltage measurement and trimming register
`value adjustment while successively changing the objects by
`switching with a relay. The same can be said with respect to
`trimming for adjustment of the write pulse width and the
`15 erase pulse width determined by dividing a clock frequency
`generated from an internal oscillator, or the current through
`a MOS transistor determined by LSI manufacturing condi(cid:173)
`tions. Thus, any process in which LSis undergoes trimming
`one after another requires a considerably long test time.
`The technique disclosed in JP-A-5-265579 has no means
`for changing the trimmed value since it uses a counter in
`hardware form and a fuse. In the case of an application to
`trimming for adjustment of a boosted voltage, however, a
`need arises to correct the trimmed value after adjustment of
`25 the voltage value, for example, if a write time target value
`is not reached.
`An object of the present invention is to provide a semi(cid:173)
`conductor integrated circuit capable of setting control infor(cid:173)
`mation for determining a voltage or a pulse width in a
`30 self-completion manner and also capable of easily correcting
`the control information.
`Another object of the present invention is to provide a
`semiconductor integrated circuit testing method in which
`control information for determining a voltage or a pulse
`width can be set with facility in overlapping manner and can
`easily be corrected.
`[1] The present invention will be outlined below with
`respect to its typical aspects.
`For example, to test a plurality of semiconductor inte(cid:173)
`grated circuits each including a CPU and a flash memory, a
`voltage is supplied as an expected voltage to the semicon(cid:173)
`ductor integrated circuits in a parallel manner from an
`evaluation device outside the semiconductor integrated cir(cid:173)
`cuits. Accordingly, each semiconductor integrated circuit
`incorporates a decision circuit which compares the expected
`voltage value and a boosted (step-down) voltage generated
`in the integrated circuit. The semiconductor integrated cir(cid:173)
`cuit also has a register for storing the result of comparison
`made by the decision circuit, and has a system capable of
`making a decision about the comparison result by means of
`a control circuit such as an internal CPU. For example, a
`data register (trimming register) for changing a boosted
`(step-down) voltage value is incorporated and an internal
`CPU enables to rewrite the value in the trimming register.
`The internal CPU controls the comparator and the register to
`perform trimming in a self-completion manner. A self(cid:173)
`trimming program transferred to memories (e.g., RAMs) in
`a plurality of memory LSis arranged as described above can
`be executed in a parallel manner. In this program, a value is
`set in the trimming register, determination of the result of
`comparison made by the voltage decision circuit is awaited,
`and a decision is made about the value in the trimming
`register representing the comparison result. According to the
`65 decision result, the value in the trimming register is updated.
`These steps are repeated until the voltage generated in the
`circuit becomes equal to the expected voltage value input
`
`BACKGROUND OF THE INVENTION
`The present invention relates to a trimming technique for
`finely adjusting a voltage, the width of a pulse, etc., pro(cid:173)
`duced in a semiconductor integrated circuit (large-scale
`integrated circuit (LSI)) in accordance with characteristics
`of LSI, and relates to a semiconductor integrated circuit such
`as a microcomputer incorporating a flash memory and to a
`testing method of performing trimming on such a semicon(cid:173)
`ductor integrated circuit.
`There are some nonvolatile memories such as flash
`memories generating a particular programming voltage in
`LSis. This voltage varies because of manufacturing varia(cid:173)
`tion and there is a need to perform trimming or fine
`adjustment for correcting the programming voltage in each
`LSI. The memory programming time characteristic also
`varies. Therefore, the programming voltage is changed
`according to the memory characteristics to constantly main- 20
`tain memory programming characteristics.
`In fine adjustment (hereinafter referred to as "voltage
`trimming") of a programming voltage (e.g., an internal
`boosted voltage) generated in such a nonvolatile memory,
`the voltage generated in the LSI is measured with an external
`evaluation device (tester or the like). Therefore, parallel
`trimming cannot be performed on a plurality of such
`memory LSis. For example, it is difficult to use a parallel
`testing method in which a program for testing flash memo(cid:173)
`ries incorporated in microcomputers is transferred to internal
`random access memories (RAMs) and parallel executions of
`the program are carried out by the internal central processing
`units (CPUs) provided in each of the microprocessors. For
`this reason, a sequential method in which trimming is
`performed on one LSI at a time to adjust an internal boosted 35
`voltage or the like has been practiced, requiring an increased
`test time. A tester having the function of performing parallel
`measurement on a plurality of LSis is considerably high(cid:173)
`priced and it is not practical to use such a high-priced tester
`only for voltage trimming or the like.
`Some flash memories or microcomputers incorporating
`flash memories require use of a trimming technique with
`respect to the width of write pulses for setting the write
`voltage application time to a specified value or with respect
`to the current through a MOST transistor as well as use of 45
`a trimming technique for voltage trimming. Use of a trim(cid:173)
`ming technique in such a case also entails the same consid(cid:173)
`eration as that described above since there is also a need to
`separately measure the object of measurement.
`JP-A-5-265579 describes an example of prior art contain- 50
`ing a description of voltage trimming. This document relates
`to a method of performing trimming for adjustment of a
`reference voltage in such a manner that a series from which
`a trimmed value is obtained is generated while a counter is
`being incremented, and the trimmed value is written to a 55
`programmable read only memory (PROM) circuit when a
`reference voltage output coincides with a target value. The
`counter and a circuit for incrementing the counter are
`provided in the form of hardware and the PROM circuit has
`a fuse configuration. According to this document, an on-chip 60
`comparator or a comparator on a tester may be used as a
`comparator for comparison between the voltage obtained by
`trimming and the target voltage value.
`
`40
`
`SUMMARY OF THE INVENTION
`In JP-A-5-265579, use of an on-chip comparator or a
`comparator on a tester as a comparator for comparison
`
`31
`
`

`
`US 7,000,160 B2
`
`3
`from the evaluation device outside the LSis, or until the
`desired condition is attained. The value in the trimming
`register when the expected value is reached is stored as a
`trimmed value. This storage may be realized by writing the
`information in a trimming area of the flash memory, for
`example.
`Similarly, with respect to the current through a MOS
`transistor in a plurality of LSis, current trimming may be
`performed by externally applying a reference current simul(cid:173)
`taneously to the plurality of LSis and by comparing the
`reference current and the current through the internal MOS
`transistor in each LSI. To externally supply a constant
`current to the plurality of LSis in a parallel manner, a
`method may be used in which a constant resistor is con(cid:173)
`nected to an input terminal of each LSI and a constant
`voltage is applied to the resistor to produce the constant
`current.
`Also, with respect to a control clock for producing a write
`pulse width and an erase pulse width, trimming for adjust(cid:173)
`ment of the frequency of the control clock may be performed
`by comparing a reference time and a time generated in an
`internal oscillator. The reference time may be internally
`produced on the basis of a clock of a particular frequency
`externally supplied at the time of testing or may be directly
`supplied externally as a reference pulse.
`As described above, a trimmed value which coincides
`with a voltage or a current of an expected value can be
`obtained by only supplying the expected voltage or current
`value externally and executing a trimming program by
`means of an internal CPU. The same effect is also ensured 30
`with respect to trimming for adjustment of the frequency of
`a control clock for generating write and erase pulses. A
`voltage, a current or a pulse of an expected value externally
`provided can be supplied in common to a plurality of LSis.
`Since a trimming program is executed by means of an 35
`internal CPU, it can be executed in the plurality of LSis in
`a parallel manner. Thus, parallel trimming can be performed
`on a plurality of LSis with facility and the total test time can
`be reduced. Also, there is no need to provide a switching
`device such as a relay in the evaluation device.
`[2] The present invention will be described in more detail
`with respect to its several aspects. According to a first aspect
`of the present invention, a semiconductor integrated circuit
`such as a data processor including a CPU and a flash
`memory or the like as on-chip components may be provided.
`<<Data Processor>>
`The semiconductor integrated circuit includes, on one
`semiconductor substrate, voltage generation means capable
`of generating a voltage on the basis of control data loaded
`into a data register, nonvolatile storage means in which the
`control data is held, and a processing circuit used to prepare
`the control data held in the nonvolatile storage means. The
`processing circuit includes a decision circuit which deter(cid:173)
`mines the relationship between a reference voltage supplied
`from the outside of the semiconductor substrate and the
`voltage generated by the voltage generation means, and a
`control circuit which determines the control data on the data
`register with reference to an output from the decision circuit,
`and which stores the determined control data in the non-
`volatile storage means by reading out the data from the data 60
`register. The operation of the control circuit is determined by
`a program.
`The decision circuit which determines the relationship
`between a reference voltage supplied from the outside of the
`semiconductor substrate and the voltage generated by the 65
`voltage generation means may have a configuration for
`directly comparing the reference voltage and the voltage
`
`4
`generated by the voltage generation means, or configuration
`for comparing the reference voltage and a voltage on a path
`where the current is controlled according to the voltage
`generated by the voltage generation means. The former
`5 configuration is most suitabl