Trials@uspto.gov
`571.272.7822
`
`
` Paper No. 9
`
`Filed: June 13, 2017
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`and MICRON TECHNOLOGY, INC.
`Petitioner,
`
`v.
`
`DANIEL L. FLAMM,
`Patent Owner.
`
`____________
`
`Case IPR2017-00282
`Patent RE40,264 E
`____________
`
`
`
`Before CHRISTOPHER L. CRUMBLEY, JO-ANNE M. KOKOSKI, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
`
`
`
`
`
`
`571.272.7822
`
`
` Paper No. 9
`
`Filed: June 13, 2017
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`and MICRON TECHNOLOGY, INC.
`Petitioner,
`
`v.
`
`DANIEL L. FLAMM,
`Patent Owner.
`
`____________
`
`Case IPR2017-00282
`Patent RE40,264 E
`____________
`
`
`
`Before CHRISTOPHER L. CRUMBLEY, JO-ANNE M. KOKOSKI, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
`
`
`
`
`
`
`
`IPR2017-00282
`Patent RE40,264 E
`
`
`I. INTRODUCTION
`
`Intel Corporation, GLOBALFOUNDRIES U.S., Inc., and Micron
`
`Technology, Inc. (collectively, “Petitioner”), filed a Petition requesting an
`
`inter partes review of claims 56–63, 70, and 71 (“the challenged claims”) of
`
`U.S. Patent No. RE40,264 E (Ex. 1001, “the ’264 patent”). Paper 2 (“Pet.”).
`
`Daniel L. Flamm (“Patent Owner”), filed a Preliminary Response. Paper 8
`
`(“Prelim. Resp.”).
`
`Under 35 U.S.C. § 314(a), an inter partes review may not be instituted
`
`unless the information presented in the Petition shows “there is a reasonable
`
`likelihood that the petitioner would prevail with respect to at least 1 of the
`
`claims challenged in the petition.” Taking into account the arguments
`
`presented in Patent Owner’s Preliminary Response, we conclude that the
`
`information presented in the Petition establishes that there is a reasonable
`
`likelihood that Petitioner would prevail in challenging claims 56–63, 70, and
`
`71 as unpatentable under 35 U.S.C. § 103(a). Pursuant to § 314, we hereby
`
`institute an inter partes review as to these claims of the ’264 patent
`
`A. Related Matters
`
`Petitioner reports that Patent Owner has asserted the ’264 patent
`
`against Petitioner and other defendants in five proceedings in the Northern
`
`District of California: Case Nos. 5:16-cv-01578-BLF, 5:16-cv-1579-BLF,
`
`5:16-cv-1580-BLF, 5:16-cv-1581-BLF, and 5:16-cv-02252-BLF. Pet. 2.
`
`The parties also state that Lam Research Corporation filed a declaratory
`
`judgment action against Patent Owner on the ’264 patent (N.D. Cal. Case
`
`No. 5:15-cv-01277-BLF) and filed seven IPR petitions on the ’264 patent:
`
`IPR2015-01759; IPR2015-01764; IPR2015-01766; IPR2015-01768;
`
`IPR2016-00468; IPR2016-00469; and IPR2016-00470. Pet. 2; Prelim.
`
`2
`
`
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`IPR2017-00282
`Patent RE40,264 E
`
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`Resp. 1. The parties also represent that Samsung Electronics, Co., Ltd. filed
`
`two IPR petitions on the ’264 patent: IPR2016-01510; IPR2016-01512. Id.
`
`In addition, we note that Petitioner also filed three other petitions
`
`challenging the patentability of certain claims of the ’264 patent: IPR2017–
`
`0279; IPR2017–00280; and IPR2017–00281.
`
`B. The ’264 Patent
`
`The ’264 patent, titled “Multi-Temperature Processing,” reissued
`
`April 29, 2008 from U.S. Patent Application No. 10/439,245 (“the ’245
`
`application”), filed on May 14, 2003. Ex. 1001, at [54], [45], [21], [22].
`
`The ’264 patent is a reissue of U.S. Patent No. 6,231,776 B1 (“the ’776
`
`patent”), which issued on May 15, 2001, from U.S. Patent Application No.
`
`09/151,163 (“the ’163 application”) filed September 10, 1998. Id. at [64].
`
`The ’264 patent is directed to a method “for etching a substrate in the
`
`manufacture of a device,” where the method “provide[s] different processing
`
`temperatures during an etching process or the like.” Id. at Abstract. The
`
`apparatus used in the method is shown in Figure 1, reproduced below.
`
`
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`3
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`IPR2017-00282
`Patent RE40,264 E
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`Figure 1 depicts a substrate (product 28, such as a wafer to be etched) on a
`
`substrate holder (product support chuck or pedestal 18) in a chamber
`
`(chamber 12 of plasma etch apparatus 10). Id. at 3:24–25, 3:32–33, 3:40–
`
`41.
`
`Figures 6 and 7, reproduced below, depict a temperature-controlled
`
`substrate holder and temperature control systems.
`
`
`
`Figures 6 and 7 depict temperature-controlled fluid flowing through
`
`substrate holder (600, 701), guided by baffles 605, where “[t]he fluid [is]
`
`used to heat or cool the upper surface of the substrate holder.” Ex. 1001,
`
`14:28–63, 16:5–67. Figure 6 also depicts heating elements 607 underneath
`
`the substrate holder, where “[t]he heating elements can selectively heat one
`
`or more zones in a desirable manner.” Id. at 15:10–26. Referring to Figure
`
`7, the operation of the temperature control system is described as follows:
`
`4
`
`
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`IPR2017-00282
`Patent RE40,264 E
`
`
`The desired fluid temperature is determined by comparing the
`desired wafer or wafer chuck set point temperature to a measured
`wafer or wafer chuck temperature . . . . The heat exchanger, fluid
`flow rate, coolant-side fluid temperature, heater power, chuck,
`etc. should be designed using conventional means to permit the
`heater to bring the fluid to a setpoint temperature and bring the
`temperature of
`the chuck and wafer
`to predetermined
`temperatures within specified time intervals and within specified
`uniformity limits.
`
`Id. at 16:36–39, 16:50–67.
`
`An example of a semiconductor substrate to be patterned is shown in
`
`Figure 9, reproduced below.
`
`Figure 9 depicts substrate 901 having a stack of layers including oxide layer
`
`903, polysilicon layer 905, tungsten silicide layer 907, and photoresist
`
`masking layer 909 with opening 911, from the treatment method shown in
`
`Figure 10, reproduced below. Id. at 17:58–18:57.
`
`
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`5
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`IPR2017-00282
`Patent RE40,264 E
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`
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`Figure 10 depicts the tungsten silicide layer being etched between
`
`points B and D at a constant temperature; the polysilicon layer being
`
`exposed between Points D and E; the polysilicon layer being etched at a
`
`constant temperature beyond point E; and the resist being ashed beyond
`
`Point I. Ex. 1001, 18:58–19:64. The plasma’s optical emission at 530
`
`nanometers is monitored to determine when there is breakthrough to the
`
`polysilicon layer (Point D) and a lower etch temperature is required to etch
`
`the polysilicon layer (Point E). Id. at 19:8–24, 19:45–52.
`
`6
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`IPR2017-00282
`Patent RE40,264 E
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`C. Illustrative Claims
`
`
`
`Of the challenged claims, claims 56 and 60 are the only independent
`
`claims at issue. Claim 56 is directed to a method of processing layers which
`
`are included in a stack of layers positioned on a substrate, and claim 60 is
`
`directed to a method for manufacturing a device comprising an integrated
`
`circuit. Claim 56 and 60, with bracketed material added,1 are reproduced
`
`below:
`
`56. A method for processing layers which are included in a
`stack of layers positioned on a substrate, the method
`comprising:
`
`[a] placing the substrate on a substrate holder;
`
`[b] sensing a substrate holder temperature;
`
`[c] etching at least a portion of a first silicon-containing layer
`in a chamber while the substrate is maintained at a
`selected first substrate temperature; and
`
`[d] etching at least a portion of a second silicon-containing
`layer in the chamber while the substrate is maintained at
`a selected second substrate temperature;
`
`[e] wherein the substrate holder is heated to a temperature
`operable to maintain at least one of the selected first and
`the selected second substrate temperatures above 49° C.,
`and the substrate temperature is changed from the first
`substrate
`temperature
`to
`the
`second
`substrate
`temperature with a control circuit operable to effectuate
`the changing within a preselected time period that is less
`than the overall process time associated with the etching
`the first silicon-containing layer and the second silicon-
`containing layer.
`
`
`
`1 Although the bracketed material is not present in the text of claims 56 or
`60, for clarity and consistency, this Decision will use the bracketed
`nomenclature as utilized by both Petitioner and Patent Owner.
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`7
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`IPR2017-00282
`Patent RE40,264 E
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`60. A method for manufacturing a device comprising an
`integrated circuit, the method comprising:
`
`[a] transferring a substrate comprising a stack of layers
`including a silicide layer into a chamber, the chamber
`comprising a substrate holder;
`
`[b] sensing the substrate holder temperature;
`
`[c] heating the substrate holder with a substrate holder control
`circuit and a heating device to maintain the substrate
`holder at a temperature that is operable to effectuate a
`substrate temperature above room temperature while
`processing the substrate;
`
`[d] processing the substrate on the substrate holder at a first
`substrate temperature; and
`
`[e] processing the substrate on the substrate holder at a
`second substrate temperature to etch at least a portion of
`the silicide layer;
`
`[f] wherein the first substrate temperature is different from
`the second substrate temperature and the first substrate
`temperature is changed to the second substrate temperature
`with a substrate temperature control circuit within a
`preselected time to etch the silicide layer.
`
`D. Prior Art Relied Upon
`
`Petitioner relies upon the following prior art references:
`
`Inventor2
`
`Patent
`
`Relevant Dates
`
`Kadomura
`
`Matsumura
`
`Kikuchi
`
`U.S. Patent No.
`6,063,710
`U.S. Patent No.
`5,151,871
`U.S. Patent No.
`5,226,056
`
`issued May 16, 2000,
`filed Feb. 21, 1997
`issued Sept. 29, 1992,
`filed June 15, 1990
`issued July 6, 1993,
`filed Jan. 9, 1990
`
`Exhibit
`No.
`1005
`
`1003
`
`1004
`
`
`
`2 For clarity and ease of reference, we only list the first named inventor.
`
`8
`
`
`
`IPR2017-00282
`Patent RE40,264 E
`
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`Muller
`
`Wang
`
`
`Pet. 4–5.
`
`U.S. Patent No.
`5,605,600
`U.S. Patent No.
`4,992,391
`
`issued Feb. 25, 1997,
`filed Mar. 13, 1995
`Issued Feb. 12, 1991,
`filed Nov. 29, 1989
`
`1002
`
`1010
`
`E. Asserted Grounds of Unpatentability
`
`
`
`Petitioner challenges claims 56–63, 70, and 71 of the ’264 patent
`
`based on the asserted grounds of unpatentability (“grounds”) set forth in the
`
`table below. Id.
`
`References
`
`Basis
`
`Challenged Claim(s)
`
`Kadomura & Matsumura
`
`§ 103(a) 56, 58
`
`Kadomura, Matsumura, & Muller
`
`§ 103(a) 57
`
`Kadomura, Matsumura, & Wang
`
`§ 103(a) 59–61, 71
`
`Kadomura, Matsumura, Muller, &
`Wang
`Kadomura, Matsumura, Kikuchi, &
`Wang
`Muller, Matsumura, & Wang3
`
`Muller, Matsumura, Wang, &
`Kikuchi
`
`§ 103(a) 62
`
`§ 103(a) 63, 70
`
`§ 103(a) 56–62, 71
`
`§ 103(a) 63, 70
`
`
`
`3 Petitioner states claims 56–62 and 71 are being challenged over the
`combination of Muller, Matsumura, and Wang. However, Petitioner does
`not address Wang in its arguments directed to claims 56–58. We address the
`challenges as they are set forth in the Petition.
`
`9
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`IPR2017-00282
`Patent RE40,264 E
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`II. ANALYSIS
`
`A. Claim Construction
`
`The’264 patent has expired.4 For claims of an expired patent, the
`
`Board’s claim interpretation is similar to that of a district court. See In re
`
`Rambus, Inc., 694 F.3d 42, 46 (Fed. Cir. 2012). Claim terms are given their
`
`ordinary and customary meaning as would be understood by a person of
`
`ordinary skill in the art at the time of the invention, and in the context of the
`
`entire patent disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257
`
`(Fed. Cir. 2007). Only those terms in controversy need to be construed, and
`
`only to the extent necessary to resolve the controversy. See Vivid Techs.,
`
`Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`
`For purposes of this Decision, based on the record before us, we
`
`determine that none of the claim terms requires an explicit construction.
`
`B. Priority Date for the Challenged Claims of the ’264 Patent
`
`
`
`As explained previously, the ’264 patent reissued from the ’245
`
`application, filed on May 14, 2003. Ex. 1001, at [21], [22]. The ’245
`
`
`
`4 The ’264 patent expired no later than December 4, 2015, which is twenty
`years after December 4, 1995, the earliest filing date of an application to
`which the ’264 claims priority. See Ex. 1001 [63]; 35 U.S.C. § 154(a)(2)
`(2012 & Supp. III 2015) (stating patent term ends twenty (20) years from the
`date on which the application for the patent was filed in the United States,
`“or, if the application contains a specific reference to an earlier filed
`application or applications under section 120, 121, 365(c), or 386(c), from
`the date on which the earliest such application was filed”).
`
`
`10
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`IPR2017-00282
`Patent RE40,264 E
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`application is a reissue of the ’776 patent, which issued May 15, 2001 from
`
`the ’163 application, which was filed September 10, 1998. Id. at [64].
`
`The ’163 application is a continuation-in-part of the following two
`
`applications: (1) U.S. Provisional Application No. 60/058,650 (“the ’650
`
`provisional application”), filed on September 11, 1997; and (2) U.S. Patent
`
`Application No. 08/567,224 (“the ’224 application”), filed on December 4,
`
`1995. Id. at [60], [63], 1:11–15.
`
`
`
`Petitioner contends that September 11, 1997 is the earliest possible
`
`priority date for the challenged claims, arguing that the ’224 application,
`
`filed on December 4, 1995, does not disclose the claimed subject matter.
`
`Pet. 9–11. Relying upon the testimony of its declarant, Dr. John Bravman
`
`(Ex. 1006, “the Bravman Declaration”), Petitioner contends the ’224
`
`application fails to disclose changing the temperature of a substrate on a
`
`substrate holder from “the selected first substrate temperature to the selected
`
`second substrate temperature within a preselected time interval” or a
`
`“substrate temperature control system” that includes a substrate temperature
`
`sensor. Id. at 10 (citing Ex. 1006 ¶¶ 30–31). Consequently, Petitioner
`
`asserts that, because the ’224 application does not provide sufficient written
`
`description support for certain limitations required by independent claims 56
`
`and 60, the challenged claims only are entitled to the priority date of the
`
`’650 provisional application (i.e., September 11, 1997). See id. at 10–11.
`
`Patent Owner does not argue that the ’264 patent is entitled to claim a
`
`priority date earlier than September 11, 1997.
`
`
`
`On this record, we are persuaded by Petitioner’s argument that the
`
`’224 application does not provide sufficient written description support for
`
`the full scope of independent claims 56 and 60, and therefore the challenged
`
`11
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`IPR2017-00282
`Patent RE40,264 E
`
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`claims of the ’264 patent are not entitled to claim priority to the December 4,
`
`1995 filing date of the ’224 application.
`
`As such, based on the this record, we agree with Petitioner that
`
`Kadomura, which was filed on February 21, 1997, and the remaining
`
`asserted references, each of which were filed before the December 4, 1995
`
`filing date of the ’224 application, qualify as prior art to the challenged
`
`claims of the ’264 patent.
`
`C. Level of Ordinary Skill in the Art
`
`Petitioner contends a person of ordinary skill in the art at the time of
`
`the alleged invention of the ’264 patent (“skilled person”) would have had
`
`(i) a Bachelor’s degree in chemical engineering, materials science
`
`engineering, electrical engineering, physics, chemistry, or a similar field,
`
`and three or four years of work experience in semiconductor manufacturing
`
`or related fields; (ii) a Master’s degree in chemical engineering, materials
`
`science engineering, electrical engineering, physics, chemistry, or a similar
`
`field, and two or three years of work experience in semiconductor
`
`manufacturing or related fields; or (iii) a Ph.D. in chemical engineering,
`
`materials science engineering, electrical engineering, physics, chemistry, or
`
`a similar field. Pet. 24–25 (citing Ex. 1006 ¶ 21.)
`
`Patent Owner does not dispute Petitioner’s proposed definition of a
`
`person of ordinary skill in the art. For the purposes of this Decision, we
`
`adopt Petitioner’s articulated level of skill in the art.
`
`D. Asserted Obviousness of Claims 56 and 58
`over Kadomura and Matsumura
`
`
`
`Petitioner contends that claims 56 and 58 are unpatentable under
`
`§ 103(a) over the combination of Kadomura and Matsumura. Pet. 25–43.
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`12
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`IPR2017-00282
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`Petitioner explains how this proffered combination purportedly teaches the
`
`subject matter of each challenged claim, and asserts that a person of ordinary
`
`skill in the art would have had reason to combine or modify Kadomura with
`
`the teachings from Matsumura. Id. Petitioner also relies upon the Bravman
`
`Declaration (Ex. 1006) to support its positions.
`
`1. Overview of Kadomura
`
`Kadomura generally relates to a dry etching method used primarily for
`
`the production of semiconductor devices and, in particular, to a dry etching
`
`method and apparatus that provides compatibility for anisotropic fabrication
`
`and high selectivity. Ex. 1005, 1:6–10. According to Kadomura, one
`
`objective of the disclosed dry etching method is to apply an etching
`
`treatment that includes a plurality of steps to a specimen within the same
`
`processing apparatus, wherein the temperature of the specimen is changed
`
`between etching in a first step and etching in a second step. Id. at 2:65–3:5.
`
`Because the disclosed dry etching method conducts each of the etching
`
`treatments in the same processing apparatus, the time for changing the
`
`specimen temperature between the steps may be shortened. Id. at 4:46–49.
`
`Moreover, by conducting the change of specimen temperature within a short
`
`period of time, dry etching treatment may be applied without deteriorating
`
`the throughput. Id. at 4:49–54. Kadomura discloses several examples of
`
`multi-temperature etch processes, including etching silicide and polysilicon
`
`at room temperature (20°C) in a first step, followed by etching polysilicon at
`
`-30°C in a second step. Id. at 6:18–7:7. After completing those two steps, a
`
`heater within substrate holder stage 12 brought the holder back up to 20ºC
`
`before the tool repeated the same two temperature etch process. Id. at 6:63–
`
`7:7, 7:31–47. Kadomura also discloses etching polysilicon at higher
`
`13
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`IPR2017-00282
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`temperatures because “radical reaction is promoted by increasing the
`
`specimen temperature (50°C).” Id. at 10:28–35.
`
`In the third embodiment discussed in relation to Figures 3A– 3C,
`
`Kadomura discloses a method of fabricating polysilicon on a SiO2 layer
`
`having a high step. Id. at 9:36–10:27. The main etching in the first step is
`
`applied at a low temperature (i.e., -30ºC), whereas the overetching in the
`
`second step is applied at a much higher temperature (i.e., 50ºC) within a
`
`short period of time of about fifty (50) seconds. Id. at 9:54– 62, 10:11–27.
`
`According to Kadomura, the change in temperature of specimen W is
`
`controlled by “the cooling means and the heater disposed to the stage 12.”
`
`Id. at 10:7–10. The functioning of the cooling means is controlled by
`
`thermometer 18, which is “connected for measuring the temperature of the
`
`specimen W.” Id. at 11:48–51, 12:36–47.
`
`2. Overview of Matsumura
`
`Matsumura generally relates to heat-processing a semiconductor
`
`wafer and, in particular, to controlling temperatures of the semiconductor
`
`wafer when it is heated or cooled. Ex. 1003, 1:8–13. According to
`
`Matsumura, one objective of the disclosed invention is to provide a “method
`
`of heat-processing semiconductor devices whereby temperatures of the
`
`semiconductor devices can be controlled at devices-heating and -cooling
`
`times so as to accurately control their thermal history curve.” Id. at 2:60–65.
`
`Matsumura discloses applying the method to plasma etching when it states
`
`that, although “the present invention has been applied to the adhesion and
`
`baking processes for semiconductor wafers in the above-described
`
`embodiments . . . , it can also be applied to any of the ion implantation,
`
`14
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`IPR2017-00282
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`[chemical vapor deposition (“CVD”)], etching and ashing processes.” Id. at
`
`10:3–7. Figure 5A, reproduced below, is a schematic diagram of an
`
`embodiment for heat-processing a substrate (wafer W) on a substrate holder
`
`(wafer-stage 12, which includes upper plate 13 and conductive thin film 14)
`
`in chamber 11.
`
`
`
`Figure 5A depicts adhesion unit 42 along with control system 20 that
`
`measures the temperature of thin film 14 deposited on the underside of upper
`
`plate 13 by using thermal sensor 25. Id. at 5:13–17, 5:32–47, 5:67–6:4,
`
`6:45–50. Control system 20 sends signals (SM) to power supply circuit 19
`
`to heat semiconductor wafer W on upper plate 13 by conductive thin film
`
`14, and sends signals (SC) to cooling system 23 to control the amount of
`
`coolant supplied to jacket 22. Id. at 5:52–6:32, Figs. 5A, 5B. Inside the
`
`control system is a “recipe,” such as that shown in Figure 9, reproduced
`
`below.
`
`15
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`Figure 9 depicts a recipe with a “thermal history curve” showing
`
`temperature as a function of time. Id. at 4:42–43. At a given time (or
`
`pulse), the control system measures the substrate holder temperature with
`
`thermal sensor 25, compares this measurement to that of the recipe shown in
`
`Figure 9, and either (1) sends a signal (SM) to power supply circuit 19 to
`
`heat the substrate (wafer W) (e.g., heating wafer W from 20ºC to 90ºC
`
`within 60 seconds); (2) sends a signal (SC) to cooling system 23 to cool the
`
`substrate by allowing jacket 22 arranged under stage 12 to exchange heat
`
`with thin film 14 (e.g., cooling wafer W from 140ºC to 20ºC within 60
`
`seconds); or (3) sends no signal and waits for the next measurement time
`
`(e.g., holding the temperature of wafer W at 140ºC for 30 seconds). Id. at
`
`5:52–6:32, Figs. 5A, 5B.
`
`3. Analysis
`
`Petitioner contends that the combination of Kadomura and Matsumura
`
`teaches all of the elements of independent claim 56 and provides arguments
`
`setting forth were each of the limitations may be found. Pet. 25–43. For
`
`16
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`IPR2017-00282
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`example, Petitioner contends that Kadomura teaches etching a silicide layer
`
`and a polysilicon layer in a layer stack that includes an oxide layer and a
`
`photoresist layer. Id. at 25–26 (citing Ex. 1005, Figs. 1A, 1C, 3A, 6:5–12,
`
`9:36–45). Petitioner contends Kadomura’s control device 25 measures
`
`wafer temperature with thermometer 18 and adjusts the temperature to
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`match a desired temperature during the etching process. Id. at 28 (citing Fig.
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`4, 12:38–48). Petitioner asserts that Kadomura changes the temperature of
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`substrate holder (stage 12) to set wafer temperature and that it would have
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`been obvious to measure the substrate holder temperature to confirm that the
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`desired temperature was achieved. Id. at 28–29 (citing Ex. 1005, 3:23–49;
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`Ex. 1006 ¶ 77). Petitioner also contends that to the extent Kadomura does
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`not expressly teach a substrate holder temperature sensor, Matsumura
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`teaches this feature as Matsumura teaches a multi-temperature processing
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`tool with a temperature sensor embedded within substrate holder (stage 12).
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`Id. at 29 (citing Ex. 1003, Fig. 5A, 5:32–33, 7:20–22). Relying on the
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`testimony of Dr. Bravman, Petitioner contends that it would have been
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`obvious to use the temperature sensor of Matsumura to measure and set the
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`temperature of Kadomura’s substrate holder in order to directly gauge how
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`well heat was transferred between the holder and the wafer (and vice versa)
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`in order to adjust recipes and improve processing efficiencies and increase
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`throughput. Id. at 31–32 (citing Ex. 1006 ¶¶ 77–79, 133; Ex. 1005, 3:19–22,
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`5:18–26).
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`Petitioner also contends that Kadomura teaches changing the
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`temperature of its substrate holder to change wafer temperature using a
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`control device with a PID controller during the two step etching process. Id.
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`at 34. For example, a polysilicon layer is etched at -30°C in a first step
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`followed by etching at 50°C in a second step. Id. In another example, a
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`silicide layer and a portion of a polysilicon layer are etched at 20°C in a first
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`step followed by etching the remaining portion of the polysilicon layer at
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`-30°C in a second step. Id. at 35. Petitioner contends that it would have
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`been obvious to etch the remaining polysilicon layer at 50°C in the second
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`step (instead of -30°C) in order to increase the etching rate in view of
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`Kadomura’s teaching to etch at 50°C and that “radical reaction is promoted
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`by increasing the specimen temperature to 50°C. Id.
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`
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`Patent Owner raises several arguments in response to Petitioner’s
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`proposed ground of unpatentability. For example, Patent Owner argues that
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`neither Kadomura nor Matsumura individually teach (1) “sensing a substrate
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`holder temperature,” (2) a “substrate holder [that] is heated to a temperature
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`operable” or (3) changing the temperature “within a preselected time period”
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`as required by claim element 56[b]. Prelim. Resp. 5–6. Patent Owner also
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`argues that Petitioner has not provided a sufficient motivation to combine
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`the teachings of Kadomura and Matsumura. Id. at 7. Specifically, Patent
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`Owner argues that Matsumura’s teaching would be unhelpful to Kadomura
`
`because the time interval between etches in Kadomura is dictated by the
`
`time it takes to change the gases. Id. (citing Ex. 1005, 7:22–30). Patent
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`Owner points to language in Kadomura that states that “the time required for
`
`the rapid cooling does not constitute a factor of delaying the time required
`
`for the etching treatment of the specimen W.” Id. (citing Ex. 1005 6:55–62).
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`On this record, we are not persuaded by Patent Owner’s individual
`
`attacks on Kadomura and Matsumura. It is well-settled that “non-
`
`obviousness [cannot be established] by attacking references individually,”
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`when, as here, the asserted ground of obviousness is based upon the
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`combined teachings of Kadomura and Matsumura. In re Keller, 642 F.2d
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`413, 426 (CCPA 1981). Instead, the test is what the combined teachings of
`
`these references would have taught or suggested to one with ordinary skill in
`
`the art. In re Young, 927 F.2d 588, 591 (Fed. Cir. 1991). In this case,
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`Petitioner’s asserted ground of obviousness are based upon the combined
`
`teachings of Kadomura and Matsumura. Additionally, Petitioner has
`
`articulated reasons combine the references. See, e.g., Pet. 25–43. For
`
`example, Petitioner contends that it would have been obvious to measure the
`
`substrate temperature holder of Kadomura to confirm that the directed
`
`temperature was achieved. Id. at 28–29. Petitioner further argues that it
`
`would have been obvious to use the temperature sensor of Matsumura to
`
`measure and set the temperature of Kadomura’s substrate holder to allow a
`
`chipmaker to directly gauge how well heat was transferred between the
`
`holder and the wafer, to obtain temperature transfer and relationship data to
`
`adjust recipes and improve processing efficiency. Id. at 32; see also id. at 31
`
`(stating Matsumura teaches that its temperature control methods can also be
`
`applied to etching processes); Ex. 1003, 10:3–7.
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`We are persuaded, based on the current record at this stage of the
`
`proceeding, that Petitioner has established a reasonable likelihood that claim
`
`56 would have been unpatentable over the combined teachings of Kadomura
`
`and Matsumura.
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`We have also considered Petitioner’s arguments and evidence that
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`Kadomura teaches etching at least one layer in “a chlorine-containing
`
`ambient” as required by claim 58, which depends from claim 56. Pet. 43.
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`Patent Owner presents no arguments directed specifically to this claim. We
`
`are persuaded, on the current record, that Petitioner has demonstrated a
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`reasonable likelihood that it would prevail on its challenge to claim 58 as
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`well.
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`E. Asserted Obviousness of Claim 57
`over Kadomura, Matsumura, & Muller
`
`Petitioner contends that claim 57 would have been obvious under 35
`
`U.S.C. § 103(a) over the combined teachings of Kadomura, Matsumura, and
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`Muller. Pet. 44–48. Petitioner explains how this proffered combination
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`purportedly teaches the subject matter of claim 57 and asserts that a person
`
`of ordinary skill in the art would have had reason to combine the teachings
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`of Kadomura, Matsumura, and Muller. Id. Petitioner relies on the Bravman
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`Declaration in support of its contentions. Id.
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`1. Muller
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`Muller is directed to methods of shaping etch profiles by controlling
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`wafer temperature using an electrostatic chuck and coolant circulating
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`through a cathode and by changing the pressure of the gas filled in the gaps
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`between the wafer and the cathode. Ex. 1002, [54], Abstract, 1:7–12, 1:44–
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`64, 4:51–5:25. Figure 4 of Muller is reproduced below.
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`
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`Figure 4 depicts wafer 104, electrostatic chuck 105, cathode 106, and gas
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`filled gap 110 between cathode 106 and wafer 104. Id. at 4:39–43, 51–55.
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`Muller teaches that the change in taper angle of etched trenches
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`correlates with increasing wafer temperature during the etching processes.
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`Ex. 1002, 3:33–66, Figs. 1, 2. Muller explains that changing pressure of the
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`gas filled in the gaps between the wafer and cathode, which can be
`
`accomplished in a very short period of time, results in an immediate effect
`
`on wafer temperature. Id. For example, wafer temperature can be increased
`
`by approximately 50ºC over a time of “several seconds” during etching. Id.
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`at 4:64–5:25, 5:41–48.
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`In one example, Muller teaches performing an initial etch at either
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`125ºC or 145ºC. Id. at 3:45–52, 3:56–66. The two etching temperature
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`examples corresponded to two different coolant temperatures. For example,
`
`use of a cathode coolant at 10ºC results in a wafer temperature of
`
`approximately 125°C, while use of a cathode coolant at 30ºC results in a
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`wafer temperature of approximately 145ºC. Id. at 3:45–52. Figure 3 below
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`shows the wafer temperature at the two cathode coolant temperatures as a
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`function of time.
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`Figure 3 depicts a graph illustrating the change in wafer temperature for
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`various coolant temperatures as a function of etch time.
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`In another example of an etching process, the gas-filled gap is
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`pressurized for a first time period and then the pressure in the gap is rapidly
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`changed to a second pressure for a second period of time. Id. at 4:64–5:3.
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`Then, the gas pressure underneath the chuck is changed to increase wafer
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`temperature by 50ºC in “several seconds” during etching. Id. at 4:64-5:25,
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`5:41–48. In this example, using a 30°C coolant, the initial pressure is
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`maintained for 70 seconds, after which the gap pressure is decreased for the
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`remaining 6 minutes of etch time. Id. at 5:26–33.
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`2. Analysis
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`Petitioner contends that dependent claim 57, which depends from
`
`claim 56 and further requires the change from the first to the second
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`substrate temperature “occurs within less than about 5 percent of the total
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`etching process time”, would have been obvious under 35 U.S.C. § 103(a)
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`over the combined teachings of Kadomura, Matsumura, and Muller. Pet.
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`44–48. Petitioner relies on the Bravman Declaration in support of its
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`contentions. Id. For example, Petitioner contends that Matsumura teaches a
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`“430 second” two step-etching process and that the temperature change
`
`between the two processes occurs “within several seconds,” which is less
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`than 5% of the total etching time. Id. at 44–45. Petitioner further argues,
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`inter alia, that it would have been obvious to incorporate Muller’s
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`continuous etch approach and backpressure temperature control design in the
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`Kadomura-Matsumura system to make temperature changes more rapid. Id.
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`at 45. Petitioner further notes that in Kadomura it is not necessary to
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`exhaust the gas between two etching steps when the same etching gas is used
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`for the two steps and that one skilled in the art would have omitted the
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`exhaustion step to etch continuously (as in Muller) in order to increase
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`throughput. See, e.g., id. at 45–46 (citing Ex. 1006 ¶¶ 42, 162).
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`At this stage in the proceedi
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