A.
`
`(_.
`
`JEDEC Standaed No. 21-C
`Page 3.9.4-10
`
`44/40
`TSOP-2
`
`0.400"
`PJN PITCH
`O.Bmm
`
`13
`
`14
`
`15
`
`17
`
`18
`
`21
`
`TOPVIEW
`
`--uw --rw
`
`Re
`AO
`
`A1
`
`A2
`
`A3
`
`A4
`vcc
`
`)
`
`-G'
`
`* Note:TheJEDECStandard
`30 term tor the TSOP-2
`· -- packag& is PDSo-G
`
`ROW!REFRESH ADDRESSES
`COLUMN ADDRESSES
`
`NJ THROUGH A7
`NJ THROUGH A7
`
`FIGURE 3.9.4-0
`64K BY 16 DRAM WITH 2 WIN TSOP-2
`
`Release 3
`
`Jedec 0007770
`
`jx0056-091
`
`91
`
`

`

`256K X 16 DRAM
`
`2
`
`3
`
`4
`
`5
`
`6 40 PIN 3
`SOJ
`7
`a 0.400" 3
`PP:0.050"
`9
`3
`
`10
`
`11
`
`40 PIN
`DIP
`14 0.400" 2
`PP:0.100"
`
`15
`
`2
`
`JEDEC Standard No. 21-C
`Page 3.9.4-11
`
`VSS
`
`0015
`
`0014
`
`0013
`
`0012
`vss
`
`0012
`
`0011
`
`0010
`
`009
`
`DSF1
`
`Ce'
`G'
`
`AS
`
`A7
`
`A6
`
`AS
`
`A4
`vss
`
`VDD
`
`000
`
`001
`
`002
`
`003
`voe
`
`004
`
`005
`·oQ6
`
`007
`
`NC
`
`i:W
`uw
`Re:
`
`NC,AS
`
`AO
`
`A1
`
`A2
`
`A3
`voe
`
`ROW/REFRESH ADDRESSES
`COLUMN ADDRESSES
`
`AO TO AS
`AO TO AS
`
`AOTOA9
`AOTOA7
`
`512 REFRESH
`
`1K REFRESH
`
`FIGURE 3.9.4-7 A
`256K BY 16 DRAM WITH EXTENDED FUNCTIONS IN DIP AND SOJ
`Release 4
`
`- - - · -·-·---·-·-···-
`
`.Jedec 0007771
`
`jxoos6-o92 I
`
`92
`
`

`

`JEDEC Standard No. 21-C
`Page 3.9.4-12
`
`MANDATORY TRUTH TABLE FOR 256K BY 16 DRAM with EXTENDED FUNCTIONS
`
`Mnem.
`
`Function
`
`RW
`READ!WRITE
`BW
`BLOCK WRITE
`LOAD MASK REGISTER
`LMR
`LOAD COLOR REGISTER
`LCR
`WAITE, MASKED
`RWM
`BLOCK WRITE, MASKED
`BWM
`CSR REFRESH (1)
`CBR
`CBR REFRESH (2)
`CBAN
`FLASH WRITE
`FWT
`• IF OSF2 IS PRESENT
`·csR(1) - All optional modes reset
`CBR(2) - Any optional modes remain active
`
`CE
`1
`1
`1
`1
`1
`1
`0
`0
`
`,
`
`Valid at RE
`w DSF(1)
`1
`0
`1
`0
`1
`1
`1
`1
`0
`0
`0
`0
`1
`0
`1
`1
`1
`0
`
`G
`
`,
`
`1
`1
`1
`1
`1
`x
`x
`1
`
`Valid at CE
`
`·osF2
`0
`0
`0
`0
`0
`0
`0
`0
`0
`
`DSF(1)
`0
`1
`0
`1
`0
`1
`x
`x
`x
`
`)
`
`FIGURE 3.9.4-7 B
`256K BY 16 DRAM MANDATORY EXTENDED FUNCTION TRUTH TABLE
`Release4
`
`Jedec 0007772
`
`jxoos6-o93 I
`
`93
`
`

`

`JEDEC Standard No. 21-C
`Page 3.9.4-13
`
`4M X 16 CRAM
`
`vss
`
`2
`
`3
`
`4
`
`5
`
`54 PIN
`TSOP2
`0.500"
`
`see
`note
`on
`width
`
`G
`NC
`NC
`
`NC
`
`A7
`
`A6
`
`)
`
`4K REFRESH
`
`BK REFRESH
`
`ROW/REFRESH ADDRESSES
`AO-+ A11
`AO -+ A9
`COLUMN ADDRESSES
`• NOTE: Pin 25 is A 12 for BK refresh and NC for 4K refresh
`• NOTE: The JEDEC Std. 30 term for the TSOP-2 package is PDSo-G.
`This standard recognizes that some early deliveries of this part may have to be in a 0.6" wide package
`
`AO-+ A12
`AO-+ AB
`
`Release 4
`
`FIGURE 3.9.4-8
`4M BY 16 DRAM IN TSOP-2
`
`Jedec 0007773
`jx0056-094 J
`
`94
`
`

`

`ADORES -
`
`JEDEC Standard No. 21-C
`Page 3.9.5-5
`
`.,...._ ______ tRELREL
`
`(tRPS)
`
`• - - - IREHREL
`
`-
`
`-
`
`rRELREH --~I
`
`RE
`
`ICELREL
`
`IRELCEH
`
`"CAS BEFORE RAS REFRESH TIMING"
`
`FIGURE 3.9.5-1 A
`DRAM ON CHIP REFRESH TIMING
`
`;::oo:
`::
`T 1
`
`- .
`
`:
`
`:--1REHREL--:
`
`~.:
`:"---
`
`:
`x:
`
`.\
`!/
`--~--~--~~~~~z·~/~~~~.
`
`- - - - '
`
`~
`cQ
`Ii I
`-:
`
`\
`
`:-
`
`I
`
`Q
`
`I
`
`CSR
`
`Initiate Self
`Refresh Mode
`
`Self Refresh
`
`Exit
`,
`• Self Refresh
`
`, Normal
`' Operating
`Mode
`
`Data Out may be either Tristate or Active depending on the state of CE\ when the cycle is entered.
`FIGURE 3.9.5-1 B
`DRAM SELF REFRESH MODE TIMING
`
`Release 4
`
`.Jedec 0007774
`
`jxoos6-o9s I
`
`95
`
`

`

`• b
`
`JEDEC Standard No. 21-C
`Page 3.9.5-0
`
`tWlREL.> O
`
`H • WRITE ENABLED
`L. • WRITE DISABLED
`
`~~---------(~_v_A_uo_o_A_T" __ ,_N ____ __.)~~~~-
`
`--<: MASK DATA
`
`DQ
`
`)
`
`FIGURE 3.9.5-2
`DRAM BIT WRITE TIMING
`
`Jedec 0007775
`
`Releaee 1
`
`jxoos6-o96 I
`
`96
`
`

`

`DRAM SPECIAL TEST AND OPERATIONAL MODES
`
`JEOEC Standard No. 21-C
`Page 3.9.5-7
`
`PURPOSE
`1
`This standard defines a scheme for controlling a series of special modes tor address multiplexed DRAM. The standard defines the logic
`interface required to enter, control, and exit from the special modes. In addition, it defines a basic special test mode plus a series of other
`special test and operational modes.
`
`2
`SPEClAL MOOE INITIATE
`The special modes will be initiated by the W\ AND CE\ BEFORE RE\ clock sequence shown in Fig.A2-1. This sequence is called "Write •
`Enable and CAS before RAS" or "WCBR". When this clock sequence is generated, !he state of the B low order Row Address bits (address
`key) will define the mode to be selected (see Par. 4) if optional modes are implemented. This mode will be latched and remain in affect until a
`special release c:ycle is generated or a new initiate c:ycle defining some ottler special mode is generated.
`
`Following the initiate cycle, all subsequent c:ycJes except refresh cycles (see pars. 3 & 5), will be operating cycles as allowed by the spacial
`mode selected.
`
`3 MODE EXIT
`A special mode will be Cleared and the memory device retumed to its normal ~rational state by the application of any normal REFRESH
`c:ycle, "RAS only refresh", (ROA) or "CAS before RAS refresh" (CSRR).
`
`4 MODE SELECTION
`Devices meeting this standard must have an implementation of the BASIC TEST MODE (see par 6) but also may contain other modes as
`options. When optional special modes are implemented, they will be selected by the state of the 8 least significant ROW Address bits at the
`time that INITIATE clock sequence is provided. The address space tor the mode selection is defined as follows.
`The special modes as selected by the 8-0it Address Key will be partitioned into tour (4) subsets as follows:
`
`1 - JEOEC Registered Modes
`
`2 - Reserved for future expansion
`
`3 - Vendor Specific Modes
`
`4 - Customer Specific MOdes
`
`4.1 MODE PARTITIONING
`These modes and their partitioning will be as diagrammed in Table A2-2. Additional address bits abOve A 7 can be used to select additional
`pages of MODE definitiOn (see par.4.3). Mode subgroups 1 and 2 will be further subdivided into "Test" and "Operationar modes as follows:
`
`TEST MODES are those that implement some special test or measurement function or algorithm designed to enhance the ability of the
`Vendor or User to determine the integrity of, or to characterize, the part.
`
`OPERATIONAL MODES are ttlose that alter the operational characteristics of ttle part but do not interfere with its function as a storage
`device and are intended to be used in system operation.
`
`The special mode can be changed at anytime by the application of a mode initiate clock sequence with the appropriate address key to define
`the new mode.
`
`4.3 ADDITIONAL MODES
`The additional address bits above A7 can be used as needed to define additional pages of MODE definitions.
`
`5
`JEDEC REGISTERED SPECIAL MODE REFRESH
`-Refresh can be performed while in a special mode by the following means.
`
`( 1) - An initiate cycle is generated (W\ and CE\ before RE\) with the address key used to select the mode currently in effect
`(2) - Any normal read or write cycle will perform REFR.ESH.
`
`-The Initiate Special Mode clock sequence will always perform an on-chip refresh.cycle even when the MODE is being changed.
`
`-This refresh applies to JEDEC Special Registered Modes only
`
`Release 4
`
`Jedec 0007776
`
`-~jx0056-097 J
`
`97
`
`

`

`JEOEC Standard No. 21-C
`Page 3.9.5-8
`
`6 BASIC TEST MODE DATA ALGORITHM
`Any memory device that implements the JED EC Registered modes must implement the "Basic Test Mode" as a minltnum. Any other of the
`special modes which are registered and listed in Table A2-3, maybe implemented atlheoption of the manufacturer. Additional MODES and
`test algorithms may be registered as needed.
`
`When a memory device is operating in the Basic Test Mode, data !hat are presented to be written into the memory will be written into multiple
`locations depending upon the internal device organization and the number of parallel bits in the internal data bus (4, B, 16, or other) (see par.
`7). When a Read Operation is done, the data recovered will include the same set of data bits on the parallel data bus. The intemal logic of the
`memory device will compare the states of all bits of the internal data bus. If all internal bits are equal, the "O" pin will take the state equal to ·1 ••
`If any internal data bits are not equal , then "O" will equal "O". This is called the "1101=" test algorithm.
`
`TheBASICTESTMOOEisassignedtheaddresskeys,•Arr1·s·andallsubsetsofthiskeyfrom.2loworder1'stoall1's(seeAppendix2). ftis
`acceptable for a device which implements the BASIC TEST MOOE and optional test modes to sense a low order subset of the key address
`field but it is recomended that at feast 3 bits be used to minimize the chances of ambiguities in the mode selection.
`
`ADDRESS SPACE COMPRESSION CONTROL
`7
`Any Standard or Registered test algorithm in Which the address space of the device is compressed by test operations on multiple intemal
`data bits will have the address bits which control the internal data bJtsasdefined in Table A2-1. In any test operations, the state of these bits
`will be "don't care•.
`
`w
`
`An
`
`tWL 1 REl2 & tCEL 1 AEL2 MUST BE 2: 0
`
`,....~~~~~~~~~~--
`
`)
`
`TRAILING EDGE TIMING NOT CRITICAL
`
`MODE SELECTION INPUT FOR MULTIPLE MOOE OP-
`
`ROW ADDRESS
`
`DON'T CARE AT COLUMN AOORESS TIME
`
`A2-~ SPECIAl OPERATIONAL MODE INmATE CYCLE
`NOTE: The timing parameters of the pulses are not specified in this standard but care must be taken in the device specification to define
`minimum and maximum pulse durations toinsurethatnoisepulses will be rejectedandthatintentionalcontrol sequencieswill be recognized.
`
`FIG
`
`Release4
`
`Jedec 0007777
`
`jxoos6-o9a I
`
`98
`
`

`

`JEDEC Standard No. 21-C
`Page 3.9.5-9
`
`- -)
`
`Table A2-1-A, 1M TO 16M ORAM ADDRESS COMPRESSION CONTROL BITS
`
`Data Bus Width(# bits)
`
`Control Address Bits
`Xi DATA INTERFACE
`
`2
`4
`B
`16
`
`RA(MSB), CA(MSB)
`RA(MSB), CA(MSB), CAO
`RA(MSB), CA(MSB), CAO, CA 1
`
`X4 DATA INTERFACE
`CAO
`CAO, CA1
`
`-
`
`(MSB = Most Significa.11
`--
`Bit)
`
`Table A2-1-B 64M DRAM ADDRESS COMPRESSION CONTROL BITS
`Compression Address= CA(MSB), CA(MSB-1 ), ... ,CA(MSB-n)
`where 2n-1 = the · number of internal parallel data, test .bits = Compression factor
`64MX 1
`16MX4
`CA12>CA8
`
`PARALLEL TEST BITS
`32(n=4)
`
`BMXB
`
`8(n=2)
`
`4(n=1)
`
`2(n=O)
`
`CA10>CAB
`
`CA 10>CA9( 4K)
`
`TABLE A2-1-C 64M DRAM ADDRESS ASSIGNMENT TABLE
`
`4MX 16
`
`CA9(4K)
`
`Test DEVICE
`Bits
`
`RFSH
`CYCLES
`
`32
`
`64M X 1
`
`32
`
`64M X 1
`
`BK
`
`8
`
`8
`
`4
`
`4
`
`2
`
`2
`
`1
`
`1
`
`16M X 4
`
`16M X 4
`
`BK
`
`BM X 8
`
`4K
`
`BM X 8
`
`SK
`
`4M X 16
`
`4K
`
`4M X 16
`
`BK
`
`2M X 32
`
`2M X 32
`
`4K
`
`BK
`
`Release 4
`
`Address Assignments
`
`These addresses can be used as common addresses for
`64M X 1, 16M X 4, BM X B, & 16M X 32 devices
`
`~ compression address
`lLQ= RAn/CAn
`
`Jedec 0007778
`L ___ ______ _ -_ __ - ____ __ ~0~099J
`
`99
`
`

`

`JEDEC Standard No. 21-C
`Page 3.9.S-10
`
`TABLE A2-2 SPECIAL MODE ADDRESS KEY SPACE
`The SPECIAL MODE Address Key space will be as shown in the following Kamaugh map with the exception
`of those codes reserved for the BASIC TEST MODE:
`
`-- 1
`
`A6
`
`AS
`
`A5
`
`AS
`
`A5
`
`AS
`
`JED EC
`Registered
`Modes
`
`Vendor
`Specific
`Modes
`
`Reserved for
`Expansion
`
`TEST
`
`OPERATION
`
`Customer
`Specific
`Modes
`
`A7
`
`A7
`
`AO - A4 define individual modes within a block
`JEDEC REGISTERED MODES - These are the modes that are defined in detail in registration documents.
`The function(s) shall be performed as defined with no variations (see Appendix 2 for list of registered modes).
`VENDOR SPECIFIC MODES - These are those modes that are implemented by a Vendor for his own in-
`house use. The details will be revealed only at the discretion of the Vendor. The code assignments will have
`no standardization from vendor to vendor except at their discretion.
`CUSTOMER SPECIFIC MODES - These modes are implemented by a vendor at the request of a specific
`customer. The information on these modes is not revealed except at their discretion.
`
`)
`
`TABLEA2-3
`REGISTERED MOOE ASSIGNMENT PAGE O TABLE
`
`ROW ADDRESS BIT
`7,6,5,4,3,2, 1,0
`0,0,0,0,0,0;0,0
`0,0,0,0,0,0, 1, 1
`0,0,0,0,0, 1, 1, 1
`0, 0, 0, 0, 1, 1, 1, 1
`0, 0, 0, 1 ' 1, 1, 1, 1
`0, 0, 1, 1, 1, 1, 1, 1
`• 0, 1, 1, 1, 1, 1, 1, 1
`* 1, 1, 1, 1, 1, 1, 1, 1
`
`FUNCTION
`
`NOT ASSIGNED
`BASIC TEST MODE, 1 /0/=
`BASIC TEST MODE, 1/0/=
`BASIC TEST MODE, 1/0/=
`BASIC TEST MODE, 1/0/=
`BASIC TEST MODE, 1 /0/=
`BASIC TEST MODE, 1/0/=
`BASIC TEST MODE, 1/0/=
`
`Additional address bits above A7 can be used to select additional pages of MODE definition.
`• It should be noted that these pre-assigned address codes do not fall into the address space assigned to
`JEDEC Registered Modes.
`NOTE:: A table of registered optional modes along with definitions will be compiled by the Committee and
`published periodically.
`
`Release 4
`
`Jedec 0007779
`
`jx0056-1 00 J
`
`100
`
`

`

`.
`
`.. l
`
`PIPELINED FAST 'PAGE MOOE
`
`PIPELINED FAST PAGE MOOE READ - WAITE
`
`JEDEC Standard No. 21-C
`Page 3.10.4-11
`
`1
`
`I
`
`J
`
`I
`
`:
`
`I
`
`:
`0
`
`I
`I
`
`I
`
`;
`
`:
`
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`
`•
`
`I
`
`.
`
`I
`
`I
`1
`
`'CE
`,
`,
`'
`'
`
`A<@dA(A) H_a ...... iA-cs)-x _______ X cA€> H_c_A.....,~o->""x·-----
`. ( Q(A}; x O(B): H
`; D(C) x--: -0(-0)-)----
`oo.@ :
`~~G-:-\:i='---------·-----<v-~---.~----~~--c~
`. .
`\ I I ~ I I L
`w@:
`.
`'
`'
`DSF • •
`
`PIPELINED FAST PAGE MODE WP.ITE - READ
`•
`J
`"RE~
`.----~------~--------------~-----------------­
`'
`Ce
`:
`..b I
`A(·~ c~(A) H CA(B) X
`~ : O(A) x :D(B) x l
`
`I
`
`I
`I
`
`I
`
`I
`
`,...-,_' ___,
`
`I
`
`-
`
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`I
`
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`
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`
`o
`
`t
`
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`
`'
`
`-------~-
`
`X cAcc> H cA@> H CA~E> X
`: x ace! x Q(D) x Q(E
`.
`I
`L
`
`•
`'
`•
`-----~--------~,~j\
`DTG
`' '
`• •
`w-{wB\
`:L
`' '
`'
`OSF •
`'
`
`I
`
`LJ
`
`'
`'
`
`NOTE: BOTH EARLY WAITES AND LATE WRITES ARE REPRESENTED
`
`FIGURE 3.10.4-38
`
`Releaae2
`
`L __
`
`.Jedec 0007780
`_ -~jx0056-101 J
`
`_
`
`101
`
`

`

`JEDEC Standard No. 21-C
`Page 3.10.4-12
`
`MPDRAM OPTIONAL MODES and CYCLES
`
`This Standard defines an optional READ mode for address multiplexed Multi-Port DAAMs.
`
`EXTENDED DATA OUT FAST PAGE MOOE
`
`This is a variation of the Fast Page Mode defined in Sec. 3.9.5.4, Par. 1.3 .. It differs from Fast Page Mode as
`follows: 1) in a READ operation, the LH transition of CE\ with RE\ active will not cause the data out terminals
`to go into a high impedence state. Instead, the data out will remain valid with data from the previously read
`address. During sequential READ operations, the data out terminals will transition from old data to new data
`at a time defined by the performance specification for the part.
`Any of the following·conditions wm cause the data out terminals to go to the high impedence state:
`1) RE\ and CE\ are both inactive.
`2) G\ is inactive.
`3) W... in active.
`
`The following timing diagram illustrates this operating mode but is included for reference only.
`
`Re-f\
`
`I
`
`I
`
`EXTENDED DATA OUT FAST PAGE MODE
`I
`I
`I
`I
`
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`I
`I
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`
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`
`Data Out may be either translate or Active depending on the state of CE\ when the cycle is entered.
`
`FIGURE 3.10.4-4
`MPDRAM EXTENDED DATA OUT FAST PAGE MODE
`
`Release4
`
`.Jedec 0007781
`
`jx0056-102
`
`102
`
`

`

`3.11 Synchronous Dynamic Random Access Memory {SDRAM)
`
`JEDEC Standard No. 21-C
`Page 3.11-1
`
`The following SDRAM standards were developed by Committee 42.3. The devices
`described are compatible with TTL and/or one or more of the low voltage interface
`standards adopted by Committee JC-16 as defined in the individual device stan(cid:173)
`dards. The device standards require that the memory devices must operate with sig(cid:173)
`nal levels and power supply voltages that are consistent with those used in the logic
`family(s) specified.
`
`)
`
`Release4
`
`Jedec 0007782
`
`jx0056-103
`
`103
`
`

`

`3.11.1 Bit Wide SDRAM
`
`JEDEC Standard No. 21-C
`Page 3.11.1-1
`
`No standards have been developed for devices with this configuration.
`
`Release 4
`
`Jedec 0007783
`
`jx0056-104
`
`104
`
`

`

`3.11.2 NIBBLE WIDE SDRAM
`
`JEDEC Standard No. 21-C
`Page 3.11.2-1
`
`3.11.2.1 - 4M BY 4 SDRAM IN TSOP2
`CAPACITY-4M WORDS OF 4 BITS
`LOGIC FEATURES-This device will contain all of the logic features described in Sec. 3.11.5
`ELECTRICAL INTERFACE-TTL or LVTIL
`PACKAGE-44 Pin TSOP2, 0.4" WIDE, O.Bmm PIN PITCH
`PIN ASSIGNMENT-Fig. 3.11.2-1
`
`)
`
`Release 4
`
`.Jedec 0007784
`
`jxoos6-1 as I
`
`105
`
`

`

`JEDEC Standard No. 21-C
`Page 3.11.2-3
`
`2M X 9 SDRAM
`
`2M X 8 SDRAM
`
`4MX4SORAM.
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`3
`
`44 Pin
`TSOP2
`0.400"
`9 PIN PITCH 3
`PP=O.S mm
`10
`3
`
`11
`
`TOP VIEW
`
`vss 1--1--~
`
`CONFIGURATION
`
`4MX4
`
`2MX 819
`
`ROW ADDRESS
`COLUMN ADDRESS
`
`AOTOA11
`AOTOA9&A11
`
`AOTOA11
`AOTOAB&A11
`
`The JEOEC Std. No 30 designator for
`the TSOP2 package is PDSC>-G
`
`Release 4
`
`FIGURE 3.11.2-1
`4M X 4 SCRAM IN TSOP2
`
`Jedec 0007785
`
`jxoos6-1 06 I
`
`106
`
`

`

`3.11.3 BYTE WIDE SDRAM
`
`JEDEC Standard No. 21-C
`Page 3.11.3-1
`
`3.11.3.1 - 2M BY 8 or 9 SDRAM IN TSOP2
`CAPACITY-2M WORDS OF 8 or 9 BITS
`LOG IC FEATURES-This device will contain all of the logic features described in Sec. 3.11.5
`ELECTRICAL INTERFACE-TIL or LVTIL
`PACKAGE---44 Pin TSOP2, 0.4" WIDE, O.Bmm PIN PITCH
`PIN ASSIGNMENT-Fig. 3.7.3-1
`
`Release4
`
`Jedec 0007786
`
`jx0056-107
`
`107
`
`

`

`JEDEC Standard No. 21-C
`Page 3.11.3-3
`
`2M X 9 SDRAM
`
`2M X SSDRAM
`
`44 Pin
`TSOP2
`0.400"
`
`3
`
`l ,,
`
`TOP VIEW
`
`CONFIGURATION
`
`4MX4
`
`2M X 819
`
`ROW ADDRESS
`COLUMN ADDRESS
`
`AO TO A11
`AOTOA9&A11
`
`AO TO A11
`AOTOAB&A11
`
`The JEDEC Std. No 30 designator for
`the TSOP2 package is PDSD-G
`
`Release 4
`
`FIGURE 3.11.3-1
`2M BY 8 OR 9 SDRAM IN TSOP2
`
`Jedec 0007787
`
`jxoos6-1 oa I
`
`108
`
`

`

`3.11.5 SDRAM Architectural and Operational Features
`The following standards describe features or characteristics that are applicable to one or more of the
`SDRAM devices described in section 3.11 of Std. 21-C.
`
`1
`
`JEDEC Standard No. 21-C
`Page 3.11.5-1
`
`Release 4
`
`Jedec 0007788
`
`jxoos6-1 og I
`
`109
`
`

`

`3.11.5.1 - SDRAM FUNCTION TRUTH TABLE
`This table defines the interface states required to execute the standard SDRAM operational
`functions.
`3.11.5.2- SCRAM FUNCTION TRUTH TABLE FOR CKE
`This table defines the interface states required to execute the standard SDRAM operational
`functions with respect to the CKE input.
`
`JEDEC Standard No. 21-C
`Page 3.11.5-3
`
`3.11.5.3- SDRAM MODE REGISTER ARCHITECTURE
`This standard describes the architecture of tl'le SDRAM internal MODE REGISTER and the
`codes that are allowable for use in it.
`3.11.5.4 through 3.11.5.15-SORAM OPERATIONAL CYCLES ANO MODES
`The following standards define and describe a number of operational cycles and modes of
`SDRAM. They are ordered roughly in the se~uence in which they would be used in normal
`SDRAM operation.
`3.11.5.4- POWER ON SEQUENCE (RECOMMENDED)
`This standard gives a recommended power, clock, and logic-4evel sequence to be used on power(cid:173)
`up to prevent data bus contention.
`3.11.5.5-AUTO PRECHARGE
`This standard gives the logic function used to active the AUTO-PAECHAAGE function.
`3.11.5.6-PRECHARGE ALL BANKS
`This standard gives the logic function used to activate the PRECHARGE-ALL-SANKS function.
`3.11.5.7- MOOE REGISTER WRITE TIMING
`This standard defines the logic sequence and timing required to write into the MODE REGISTER.
`3.11.5.8 - AUTO REFRESH
`This standard defines the logic state and interface sequence required to perform an AUTO RE·
`FRESH
`3.11.5.9-WRITE LATENCY
`This standard defines WRITE LATENCY and mustrates it with a timing diagram.
`3.11.5.10-0QM LATENCY FOR READS ANO WRfTES
`In this standard DOM LATENCY is defined and the relationships between the DOM signal and the
`interface data tor READs and WRfTEs is defined and shown in timing diagrams.
`3.11.5.11- PRECHARGE TIMING FOR READS
`This standard describes the relationship between the assertion of a PRECHARGE command and
`data out from a READ command.
`3.11.5.12 ~ COt.tJMN ADDRESS TO COLUMN-ADDRESS DELAY
`This standard defines constraints imposed on the CA to CA delay and illustrates them wtth a timing
`diagram.
`
`3.11.5.13 - CKE TIMING FOR POWER DOWN
`This standard describes the interface sequence required to place the SDRAM into the POWER(cid:173)
`DOWN state using CKE.
`3.11.5.14 - SELF REFRESH ENTRY AND Exrr
`This standard defines the logic states and timing sequence used to enter and exit the SELF-RE·
`FRESH mode.
`3.11.5.15 - CKE TIMING FOR CLOCK SUSPENI"\
`This standard describes the interface timing sequence when CKE is used to suspend the clock.
`
`Release 4
`
`Jedec 0007789
`
`-~jx0056-110 J
`
`110
`
`

`

`CURRENT s
`STATE
`
`IDLE
`
`ROW
`ACTIVE
`
`READ
`
`WRITE
`
`JEOEC Standard No. 21-C
`Page 3.11.5-5
`
`SCRAM FUNCTION TRUTH TABLE
`
`RE CE
`
`w
`
`An
`
`ACTION
`
`x
`H
`L
`x
`H
`L
`H
`L
`x
`x
`H
`L
`H
`L
`x
`x
`H
`L
`H
`L
`H
`L
`x
`x
`H
`L
`H
`L
`H
`L
`x
`x
`H
`L
`H
`L
`x
`x
`x
`H
`L
`H
`L
`x
`x
`
`NOP
`NOP
`ILLEGAL2
`ILLEGAL2
`Row (&Bank) active; Latch Row Address
`N0?4
`Auto-Refreshs
`Mode Register Access5
`
`x
`x
`BA
`BA.CA
`BA.RA
`BA,A10
`x
`Op-code
`x
`NOP
`x
`NOP-
`BA, CA, A10 Begin Read; Latch CA; Detennine AP
`BA, CA, A10 Begin Write; Latch CA; Determine AP
`ILLEGAL2
`BA,RA
`Precharge
`BA, A10
`x
`ILLEGAL
`x
`NOP (Continue Burst to End;=>Row Active)
`x
`NOP(Continue Burst to End;==-Row Active)
`RESERVED (Term. Burst);==-Row Active
`BA
`BA,CA,A10 Term Burst, New Read, Determine AP3
`BA, CA, A10 Term Burst, Start Write, Determine AP3
`ILLEGAL2
`BA,RA
`Term Burst, Precharge Timing for Reads
`BA, A10
`x
`ILLEGAL
`x
`NOP(Continue Burst to End;==-Row Active)
`x
`NOP(Continue Burst to End;==-Row Active)
`RESERVED (Term Burst);==-Aow Active
`BA
`BA, CA, A10 Term Burst, Start Read, Determine AP3
`BA,CA,A10 Term Burst, New Write, Determine AP3
`ILLEGAL2
`BA,AA
`Term Burst, Precharge3
`BA, A10
`x
`ILLEGAL
`x
`NOP (Continue Burst to End;=>Precharge)
`x
`NOP (Continue Burst to End;==-Precharge)
`-· - - - -l[[EGA[Z ___ -
`- - - ---- --- -
`BA
`ILLEGAL2
`BA, CA, A10
`x
`ILLEGAL
`ILLEGAL2
`BA, RA, A10
`x
`ILLEGAL
`x
`NOP (Continue Burst to End;==-Precharge)
`x
`NOP (Continue Burst to End;-Precharge)
`..
`ILLEGAL2
`BA
`ILLEGAL2
`8A,CA,A10
`x
`ILLEGAL
`ILLEGAL2
`BA, RA, A10
`x
`ILLEGAL
`
`-
`
`x
`x
`H
`H
`H
`H
`H
`L
`H
`L
`H
`L
`L
`L
`L
`L
`x
`x
`H
`H
`H
`L
`H
`L
`H
`L
`H
`L
`L
`L
`x
`x
`H
`H
`H
`H
`H
`L
`H
`L
`H
`L
`H
`L
`L
`L
`x
`x
`H
`H
`H
`H
`L
`H
`L
`H
`H
`L
`H
`L
`L
`L
`x
`x
`H
`H
`- --- H-- H
`H
`L
`L
`L
`H
`L
`L
`L
`x
`x
`H
`H
`H
`H
`H
`L
`H
`L
`H
`L
`L
`L
`
`H
`L
`L
`L
`L
`L
`L
`L
`H
`L
`L
`L
`L
`L
`L
`H
`L
`L
`L
`L
`L
`L
`L
`H
`L
`L
`L
`L
`L
`L
`L
`H
`READ
`L
`with
`L
`AUTO
`Precharge L
`L
`L
`L
`H
`WRITE
`with
`L
`L
`AUTO
`Precharge L
`L
`L
`L
`
`Release 4
`
`TABLE 3.11.5-1
`SDRAM FUNCTION TRUTH TABLE
`
`Jedec 0007790
`
`jx0056-111
`
`111
`
`

`

`JEDEC Standard No. 21-C
`Page 3.11.5-6
`
`ROW
`Activating
`
`WRITE
`Recovering
`
`ACTION
`
`NOP===-idle after tRP
`NOP===-idle after tRP
`ILLEGAL2
`ILLEGAL2
`ILLEGAL2
`NOP'
`ILLEGAL
`NOP===-Row Active <after tRCD
`NOP===-Row Active after tRCD
`ILLEGAL2
`ILLEGAL2
`ILLEGAL2
`ILLEGAL2
`ILLEGAL
`NOP
`NOP
`ILLEGAL2
`ILLEGAL2
`ILLEGAL2
`ILLEGAL2
`ILLEGAL
`NOP::oidle after tRP
`NOP=':.idle after tRP
`ILLEGAL
`ILLEGAL
`ILLEGAL
`NOP
`NOP
`ILLEGAL
`ILLEGAL
`ILLEGAL
`
`SDRAM FUNCTION TRUTH TABLE {contir1ued)
`CE w An
`s ~
`<_:I_
`·-· I
`STATE
`x x x
`x
`Precharging H
`x
`H
`H
`H
`L
`H
`BA
`H
`L
`L
`x
`H
`BA.CA
`L
`L
`H
`H
`BA.RA
`L
`L
`H
`BA, A10
`L
`L
`L
`x
`x
`L
`L
`L
`x x
`x
`x
`H
`x
`H
`H
`H
`L
`L
`H
`H
`H
`L
`x
`H
`L
`L
`BA.CA
`H
`H
`BA.RA
`L
`L
`BA,A10
`H
`L
`L
`L
`x
`x
`L
`L
`L
`x
`x
`x
`x
`H
`x
`H
`H
`H
`L
`H
`H
`BA
`L
`L
`x
`H
`L
`L
`BA.CA
`H
`H
`L
`L
`BA.RA
`H
`L
`BA,A10
`L
`L
`x
`x
`L
`L
`L
`x
`x
`x
`x
`Refreshing H
`x x
`H
`H
`L
`x
`x
`H
`L
`L
`x x
`H
`L
`L
`x
`x
`L
`L
`L
`x
`x
`x
`x
`H
`x
`H
`H
`H
`L
`x
`H
`H
`L
`L
`x
`x
`L
`H
`L
`x
`x
`x
`L
`L
`
`Mode
`Register
`Accessing
`
`BA= Bank Address
`AP;; Auto Preenarge
`
`Term = Terminate
`---·-- -NoP·= No Operation--
`
`ABBREVIATIONS
`RA = Row Address
`e,;..-~-column-.A:Cidress
`NOTES:
`1. Alf entries assume that CKE was active (HIGH) during the preceeding clock cycle and the current clock
`cycle.
`2. Illegal to bank in specified state; function may be legal in the bank il"dicated by BA, depending on the state
`of that bank.
`3. Must satisfy the "2n-ru1e•, bus contention, but tum around, and/or write recovery requirements.
`4. NOP to bank precharging or in idle state. May precharge bank(s) indicated by BA (and A10).
`5. Illegal if any bank is not idle.
`ILLEGAL = Device operation and/or data-integrity are not guaranteed
`
`TABLE 3.11.5-1
`SDRAM FUNCTION TRUTH TABLE (Continued)
`
`Release4
`
`Jedec 0007791
`
`L ___ - ________ · ____ -_ -______ ···_- __ 1oos6-~J
`
`112
`
`

`

`SDRAM FUNCTION TRUTH TABLE for CKE
`
`JEDEC Standard No. 21-C
`Page 3.11.5-7
`
`CK En s
`'RE CT w An ACTION
`x x x x x
`x
`INVALID
`H x x x x EXIT Self-Refresh~ ABI
`H
`L H H H x EXIT Self-Refresh~ ABI
`H
`L x
`ILLEGAL
`H H
`L
`H
`L x x
`L H
`ILLEGAL
`H
`L x x x
`ILLEGAL
`H
`L
`x x x x x NOP (Maintain Self-Refresh)
`L
`H x x x x
`INVALID
`H
`L H H H x EXIT Power Down~ABI
`L
`L H H H x EXIT Power Down=>ABI
`L
`L x x
`ILLEGAL
`L H
`L
`H H x
`ILLEGAL
`L
`L
`L
`L x
`ILLEGAL
`·L H
`L
`L
`x x NOP(Maintain Low-Power Mode)
`L
`L
`L
`L
`x x x x x Refer to Table 1
`H
`H x x x x Enter Power-Down
`L
`H H H x Enter Power-Down
`L
`L
`L x
`L H H
`ILLEGAL
`L
`x x
`L H
`ILLEGAL
`L
`L
`H x x
`L
`ILLEGAL
`L
`L
`H x Enter Self-Refresh
`L
`L
`L
`L
`L x
`ILLEGAL
`L
`L
`L
`L
`x x x x x NOP
`L
`x x x x x Refer to operations Table 1
`H
`x x x x x Begin Clock Suspend next cycles
`L
`x x x x x Exit Clock Suspend next cycles
`H
`x x x x x Maintain Clock Suspend.
`L
`
`CKErr-~
`
`CURRENT
`STATE
`Self-
`refresh6
`
`Power-
`Down
`
`H
`L
`L
`L
`L
`L
`L
`H
`L
`L
`L
`L
`L
`L
`All Banks H
`ldle7
`H
`H
`H
`H
`H
`H
`H
`L
`Any State H
`other than H
`listed
`L
`above
`L
`
`ABBREVIATIONS
`ABI = All Banks Idle
`NOTES:
`
`6. CKE Low-to-High transition will re-enable CK and other inputs asynchronously. A minimum setup time
`must be satisfied before any command other than EXIT.
`· 7:Power.;;;Down-and-se1t~Retresh can be entered· only from the All Banks Idle State.
`8. Must be legal command.
`
`TABLE 3.11.5-2
`SCRAM FUNCTION TRUTH TABLE for CKE
`
`Release 4
`
`Jedec 0007792
`
`jx0056-113
`
`113
`
`

`

`JEDEC Standard No. 21-C
`Page 3.11.5-8
`
`SDRAM Mode Register
`
`This Mode Register is located on the Synchronous DRAM (SDRAM) chip. Its purpose is to store the mode(cid:173)
`of-operation data. This data is written after power-on and before normal operation. The data contains the
`Burst Length, the Burst Type, the CE Latency, and whether it is to be operating in Test Mode, or Normal aper·
`ating mode. Q,Jing operation, this register (and therefore operation of the chip) may be changed. according
`to the requirements of the Mode-Register-Write Timing diagram. So, while operating in one mode, for exam·
`pie Burst of 4 ;11 sequential addresses; it can change to Burst of B in Interleaved address mode.
`
`16M/18M SDfiAM Mode Register architecture:
`
`Bit#
`
`11 10 9
`
`8
`
`7
`
`6
`
`5
`
`4
`
`3
`
`2
`
`1
`
`0
`
`The code shown is reserved
`for Test Mode entry.
`
`Ro 1 o I o i 1 I o I o I o 1 o I o I o I o I
`0 l 0
`
`0
`
`0
`
`0
`
`LTMODE
`
`BT
`
`B.L.
`
`_J
`
`BL
`000
`001
`010
`BURST
`...... LENGTH 011
`100
`101
`11 0
`1 1 1
`
`BT=O
`R• (1)
`R• (2)
`4
`8
`R•
`R•
`R•
`R" «FULL PAGE)
`
`BT=1
`R• (1)
`R• (2)
`4
`8
`R"
`R"
`R"
`R"
`
`BURST
`TYPE
`
`0
`1
`
`SEQUENTIAL
`INTERLEAVED
`
`)
`
`-- -- --
`
`- -
`
`- ---~ ~-- .__. ·-----·---~ -·----- Ct;---~-GE-LA,.ENCY-- - ··
`000
`R"
`1
`001
`2
`010
`LATENCY 011
`3
`MODE
`(4)
`100
`R"
`101
`R•
`1 1 0
`R"
`1 1 1
`
`NOTE: All items in parentheses are optional
`
`FIGURE 3.11.5-1
`SDRAM MODE REGISTER ARCHITECTURE
`
`Release 4
`
`Jedec 0007793
`
`jx0056-114
`
`114
`
`

`

`3.11.5.4-Power On Sequence (Recommended)
`
`JEDEC Standard No. 21-C
`Page 3. 11.5-9
`
`The synchronous nature of the inputs and outputs of the SDRAM device create the possibility that a SDRAM
`device could power up in a state with data being driven out of the part, and in a multipart system, such a condi(cid:173)
`tion may cause data contention and possibly device damage in the Jong term. In an attempt to reduce the
`possibility of data contention, both system and device designers should strive toward ensuring a High-Z out(cid:173)
`put state during the initial power up sequence. The following recommended power on sequence is ottered
`for both system and device designers as a means to help the device power up with the outputs in a High-Z
`state.
`
`The default power on value for the mode register is supplier specific and may be undefined.
`
`The default power on value for the device is supplier specific and may be undefined.
`
`The recommended power on sequence is as follows: .
`
`1. Apply power and start clock. Attempt to maintain a NOP condition at the inputs
`2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200 µS.
`3; Issue precharge commands for all banks of the device.
`4. Jssue B or more autorefresh commands.
`5. Issue a mode register set command to initialize the mode register.
`
`The device is now in the IDLE state and is ready for normal operation.
`3.11.5.5-Auto Precharge
`The user may specify that the bank currently being accessed precharge itself as soon as the burst is com(cid:173)
`pleted. This is done using address bit A 1 o during the column address cycle. The following table defines the
`options available from A 10 during the column address portion of any cycle.
`
`A10
`
`0
`1
`
`Option
`
`Do not auto precharge, leave bank active at end of burst.
`
`Auto precharge bank specified by A11 at end of burst.
`
`The user must wait until the precharge is completed before issuing another command to the device. Timing
`for auto precharge is required to be the same as or less than the minimum requirement of external precharge.
`
`3.11.5.6-Precharge All Banks
`The user may specify, during a precharge command, whether to precharge only the specified bank or to pre·
`cliarge alrbahks: A1 l is-i:ised to specify the bank1o be precharge, and-A1 o is used to indicate the precharge
`option. The following table defines the options available from A 1 o during the precharge cycle.
`
`A10
`
`0
`1
`
`Option
`
`?recharge bank specified by A 11
`
`Precharge All banks
`
`Release 4
`
`.Jedec 0007794
`-~jx0056-115 J
`
`115
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`JEDEC Standard No. 21-C
`Page 3.11.5-10
`
`3.11.5.7-Mode Register Write Timing
`The Mode Register Set Cycle is initiated by holding the S, RE, CE, and W signals low at the clock rising edge.
`The address lines at the same clock edge contain the mode register set opcode and the valid mode informa(cid:173)
`tion to be written into the mode register. A mode register ;:;et cycle can be followed by a new command in
`no less than 3 clock cycles as illustrated in the diagram below.
`
`s D
`
`I
`
`•
`l!t'E I
`
`I
`
`w
`
`An
`
`+
`
`NOP
`
`Mode Register
`Set Command
`
`All Banks Idle
`
`\
`
`\
`
`•
`
`DI
`i I
`.
`f I
`I
`\
`cp
`
`NOP
`
`"Jew Command can
`occur here or later
`
`)
`
`Note: Clock Low-to-high transitions occur at the dottea lines.
`
`- --- - ----- ---··---------- ---~---- ---·- - ---- --~~--- --~--- ----~---- - -- -- ·-- ··---- -
`
`Release4
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`Jedec 0007795
`
`jx0056-116
`
`116
`
`

`

`3.11.5.8-Auto Refresh
`Auto Refresh is an operation that initiates a single refresh cycle for an SDRAM, but that once initiated, is com(cid:173)
`pleted by internal control in the device with the refresh address being supplied by an internal register in the
`device. Before performing an Autoretresh, all banks of the device must be precharged (IDLE). Autorefresh
`is entered by asserting RE and CE on the same clock cycle. All banks will automatically precharge at the
`end of the refresh cycle. Additional commands must not be supplied to the device during the minimum refresh
`time specified. The following timing diagram illustrates the refresh cycle requirements.
`
`JEDEC Standard No. 21-C
`Page 3.11.5-11
`
`____.n.___,___... c _____ :
`
`I
`I
`
`I
`
`I
`I
`
`r\_J
`:\J_I':I I
`
`C tRc - Supplier Specific Minimum Time
`~
`CJ
`~
`J
`~
`t
`
`n
`
`w
`
`An i i
`
`All Banks
`ld'9
`
`Autorefresh
`Command
`
`t
`
`NOP
`
`NOP
`
`I
`I
`I
`t
`
`t cp '
`
`I
`I
`
`I
`I
`I
`
`t
`
`New Command can occur here
`
`I
`
`I
`I
`
`Note: Clock Low_:to-high transitions occur at ttie aotted lines.
`
`Release 4
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`H - -
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`jx0056-117]
`-
`-
`-
`-
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`Jedec 0007796
`
`117
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`

`

`JEOEC Standard No. 21-C
`Page 3.11.5-12
`
`3.11.5.9-Write Latency
`(Write Latency = 0)
`Write Latency for Synchronous DRAM shall be as defined as the clock cycle difference between the clock
`where write comm