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`USOO5448528A
`
`United States Patent
`
`[191
`
`[11] Patent Number:
`
`5,448,528
`
`Nagai
`
`[45] Date of Patent:
`
`Sep. 5, 1995
`
`[54] SYNC}-IRONOUS DRAM HAVING INITIAL
`MODE SETTING CIRCUIT
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`[75]
`
`Inventor:
`
`Eiichi Nagai, Kawasaki, Japan
`
`[73] Assignee:
`
`Fujitsu Limited, Kawasaki, Japan
`
`[21] Appl. No.: 307,420
`
`[22] Filed:
`
`Sep. 19, 1994
`
`Foreign Application Priority Data
`[30]
`Sep. 21, 1993 [JP]
`Japan .................................. 5—235225
`
`Int. Cl.5 ............................................ .. G1lC 13/00
`[51]
`[52] U.S. Cl. ............................... .. 365/233; 365/225.7;
`365/230.06
`[58] Field of Search ................. 365/233, 230.06, 225.7
`
`5,311,483
`
`5/1994 Takasugi ............................. 365/233
`
`Primary Exanzz'ner—Do H. Yoo
`Attorney, Agent, or Firm—Nikaido, Marmelstein,
`Murray & Oram
`
`[57]
`
`ABSTRACI‘
`
`The initial mode setting circuit 30 has a circuit 31 for
`generating a reset pulse RST after detecting that the
`power source voltage VCC has reached a specified
`value when the power source voltage VCC starts up,
`and fuses 32 to 37, each one end of which is commonly
`connected to the output end of the reset signal generat-
`ing circuit 31 and the other ends of which are connected
`to one of either the set input end S or the reset input end
`R of the flip flops 11 to 13. The fuses 32 to 37 are melted
`and cut off electrically or with a laser.
`
`7 Claims, 4 Drawing Sheets
`
`WRAP
`TYPE
`
`CAS
`LATENCY
`
`1
`
`KINGSTON 1006
`
`KINGSTON 1006
`
`

`
`U.S. Patent
`
`Sep. 5, 1995
`
`Sheet 1 of 4
`
`5,448,528
`
`BURST
`LENGTH
`
`WRAP
`TYPE
`
`CAS
`LATENCY
`
`2
`
`

`
`U.S. Patent
`
`Sep. 5, 1995
`
`Sheet 2 of 4
`
`5
`
`8258’M’
`
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`6mm
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`EmQ;
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`

`
`U.S. Patent
`
`Sep. 5, 1995
`
`Sheet 3 of 4
`
`5,448,528
`
`F!G.3A
`(PRIOR ART)
`
`(4 CLOCKS)
`SETTING
`ACCESSABLE
`MODE
`8 DUMMY CYCLES
`200us
`I<—————>!<————————————>i<————>§———>
`
`VCC /
`
`F|G.3B
`
`ACCESSABLE
`8 DUMMY CYCLES
`200M
`p__—_4
`
`VCC 7:
`
`RST
`CK2
`
`in
`,'
`
`4
`
`

`
`U.S. Patent
`
`Sep. 5, 1995
`
`Sheet 4 of 4
`
`5,448,528
`
`F|G.4
`
`(PRIOR ART)
`
`
`
`BURST
`LENGTH
`
`WRAP
`TYPE
`
`' OAS
`LATENCY
`
`5
`
`

`
`1
`
`5,448,528
`
`SYNCHRONOUS DRAM HAVING INITIAL MODE
`SETTING CIRCUIT
`
`BACKGROUND OF THE INVENTION
`
`5
`
`invention relates to a synchronous
`The present
`DRAM that performs data input/output in sync with a
`clock and that has initial mode setting circuit.
`With the increase in the system clock frequency of 10
`microprocessors, demand has risen for DRAM with
`which high-speed access is possible. In response to this
`demand, synchronous DRAMS have been developed.
`A synchronous DRAM is provided with a mode
`register and by setting the burst length, wrap type and
`CAS latency in the register, optimal operation for the
`system can be achieved.
`The burst length referred to here is the number of
`data that are input/output continuously and it can be set
`to l, 2, 4, 8 or full page. Wrap type refers to the method
`with which column addresses which are internally gen-
`erated are changed at the time of burst access. The
`sequential method, that changes column addresses con-
`tinuously within the same bank, or the interleave
`method, that scrambles column addresses alternately
`between two banks can be selected for the wrap type.
`CAS latency refers to the number of clock cycles that
`pass after the read command is input until the time when
`the first data are read, and a latency of l, 2 or 3 can be
`selected.
`
`20
`
`25
`
`30
`
`15
`
`FIG. 4 is a simplified illustration of a circuit in the
`prior art that is related to mode setting within a syn-
`chronous DRAM.
`
`35
`
`The mode register 10 is provided with 3-bit D flip
`flops 11 to 13. The outputs from the D flip flops 11, 12
`and 13 respectively indicate the burst length, wrap type
`and CAS latency. FIG. 4 is simplified, but in fact, one
`flip flop is provided for each of the 1, 2, 4, 8 and full
`page burst lengths and this applies to other modes.
`Each of the AND gates 21 to 23 is opened by the
`mode register setting signal MRS and their outputs are
`determined by the values of the 7-bit addresses A0 to
`A6. The mode register setting signal MRS is an output
`of the AND gate 25 and it is set to ‘l’ when the chip
`select signal ‘C5, the row address strobe signal *RAS,
`the column address strobe signal *CAS and the write
`enable signal *WE are all set to ‘0’. Generally speaking,
`a signal *S means the signal whose logical value is in
`inverse relation to a signal S.
`In the structure described above, with a program, by
`setting the chip select signal *CS,
`the row address
`strobe signal *RAS, the column address strobe signal
`*CAS and the write enable signal *WE to ‘O’ for the
`synchronous DRAM, and at the same time, by assigning
`specific address values A0 to A6, the appropriate opera-
`tion mode can be set in the mode register 10.
`Generally, a DRAM cannot be accessed immediately
`after the power source voltage VCC starts up, as shown ,
`in FIG. 3A. Namely, after the power source voltage
`VCC reaches a specified value, such as 3.3 Vj-.O.3 V,
`200 ps, i.e., the time that is required for the substrate
`bias circuit within the DRAM to stabilize, is allowed to
`pass. Further, it is necessary to perform dummy opera-
`tions for 8 cycles in order to set the potential of the
`sequential logic circuit to a normal level. In the case of 65
`synchronous DRAM, furthermore, one clock cycle for
`the mode setting described above and three clock cycles
`for awaiting stabilization of the voltage level of the
`
`45
`
`50
`
`S5
`
`6
`
`2
`signal related to the setting are required, so a total of 4
`additional clock cycles is required.
`Because of this, a long time must elapse after power
`up before access is enabled, and it is necessary to set the
`mode with an initialization routine or the like before the
`memory can be accessed after power up.
`SUMMARY OF THE INVENTION
`
`In view of the prior art described above, an object of
`the present
`invention is to provide a synchronous
`DRAM which can reduce the length of time that elap-
`ses after power up until access is enabled and which can
`eliminate initial mode setting using a program.
`According to the present invention, there is provided
`a synchronous DRAM performing data input or output
`operation synchronized with a clock input in one of
`operating modes, the mode being set in a mode register,
`comprising: a command decoder for decoding a control
`signal from outside to generate a mode register setting
`signal and for, when said mode register setting signal is
`active, decoding an memory address to set the operat-
`ing mode in the mode register; and a initial mode setting
`circuit for generating a reset signal after detecting that
`a power source voltage has reached a value after start
`up of said power source voltage and for setting an initial
`value of the operating mode in said mode register with
`timing of said reset signal.
`Since the operating mode that the user normally uses
`or that the user requests can be initially set in the mode
`register automatically in response to the reset signal that
`is generated at power up, access becomes possible after,
`for example, 8 dummy cycles. This means, as shown in
`FIG. 3B for exampleythat access is possible by four
`clock cycles sooner than in the prior art, just as with
`non-synchronous type DRAM.
`Also, it is not necessary to set initial mode in an ini-
`tialization routine or the like.
`In the first mode of the present invention, said mode
`register has flip flops, each of said flip flops has a set
`input end and a reset input end; said initial mode setting
`circuit comprises; a reset signal generating circuit for
`generating a reset pulse from an output end after detect-
`ing that said power source voltage has reached a value
`when said power source voltage starts up; and non-
`volatile switching elements, one end of each of which
`being commonly connected to said output end of said
`reset signal generating circuit and another end of each
`of which being connected to one of either said set input
`end or said reset input end of one or more of said flip
`flops
`By this first mode, It becomes possible to set an initial
`value for the operating mode easily in correspondence
`with the system being used by the synchronous DRAM
`user.
`
`In the second mode of the present invention, said flip
`flops are N number; and said non-volatile switching
`elements are 2N number, one end of each of which
`being commonly connected to said output end of said
`reset signal generating circuit and other ends of which
`being connected to said set input ends or said reset input
`ends of said flip flops respectively.
`This second mode simplifies the structure.
`In the third mode of the present invention, said non-
`volatile switching elements are fuses cut off or not in
`accordance with said initial mode.
`This third mode makes possible to set various initial
`mode by melting and cut off electrically or with a laser
`in accordance with user’s request.
`
`

`
`5,448,528
`
`3
`In the forth mode of the present invention, said non-
`volatile switching elements are wiring pattern having
`connection/disconnection between said ends in accor-
`dance with said initial mode.
`This third mode simplifies the structure.
`As other mode, each of said non-volatile switching
`elements comprises a switching transistor connected
`between said output end of said reset signal generating
`circuit and said set input end or said reset input end of
`one of said flip flops.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 shows a circuit that is related to mode setting
`within the synchronous DRAM in an embodiment of
`the present invention;
`FIG. 2 is a block diagram showing the overall config-
`uration of a synchronous DRAM that includes the cir-
`cuit shown in FIG. 1;
`FIG. 3A is a waveform diagram of the process lead-
`ing to the time when access is enabled in the prior art;
`FIG. 3B is a waveform diagram of the process lead-
`ing to the time when access is enabled in an embodiment
`of the present invention; and
`FIG. 4 shows a circuit that is related to mode setting
`within the synchronous DRAM in the prior art.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`
`FIG. 2 shows an overall configuration of the syn-
`chronous DRAM.
`
`30
`
`5
`
`l0
`
`15
`
`20
`
`25
`
`35
`
`45
`
`50
`
`55
`
`4
`setting of the mode, that is normally used in the system,
`in the mode register 10 at the time of power up.
`As shown in FIG. 1, the initial mode setting circuit 30
`is provided with a reset signal generating circuit 31 that
`generates a one-pulse reset signal RST that is output at
`start up after detecting that the power source voltage
`VCC has reached a specified value in the range of, for
`example, 3.3 ViO.3 V and non-volatile switching ele-
`ments 32 to 37, one end of each being connected com-
`monly to the output end of the aforesaid reset signal
`generating circuit 31 and the other ends being con-
`nected to the set input ends and the reset input ends of
`the D flip flops 11, 12 and 13 respectively.
`The non-volatile switching elements 32 to 37 may be
`fuses that can be melted and cut off electrically or with
`laser or they may be a wiring pattern in which connec-
`tion/disconnection can be selected at layout design.
`Either one of 32 or 33, either one of 34 or 35 and either
`one of 36 or 37 of the non-volatile switching elements
`32 to 37 are fused or disconnected depending upon the
`operating mode that is normally used by the user or
`requested by the user. In FIG. 1,
`the non-volatile
`switching elements 33, 35, and 37 are set to ON and the
`non-volatile switching elements 32, 34, 36 are set to
`OFF.
`
`The clock CK is supplied from the clock buffer 46
`shown in FIG. 2 to clock input ends of D flip flops 11
`to 13 when setting is made in the mode register 10 with
`a program as in the prior art.
`The other aspects of FIG. 1 are identical to those in
`FIG. 4.
`Next, the operation of the embodiment structured as
`described above is explained.
`In FIGS. 1 and 3B when the power source voltage
`VCC is started at power up and reaches a specified
`value in the range such as 3 Vi0.3 V, a reset signal
`RST is output from the reset signal generating circuit
`31, which then is supplied to the reset input end of the
`D flip flops 11 to 13 of the mode register 10 to clear the
`contents of D flip flops 11 to 13 to 0. With this, the burst
`length, the wrap type and the CAS latency that are
`normally used by the user or which are requested by the
`user are initially set.
`Since the 8 dummy clock cycles and 200 its shown in
`FIG. 3B relate to a memory cell array, normal access
`cannot be made to the memory cell array while the
`dummy cycles are running. However, since the setting
`in the mode register 10 does not constitute an access to
`the memory cell array, mode setting can be made imme-
`diately after the power source voltage VCC starts up as
`described above.
`
`With the present embodiment, since the operating
`mode that the user normally uses or the user requests is
`initially set in the mode register automatically in re-
`sponse to the reset signal RST that is generated with
`power up, access becomes possible after 8 dummy clock
`cycles just as with non-synchronous DRAM. This
`means that access is possible sooner by four clock cycles
`compared to the prior art. Also, it is not necessary to
`perform initial mode setting in an initialization routine
`or the like.
`
`This synchronous DRAM is provided with the
`DRAM core 40 of bank 0 and the DRAM core 41 of
`bank 1. The addresses A0 to All are supplied to the
`row address input ends RADR of the DRAM cores 40
`and 41 via the address buffer 42. When the address bit
`A11 is set to ‘0’, the DRAM core 40 is selected and
`when the address bit All is set to ‘l’, the DRAM core 41
`is selected. The addresses A0 to All that are supplied
`next are held in the column address counters 43 and 44
`via the address buffer 42 and their contents are supplied
`to the column address input ends CADR of the DRAM
`cores 40 and 41. The contents of the column address
`counters 43 and 44 are counted up during a burst trans-
`fer in correspondence with the mode set in the mode
`register 10. Input/output of the data D0 to D7 for the
`data input/output ends I/O of the DRAM cores 40 and
`41 is performed through the input/output data buffer
`register 45. The control of data input/output is exe-
`cuted, in sync with the clock CLK supplied to the clock
`buffer 46, based upon the chip select signal *CS, the
`row address strobe signal *RAS, the column address
`strobe signal *CAS and the write enable signal *WE
`that are supplied to the command decoder 20.
`If any of the chip select signal *CS, the row address
`strobe signal *RAS, the column address strobe signal
`CAS or the write enable signal *WE are not set to ‘0’,
`they are held in the control signal latch circuit 47 and 48
`by the clock from the clock buffer 46 and they are then
`supplied to the row address strobe signal input end
`RAS, the column address strobe signal input end CAS
`and the write enable signal input end WE of the DRAM
`cores 40 and 41. The clock CLK becomes validated in
`the clock buffer 46 when the clock enable signal CKE is
`set to ‘1’.
`In addition to the structure of the known art de-
`scribed above, this embodiment is further provided with
`the initial mode setting circuit 30 that performs initial
`
`Having described specific embodiment of the present
`invention, it is to be understood that modification and
`variation of the invention are possible without depart-
`ing from the spirit and scope thereof.
`What is claimed is:
`
`65
`
`1. A synchronous DRAM performing data input or
`output operation synchronized with a clock input in one
`
`7
`
`

`
`5
`of operating modes, the mode being set in a mode regis-
`ter, comprising:
`a command decoder for decoding a control signal
`from outside to generate a mode register setting
`signal and for, when said mode register setting 5
`signal is active, decoding a memory address to set
`the operating mode in the mode register; and
`an initial mode setting circuit for generating a reset
`signal after detecting that a power source voltage
`has reached a value after start up of said power 10
`source voltage and for setting an initial value of the
`operating mode in said mode register with timing
`of said reset signal.
`2. A synchronous DRAM according to claim 1:
`wherein said mode register has flip flops, each of said
`flip flops has a set input end and a reset input end;
`wherein said initial mode setting circuit comprises;
`a reset signal generating circuit for generating a reset
`pulse from an output end after detecting that said
`power source voltage has reached a value when 20
`said power source voltage starts up; and
`non-volatile switching elements, one end of each of
`which being commonly connected to said output
`end of said reset signal generating circuit and an-
`other end of each of which being connected to one 25
`of either said set input end or said reset input end of
`one or more of said flip flops.
`3. A synchronous DRAM according to claim 2
`wherein said on-volatile switching elements are fuses
`
`15
`
`6
`cut off or not in accordance with said initial value of the
`operating mode.
`4. A synchronous DRAM according to claim 2
`wherein said non—volatile switching elements are wiring
`patterns having connection/disconnection between said
`output end of said reset signal generating circuit and
`said one of either said set input end or said reset input
`end of one or more of said flip flops in accordance with
`said initial value of the operating mode.
`5. A synchronous DRAM according to claim 2:
`wherein said flip flops are N number; and
`wherein said non—volatile switching elements are 2N
`number, one end of each of which being commonly
`connected to said output end of said reset signal
`generating circuit and other ends of which being
`connected to said set input ends or said reset input
`ends of said flip flops respectively.
`6. A synchronous DRAM according to claim 5,
`wherein said non—volatile switching elements are fuses
`cut off or not in accordance with said initial value of the
`operating mode.
`7. A synchronous DRAM according to claim 5
`wherein said non-volatile switching elements are wiring
`patterns having connection/disconnection between said
`output end of said reset signal generating circuit and
`said one of either said set input end or said reset input
`end of one or more of said flip flops in accordance with
`said initial value of the operating mode.
`*
`*
`=l<
`*
`*
`
`5,448,528
`
`30
`
`35
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`45
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`50
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`55
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`60
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`65
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`8