O
`112; United States Patent
`Merritt
`
`I|||||||||||||||||l|||||||||||||||||l|||l|||l|||||||||||l|||||||||||||||Il|
`
`USU0624-379':’B1
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,243,797 B1
`*Jun. 5, 2001
`
`OTHER PUBLICATIONS
`‘
`‘
`_
`”
`_
`“Mlcron 4 Meg X 412 Meg X 8 SDRAM , Micron .S_vrtc1’tro-
`nous DRAMDarr1 Book, Micron Technology, [ne., pp. 1-14,
`(Rev Fell 1997)-
`"Wav'e—pipelining: Is it Practical?"',1'994 IEEE Inremariortal
`.Stmpo.st'un1 on Cireztmt and S}-‘.5'IetttS_. vol. 4 of 6 VLSI, pp.
`163, (164 is blank, not included and 165-166, (May 3U'—Jun.
`2. 1994).
`
`(List continued on next pagan}
`
`Primary E.camr'r1er—John W. Cabcca
`Assistant Examim.=1'—Matthcw D. Anderson
`(74) Attomcy, Agent, or Ft'rm—Schwegman, Lundberg,
`wocsgncr & K_]mh’ p_A_
`
`(57)
`
`ABSTRACT
`
`A multiplexing arrangement for transferring data retrieved
`from a memory array to data outputs of a semiconductor
`memory, incltrding H rnultiplexing circuit that is responsive
`to latency select signals to cause data retrieved sequentially
`from the memory array to be loaded into and read from data
`latch circuits of a data output register in a sequence that
`establishes a known delay between the time that data is
`retrieved from the memory array and stored in the data
`output register and the time that the data is read from the data
`output register. The delay allows data to be held in the data
`output register when the data is available and to be passed
`to the data outputs of the memory when desired. Also
`described is a multi-phase timing signal generator that
`includes a multistage shift register eonnected for operation
`as a recirculating shift register, a drive circuit responsive to
`system clock pulses for advancing a bit pattern through the
`shift register, and an output eircu it for logically combining
`signals provided at outputs of the shift register as the hit
`pattem is advanced through the shift register to produce
`.
`.
`.
`.
`‘°'4”°"i”" t""'"3 '°"*‘=’*”"""
`
`21} Claims. 7 Drawing Sheets
`
`(54) MULTIPLEXED SEMICONDUCTOR DATA
`TRANSFER ARRANGEMENT WITH TIMING
`SIGNAL GENERATOR
`
`{as}
`
`(73)
`
`Inventor: Todd A. Merritt, Boise. ID (US)
`_
`I
`_
`A-3513:0337 Mlcmn T'3‘~"1|1'U8!'s [W3-s B01-5*'=» [D
`(US)
`
`{*) Notice:
`
`This patent issued on a continued pros-
`ecution application filed under 37 CFR
`1.53{d}, and is subject to the twenty year
`Pmlll
`‘elm P1'°Vi5i011‘3 Of 35 U-SC
`1541311 31-
`_
`_
`_
`_
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C.‘. 15411-1) by 0 days.
`
`(21) Appl. No.: os1sm,11s1
`
`Filed:
`
`Feb. 13, 1997
`
`(23
`?
`_
`[me CL
`1311
` (52) U.S.Cl.
`
`_
`GWIF 12190
`7111167; 7113169; 711.-“I57;
`711.1100; 7111168
`3651233, 230.03,
`(58) Field of Search
`3651"189.12, 711.1104, 167, 100, 101, 102,
`105, 111, 151], 154, 157, 168, 169
`
`(56)
`
`References Cited
`
`US‘ PATENT DOCUMENTS
`4,961,169 * 10.119911 Marsumum el al.
`4,985,643
`1.1199] Proeh-sting
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`5’34q>5f"c’
`9-"994 Mem“ '9' “I
`5334350 ==
`111995 Lee
`$430,537 ~
`711995 Hung et at.
`5,544,124 *
`8.31996 ?.aga1'eln|.
`5,587,961 ~ 12.11996 Wright ct at.
`
`
`
`3eSt189.12
`3{I?_trt-'13
`711.-’ 157
`39594-35
`3'c’5-£2335
`355.1233
`.. 36$/23(I.U8
`.. 3t':5f23l'.|'.l']8
`355.1233
`
`20
`OLl'|'F'UT
`Itl'|"PX
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`?—.—ono11
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`32
`Dtlfl-In-0tJT
`REGISTER
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`DATA-IN
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`1
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`KINGSTON 1005
`
`KINGSTON 1005
`
`

`
`US 6,243,797 B1
`Page 2
`
`OTHER PUBLICATIONS
`
`Fujiwara, el al,, "A 200MHz 16Mbi1 Synchronous DRAM
`with Block Access M0de”,J994 .S‘ymp-asium on VLSI Cir-
`c1¢i!$—D£geS£ of Teclmical _Papers,
`IEEE Cat. No.
`94-Ch3-134-8, pp. 79-30. (Jun. 9-11, 1994).
`
`Takai, et a]., “250 MIT:-yte,-‘sec Synchronous DRAM Using a
`3—Stage—Pipelined ArchEtoe:rure”,i'993 Sym,r)os£um rm VLSI
`C£rcw’rs—Digesr of1"e'chm’caIPaper, [BEE Cat. No. 93 (Ill
`3304-3, pp. 59-60, (May 19-21, 1993).
`
`Wong, et al., “A Bipolar Population Counter Using Wave
`Pipelining to Achieve 25:: Normal Clock Frequency”.I992
`IEEE Imerrsarfonaf SoI:'d—S.'a'Ie Cimuirs Conference—Dri—
`gas! of Tecimical Papers, First E.dition—lEEE Cat. No.
`92CH3128—IS, pp. 56-57, (Feb, 1992).
`You, at al., "A 150MHz 8—Banks 256M Synchronous
`DRAM with Wave Pipelining Met]:ocls“,1C-'95 IEEE lm‘er-
`nrrrionrr! SohT:i—Sm.-‘e C:‘rcm’Is- Coriference, lSSCC95,?Sessinn
`l4—Paper FA 14.4, pp. 250, (1995).
`* cited by examiner
`
`2
`
`

`
`U.S. Patent
`
`Jun. 5, 2001
`
`Sheet 1 of 7
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`US 6,243,797 B1
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`U.S. Patent
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`Jun. 5, 2001
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`US 6,243,797 B1
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`Jun. 5, 2001
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`US 6,243,797 B1
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`US 6,243,797 B1
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`US 6,243,797 B1
`
`1
`MULTIPLEXED SEMICONDUCTOR DATA
`TRANSFER ARRANGEMENT WITH TIMING
`SIGNAL GENERATOR
`
`FIEID OF THE INVENTION
`
`The present invention relates to semiconductor memory
`devices, and in particular, the invention relates to a multi-
`plexed data transfer system and method for controlling the
`transfer of data from a memory array to the data outputs of
`an integrated circuit memory device, and for providing
`programmable latency control in the data transfer operation.
`BACKGROUND OF THE INVENTION
`
`l-TJ
`
`2
`there is a need in the art for a multiplexed data transfer
`system and method for controlling the transfer of data
`retrieved from a memory array to data outputs of a semi-
`conductor memory and for providing programmable latency
`control in the data transfer operation.
`SUMMARY OF THE INVENTION
`
`The present invention provides a multiplexing arrange-
`ment for controlling the transfer of data retrieved from a
`memory array of a semiconductor memory to data outputs of
`the semiconductor memory and for providing programmable
`latency control in the data transfer operation. The multiple 3:-
`ing arrangement comprises a data output register which
`includes a plurality of data storage circuits for storing data
`that is retrieved from the memory array. A multiplexing
`circuit is responsive to timing signals produced by a timing
`signal generator to load data that
`is retrieved from the
`memory array into the data storage circuits of the data output
`register. The timing signals are also used to read the data
`from the data storage circuits of the data output register for
`passing the data from the data output register to the data
`outputs of the semiconductor memory. The multiplexing
`circuit responds to the timing signals and to a latency select
`signal to load the data into the data storage circuits in a
`sequence that estabtishes a known delay between the time
`that the data is retrieved from the memory array, and stored
`in the data output register, and the time that data stored in the
`data output register is passed to the data outputs. The delay
`allows data to be held in the data output register when the
`data is available and to be passed to the data outputs of the
`semiconductor memory when desired.
`In accordance with another aspect of the invention, there
`is provided a multi-phase liming signal generator which is
`characterized by fast speed. The timing signal generator
`comprises a multi-stage shift register connected for opera-
`tion as a recirculating shift register. The shift register stages
`store a predetermined bit pattern and a drive circuit, respon-
`sive to system clock pulses, advances the bit pattern through
`the shift register. An output circuit logically combines the
`signals provided on signal outputs of the shift register stages
`as the bit pattem is advanced through the shift register to
`produce a sequence of tinting signals. In one embodiment,
`the drive circuit comprises a pair of two-stage drive shift
`registers storing complementary bits which change in state
`in response to system clock pulses, for producing comple-
`mentary bit pattern advance signals for the multi-stage shift
`register. This arrangement produces complementary drive
`signals without the need for inverters, and thus eliminates
`the delay introduced by inverters.
`for
`The timing signal generator is particularly useful
`Iatency control
`in the transfer of data retrieved from a
`memory array of a semiconductor memory to data outputs of
`the semiconductor memory. In such application, the timing
`signal generator inctudes a latency control circuit which
`delays the response of the timing signal generator by cite
`system clock pulse to provide a clock latency of one for the
`data transfer arrangement.
`
`BRIEF DESCRIPIION OF THE DRAWINGS
`
`FIG. 1 is a functional block diagram of a synchronous
`dynamic random access memory incorporating a multi-
`phase timing signal generator and a data output multiplexing
`control circuit provided by the invention;
`FIG. 2 is a block diagram of a multi-phase timing signal
`generator and a data output multiplexing control circuit
`provided by the invention, and which form a portion of the
`
`15
`
`25
`
`As microprocessors have become faster, a need has devel-
`oped for speeding up memory usage. Various arrangements
`have been proposed for reducing access time for semicon-
`ductor memory devices, such as synchronous dynamic ran-
`dom access tnemory devices. One of the most common
`approaches for speeding up memory usage is through the use
`ofpipe lining arrangements. In pipelining arrangements, data
`that is read out of a memory is temporarily held in data
`registers interposed in the data path between the memory
`array and output bulfers of the inputioutput circuits of the
`memory system until needed, allowing the memory to be
`accessed to read out other data. Many known pipelining
`arrangements require clocked storage elements in the
`address buffer, the column switch and in the data output path
`to maintain synchronization between the data and the sys-
`tem. The need for these clocked storage elements places a
`restriction on the clock frequency of the system clock.
`A further consideration is that pipelining arrangements
`require internal clock pulses for controlling the sequencing
`of the data transfer operations. In many instances such
`internal timing signals are derived from the system clock,
`typically using counter circuits. The counter circuits divide
`the system clock pulses to produce a series of internal clock
`pulses having a predetermined relation to the clock pulse.
`However,
`the timing signals that are produced using a
`counter circuit have an inherent skew because the system
`clock pulses must
`ripple through several stages of the
`counter circuit
`in producing the internal clock pulses.
`Moreover, in producing a multi-phase irttemal clock signal
`using counter circuits, the output of the counter circuits must
`be sampled to detect a 1—1 state followed by activation of
`the reset input of the counter circuit. This results in a time
`delay and further skews the output signal provided by the
`counter circuit based internal clock pulse generator. Other
`clock pulse generating circuits employ inverter circuits for
`producing sequenced clock pulses. However,
`the inverter
`circuits introduce delays that must be compensated for to
`avoid speed loss.
`A synchronous dynamic random access memory employ-
`ing wave pipelining methods is disclosed in an Article
`J:‘J:
`entitled "A 150 MHz 8-Banks 256M Synchronous DRAM _
`with Wave Pipelinirtg Methods” by Hoi-Jun Yoo, et. at,
`which appeared in the 1995 IEEE International Solid State
`Circuits Conference, Digest of Technical Papers, pages 250,
`251 and 374, Feb. 17, 1995. The memory includes steering
`circuitry in the data path which transfers data to and from the
`data output registers according to external latency program-
`ming. However, this arrangement rcquires separate clock
`signals for data reception from the pipelining path and for
`data transfer to the output driver.
`For the reasons stated above, and for other reasons stated
`below which will become apparent to those skilled in the art
`upon reading and understanding the present specification,
`
`39
`
`35
`
`60
`
`10
`10
`
`

`
`US 6,243,797 B1
`
`3
`inputfoutput circuits of the synchronous dynamic random
`access memory of FIG. 1;
`FIG. 3 is a block diagram of the multi-phase timing signal
`generator provided by the invention;
`FIG. 4 is a schematic representation of the multi-phase
`timing signal generator of FIG. 3;
`FIG. 5 is a timing diagram showing the relationship
`between system clock pulse and the timing signals provided
`by the multi-phase timing signal generator of FIG. 4;
`FIG. 6 is a schematic representation of the data output
`multiplexitlg control circuit provided by the invention; and
`FIG. 7 is a timing diagram showing the relationship
`between the memory system clock pulses and the availabil-
`ity of the data bits for three levels oflatency provided by the
`data output multiplexing control circuit provided by the
`invention.
`
`DlLS(;'RIl"l‘lON 01''" Till: Pl{l."l-‘l£l{RI-.*"D
`EMBODIMENI‘
`
`In the following detailed description of the preferred
`embodiment, reference is made to the accompanying draw-
`ings which form a part hereol’, and in which is sh own by way
`of illustration a specific preferred embodiment in which the
`invention may be practiced. The preferred embodiment is
`described in sufficient detail to enable those skilled in the art
`
`to practice the invention, and it is to be understood that other
`embodiments may be utilized and that logical and electrical
`changes may be made without departing from the spirit and
`scope of the present
`invention. The following detailed
`description is, therefore, not to be taken in a limiting sense,
`and the scope of the present invention is defined only by the
`appended claims.
`FIG.
`1
`is a functional block diagram of a synchronous
`dynamic random access memory (SDRAM) 10 incorporat-
`ing the data output multiplexing arrangement provided by
`the invention. In the exemplary embodiment, the SDRAM
`organized as a dual
`1 Meg><8 memory and includes a
`synchronous interface. Each of the 1 Meg><8 bit banks is
`organized as 2048 rows by 512 columns by eight bi ts. Much
`of the circuitry of the SDRAM 10 is similar to circuitry in
`known SDRAMS, such as the MT4-SLCZMSA1 S 2 Megx8
`SDRAM which is commerciaily available from Micron
`Technology, Inc. Boise Id., 83707, and which is described in
`detail in the corresponding Micron Technology, Inc. Func-
`tional Specification which is incorporated herein by refer-
`ence.
`
`1-71
`
`15
`
`25
`
`39
`
`35
`
`SDRAM 10 includes a bank I} memory array 22 and a
`bank 1 memory array 24 which both comprise storage cells
`organired in rows and columns for storing data.
`In one
`embodiment of SDRAM 10, each bank memory array com-
`prises eight separate arrays of 2048 rows>:512 columns.
`A system clock (CLK) signal is provided through a CLK
`J:‘J:
`input pin and a clock enable signal (CKE) is provided _
`through a CKE input pin to SDRAM it}. The CLK signal is
`activated and deactivated based on the state of the CKE
`
`signal. All the input and output signals of SDRAM II], with
`the exception of the CKE input signal during power down
`and self refresh modes, are synchronized to the active going
`edge (the positive going edge in the embodiment illustrated
`in FIG. 1) of the CLK signal.
`A chip select (CS*) input pin inputs a C‘S* signal which
`enables, when low, and disables, when high a command
`decoder 26. Command decoder 26 is included in control
`
`60
`
`4
`pin, column address strobe (C‘AS*) signal on :1 {.‘AS* pin,
`and a write enable (WE*) signal on a WE‘ pin. Command
`decoder 26 decodes the RAS*, CAS*, and WE* signals to
`place control logic 28 in a particular command operation
`sequence. Control logic 28 controls the various circuitry of
`SDRAM 10 based on decoded commands such as during
`controlled reads or writes from or to bank 0 memory array
`22 and bank 1 memory array 24. Abank address (BA) signal
`is provided on a BA input pin to define which bank memory
`array should be operated on by certain commands issued by
`control logic 28.
`Address inputs bits are provided on input pins A0—A1l}.
`As described below, both the row and column address input
`bits are provided on the address input pins. During write
`transfer operations, data is supplied to SDRAM 10 via
`inputtolltput pins (DQl]—DQ7}. During read transfer
`operations, data is clocked out of SDRAM 10 via inputs’
`output pins D'00—DQ7. An inputfoutput mask signal
`is
`provided on a DQM input pin to provide control for a data
`input register 3|} and El data output register 32.
`Power-up and initialization functions of the SDRAM II]
`are conducted in the conventional manner. Moreover,
`refresh functions of the SDRAM 10 are provided in the
`known manner employing a refresh controller 34 and a
`refresh counter 38 to refresh the memory arrays.
`Avalid ACTIVE command is initiated by control logic 28
`with the CS* and RAS* signals low and with the CAS* and
`WE‘ signals high on a rising edge of the CLK signal. "During
`the ACTIVE command the state of the BA signal determines
`which bank memory array to activate and address. During
`the ACTIVE command, a value representing a row address
`of the selected bank memory array, as indicated by address
`bits on input pins A0—Al0, is latched in a row address latch
`42. The latched row address is provided to a row multiplexer
`46 which provides a row address to row address latch 48 to
`be provided to bank 0 memory array 22 or row address latch
`50 to be provided to bank 1 memory array 24, depending on
`the state of the BA signal. Arow decoder 52 decodes the row
`address provided from row address latch 48 to activate one
`of the 2,048 lines corresponding to the now address for read
`or write transfer operations, to thereby activate the corre-
`sponding row of storage cells in bank 0 memory array 22.
`Row decoder 54 similarly decodes the row address in row
`address latch 50 to activate one of the 2,048 lines to bank 1
`memory array 24 corresponding to the row address for read
`or write transfer operations, to thereby activate the corre-
`sponding row of storage cells in bank 1 memory array 24.
`A valid READ command is initiated with the ('.‘S* and
`CA3‘ signals low, and the RAS* and WE* signals high on
`a rising edge of the CLK signal. The READ command from
`control logic 28 controls a column address latch 56 which
`receives address bits Al)—A9 and holds a value representing
`a column address of the bank memory array selected by the
`BA signal at
`the time the READ command is initiated.
`Address pin All} provides an input path for a command
`signal which determines whether or not an AUTO-
`PRECHARGE command is to be initiated automatically
`after the READ command as is known in the art. The READ
`command provided from control logic 28 also initiates a
`burst read cycle by starting a burst counter 60 in the manner
`known in the art.
`
`A column address butler 62 receives the output oi‘ the
`burst counter 60 to provide the current count of the column
`‘ address to a column decoder 64. Column decoder 64 acti-
`
`logic 23. Command decoder 26 receives control signals
`including a row address strobe (l1AS“) signal on a RAS*
`
`vates eight of the 512><8 lines, provided to sense amplifiers
`and inputroutput (U0) gating circuit 66 and sense amplifiers
`
`11
`11
`
`

`
`US 6,243,797 B1
`
`5
`and 1.50 gating circuit 68 corresponding to the current
`column address. Sense amplifiers and IE0 gating circuits 66
`and 68 operate in a manner known in the art to sense the data
`stored in the storage cells addressed by the active row
`decoder line and the active column decoder lines to provide
`the selected eight bit byte of data from either bank!) memory
`array 22 or bank 1 memory array 24 respectively to data
`output register 32 during :1 read operation. Data output
`register 32 provides the selected eight bit byte of data to
`in putfoutput data outputs at pins DQO—DQ7.
`A valid WRITE cotnmand is initiated with the CS*,
`CAS*, and WE" signals low and the RAS* signal high on
`the rising edge of the CLK signal. The WRITE command
`provided from command controller 28 clocks column
`address latch 56 to receive and hold a value representing a
`column address of the bank memory array selected by the
`state of the BA signal at the time the WRITE command is
`initiated, as indicated by the address provided on address
`input pins A0-A9. As with the read operation, during the
`WRITE command, address pin A10 provides the additional
`feature to select whether or not the AU'I‘{')-I’l{L-;Cl-IARGII
`command is to be initiated following the WRITE command.
`Burst counter 60 initiates the burst write cycle. Column
`address buffer 62 receives the output of the burst counter 60
`and provides the current column address to column decoder
`64. Column decoder 64 activates eight of the 5l_2><8 lines to
`sense amplifiers and IIO gating circuits 66 and 68 corre-
`sponding to the column address to indicate where the
`incoming eight bit byte of data is to be stored in either bank
`0 memory array 22 or bank 1 memory array 24.
`During WRl'l‘l':‘ command operations, data is provided on
`inputtoutput pins DQO—DQ3 to data—in register 30. The eight
`bit byte of input write data is provided to the selected bank
`memory array with sense amplifiers and Ia'Ct gating circuits
`66 or 68 in a manner known in the art based on the activated
`eight lines corresponding to the current column address.
`In accordance with the invention, the transfer of the data
`read out of the memory arrays 22 and 24 to the data outputs
`D'Q0—-DQ7 through the data output register 32 is controlled
`by data output multiplexer 20. As will be described, the data
`output multiplexer 20 provides programmable latency con-
`trol in data transfer operations.
`The data that is read from the SDRAM can be latched
`
`l-TJ
`
`15
`
`25
`
`39
`
`35
`
`6
`conductor SDRAM. as is known in the art. The mode
`register 40 latches the state of one or more of the address
`input signals A0—A9, or data signals DQO—DQ7, upon
`receipt of a write-CAS*-before-R.=\S* (WCBR) program-
`ming cycle. In the exemplary embodiment, latency control
`outputs CL2 and CL3 provided by the mode register 40 are
`used to control
`the required circuits of the SDRAM.
`Moreover, the data output multiplexing circuits provide an
`inherent clock latency of one and are prograntrnable to
`provide a clock latency of two or a clock latency of three.
`This basic implernentation requires very little additional
`circuitry to the standard SDRAM.
`Output Logic
`FIG. 2 is a block diagram of a portion of the output logic
`and latches 32 of the SDRAM 10 of l"lG. 1, and illustrates
`a multi—phasc timing signal generator 210 and a data output
`multiplexing control circuit 220 of the data output multi-
`plexer 21} provided by the invent ion, and data output register
`circuits 230 and 240 of the data output register of the
`SDRAM. In the exemplary embodiment, the timing signal
`generator 210 produces a three-phase timing signal.
`However,
`the timing signal generator can be adapted to
`provide more or less than three timing signals, as a function
`of application.
`The three-phase timing signal generator 210 and the data
`output multiplexing control circuit 220 control the transfer
`of data read out ofthe arrays 22 and 24 and placed on data
`lines DATA1—DATAB (and DATAl"‘—DATA3*} to respec-
`tive data outputs DQO—DQ7. The data is temporarily stored
`in the data output registers prior to transfer to the data
`outputs. A separate data output register circuit is individually
`associated with each ofthe eight data line pairs of the read
`data bus. FIG. 2 illustrates data output register circuits 230
`and 240 which receive the data read out onto read data line
`pair DAIA1 and DAl'2\l*. and read data line pair DAYAS
`and DAl'Al'l*, respectively. Each of the data output register
`circuits, such as data output register circuit 230, includes
`three data storage circuits, embodied as latch circuits 231,
`232 and 233 the outputs of which are commonly connected
`to data output DQO. Similarly, the other seven data output
`register circuits, such as data output register circuit 240
`shown in FIG. 2, also include three data latch circuits which
`have outputs commonly connected to data outputs
`I)Ql—I)C_t7, such as data output DQ7 for data output register
`circuit 240.
`
`external to the SDRAM in synchronization with the signal
`CLK after a predetermined number of CLK cycle delays.
`This delay arrangement is commonly referred to as clock
`latency. Once the SDRAM 10 begins to output data in a read
`cycle,
`the output drivers will continue to drive the data
`outputs DQl]—DQ7 without tri-stating the data outputs dur-
`ing CII._K high intervals dependent upon the state of the chip
`select signal (CS’‘) and the write enable signal (WE*), thus
`allowing additionai time for the memory system to latch the
`output data.
`J:‘J:
`The SDRAM requires a full clock cycle (high and low ‘
`transitions) for each memory cycle. In the read cycle, the
`data that is read out of the one of the memory arrays 22 and
`24 is latched into the data output register 32 and is read out
`stthsequently with each rising edge of each clock pulse CLK
`after the first CLK latency.
`Prograrnrznability of operating parameters of the synchro-
`nous dynamic random access memory, such as burst length,
`burst type, read latency, operating mode and a write burst
`mode, is accomplished through the use of a mode register 40
`associated with control logic 28 (FIG. 1). The user selects
`the mode register 40 command to select operating
`parameters, such as burst length or latency, for the semi-
`
`60
`
`Each of the latch circuits, such as latch circuit 231, can
`comprise a pair of latch circuits, for receiving the comple-
`mentary signals on read data lines DATA1 and DATA1*,
`with the outputs of such paired latch circuits being applied
`to an output driver circuit (not shown) to produce output
`DQI}. This arrangement allows tri-stating of the output
`driver, as is known in the art. Alternatively, where such
`feature is not required, only the true state DATAI can be
`applied to the latch circuits 231-233, in which case, the latch
`circuits 231-233 can each comprise a singie latch circuit.
`The three-phase timing signal generator 210 derives from
`the system clock CLK three-phase timing signals Enl, En2
`and En3 which are used to control
`the translier of data
`through the data output register circuits, such as data output
`register circuits 230 and 240. of the [£0 logic and latch
`ci.rcuits 30 of the semiconductor SDRAM 10. The three-
`phase timing signals control both the latching of the data into
`the data output register 32 and the application of the latched
`- data to the data outputs DQO—DQ7.
`As will be shown, the data output multiplexing control
`circuit 220 controls the enabling of the data latch circuits of
`
`12
`12
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`US 6,243,797 B1
`
`7
`the data output register circuits as a function of the latency
`setting for the arrangement. The data multiplexing arrange-
`ment inherently provides a clock latency of one clock cycle
`as a result of the latency control circuit of the timing signal
`generator as will be described. However,
`the data output
`multiplexing control circuit are programmable to provide a
`clock latency of two, or at clock latency of three, as a
`function of application. A clock latency of two is set hy
`activating signal CL2 using the general mode register 40
`(FIG. 1). Aclock latency of three is set by activating signal
`Cl_3 using the general mode register 40. If neither signal
`CL2 or C13 is activated,
`the data output multiplexing
`control circuit provide a clock latency of one.
`Timing Signal Generator
`Referring to FIG. 3, the three-phase timing signal gen-
`erator 210 includes a reset circuit 302, a latency control
`circuit 304, a multiplexer and output driver circuit 306, a
`shift register 308 and an output circuit 310. The timing
`signals produced by the three-phase timing signal generator
`are used in controlling the data output multiplexing control
`circuit 220 (FIG. 2) in loading data into the data output
`register circuits, such as data output register circuits 230 and
`240. shown in FIG. 2, and in reading data from the data
`output register circuits.
`The reset circuit 302 responds to an active low reset signal
`RESl:T* to initialize the circuits of the three-phase timing
`signal generator 210. Digressing, referring to FIG. 6, the
`reset signal RESET"‘
`is produced by a NOR gate 604 and
`becomes active low state whenever a system reset signal
`SYSRESET" is produced or when programmed latency is
`changed, as indicated by the disabling of a NOR gate 602 by
`either one of its input signals CL2 or CL3 becoming a logic
`high level, as will be described. The system reset signal
`SYSRESET* is provided at powerup at the start of a write
`operation or in response to prcchargirtg of both memory
`banks at the end of a read function.
`
`the latency timing control
`Referring again to FIG. 3,
`circuit 304 delays the response ofthe timing signal generator
`for one cycle of the external clock following the application
`of the rum! signal. This delay provides the inherent clock
`latency of one for the data output multiplexing control
`circuit 220 (FIG. 6) in the exemplary embodiment.
`It is
`pointed out that the timing signal generator can be used in
`other applications in which this delay is not required. In such
`appiications, the latency timing control circuit 304 can be
`bypassed by connecting the output of the reset circuit 302
`directly to the input of the output driver circuit 306.
`Alternatively, for applications in which the inherent one
`cycle of clock latency is not required, the timing signal
`generator can be produced without the latency timing con-
`trol circuit.
`
`l-TJ
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`15
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`25
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`39
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`35
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`8
`in a known
`produce enabling signals I:'n1, E112 and En3,
`sequence. defining the three -phase timing signals.
`The use of the shift register 308 in producing the three-
`phase timing signals in accordance with the invention mini-
`mizes time delays through the timing signal generator. In
`addition,
`the multiplexer and output driver circuit 306
`causes the timing pulses TPA and TPB provided on nodes
`446 and 448 (FIG. 4) to change at the same time to provide
`complementary signals for stepping the bit pattern through
`the shift register 308, further minimizing deiay. In contrast,
`the use of inverting of shift register outputs to produce
`complementary shift register clocking signals in the con-
`ventional manner, would result
`in considerable delay in
`clocking the bit pattern through the shift register.
`Considering the three-phase timing signal generator 210
`in more detail, with reference to FIG. 4, the reset circuit 302
`includes an inverter 402, a NOR gate 404 and a NOR latch
`circuit 406. The external or system clock C‘LK is connected
`to one input of the NOR gate 404, the other input of which
`is connected to receive the complement of the reset signal
`RESET‘. The external clock CLK is also connected to one
`
`input of a NAND gate 410 of the multiplexer and output
`driver circuit 306. The NOR latch circuit 406 is reset
`in
`response to each low condition (active state) for the reset
`signal RESET"‘.
`The latency timing control circuit 304 includes a
`p-channel pass transistor 412,
`a
`latch circuit 414, an
`n-channel pass transistor 416 and a latch circuit 418 which
`are connected in series between the output of NOR latch 406
`ofthe reset circuit 302 and :1 second input ofNAND gate 410
`of the multiplexer circuit 306. The gate electrodes of the
`transistors 412 and 416 are commonly connected to the
`output of an inverter 420 the input of wlrich is connected to
`receive the external clock t’.‘l.K. The latency control circuit
`304 further includes an nchannel
`transistor 422 and a
`p-channel transistor 424 for initializing the latch circuits 414
`and 418. Transistor 422 has its gate electrode connected to
`the output of inverter 402 to load a logic high level, ie, logic
`1, into the latch circuit 414 when the reset signal RESET*
`and is in its true state. Similarly, transistor 424 has its gate
`electrode connected to conductor 426 and is responsive to
`the true state for the reset signal RESET“ to load a logic low
`level, i.e., logic 0, into the latch circuit 418.
`The multiplexer and output driver circuit 306 includes a
`two—stage shift register 430, having an input stage 43] and
`an output stage 432, the output of which is coupled through
`an inverter 433 to the input of the input stage 431. The
`multiplexer and output driver circuit 306 further includes a
`complementary two-stage shift register