`
`In re Patent of: Krause
`US Patent No.: 6,157,589
`Issue Date:
`December 5, 2000
`Appl. Serial No.: 09/343,431
`
`Title: DYNAMIC SEMICONDUCTOR MEMORY DEVICE AND METHOD
`FOR INITIALIZING A DYNAMIC SEMICONDUCTOR MEMORY
`DEVICE
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`
`
`DECLARATION OF VIVEK SUBRAMANIAN
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`
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`
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`I, Vivek Subramanian, declare as follows:
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`I. Introduction
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`1.
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`I am making this declaration at the request of the Real Party in Interest
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`(Kingston Technology Company, Inc.) in the matter of Inter Partes Review of U.S.
`
`Patent No. 6,157,589 (“the ’589 patent”).
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`2.
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`I am being compensated for my work. My compensation does not depend on
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`the outcome of this proceeding.
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`3.
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`I have been asked to consider whether certain references disclose or render
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`obvious the claims of the ’589 Patent, either alone or in combination with each
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`other.
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`1
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`KINGSTON 1003
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`4.
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`I have been advised that a patent claim may be invalid as obvious if the
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`differences between the subject matter patented and the prior art are such that the
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`subject matter as a whole would have been obvious at the time of the invention to a
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`person having ordinary skill in the art. I have also been advised that several factual
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`inquiries underlie a determination of obviousness. These inquiries include the
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`scope and content of the prior art, the level of ordinary skill in the field of the
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`invention, the differences between the claimed invention and the prior art, and any
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`objective evidence of non-obviousness.
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`5.
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`I have been advised that objective evidence of non-obviousness directly
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`attributable to the claimed invention, known as “secondary considerations of non-
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`obviousness,” may include commercial success, satisfaction of a long-felt but
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`unsolved need, failure of others, copying, skepticism or disbelief before the
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`invention, and unexpected results. I am not aware of any such objective evidence
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`of non-obviousness that is directly attributable to the subject matter claimed in the
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`’589 patent at this time.
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`6.
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`In addition, I have been advised that the law requires a “common sense”
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`approach of examining whether the claimed invention is obvious to a person skilled
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`in the art. For example, I have been advised that combining familiar elements
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`according to known methods is likely to be obvious when it does no more than
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`yield predictable results. I have further been advised that this is especially true in
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`2
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`instances where there are a limited numbers of possible solutions to technical
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`problems or challenges.
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`7.
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`I have been informed that claims 11 and 12 of the ’589 Patent are subject to
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`this inter partes review.
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`II. Materials Reviewed
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`8.
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`In forming the opinions, I express below, I considered my own knowledge
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`of the art and at least the following references:
`
`KINGSTON-1001 U.S. Patent No. 6,157,589 (’589 Patent)
`KINGSTON-1002 File History of U.S. Patent No. 6,157,589
`KINGSTON-1005 U.S. Patent No. 6,243,797 B1 (“Merritt”)
`KINGSTON-1006 U.S. Patent No. 5,448,528 (“Nagai”)
`KINGSTON-1007 JEDEC Standard 21-C Release 4
`Plaintiff Polaris Innovations Limited’s Preliminary
`Disclosure Of Asserted Claims And Infringement
`Contentions, Exhibit 1, Preliminary Infringement Claim
`Chart for U.S. Patent No. 6,157,589 (“589 Patent”)
`Polaris Innovations Ltd. v. Kingston Tech. Co., Inc., Case
`No. 8:16-cv-300-CJC (C.D. Cal. July 8, 2016)
`
`KINGSTON-1008
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`III. Qualifications
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`9.
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`I summarize my relevant knowledge and experience below. My Curriculum
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`Vitae contains additional information and is attached as Exhibit 1004.
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`3
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`10.
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`I received a B.S. in electrical engineering from Louisiana State University in
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`1994, an M.S. in electrical engineering from Stanford University in 1996, and a
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`Ph.D. in electrical engineering from Stanford University in 1998.
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`11.
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`I co-founded Matrix Semiconductor, Inc. in 1998 to develop high density
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`memory technology.
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`12.
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`I have been teaching in the Electrical Engineering and Computer Sciences
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`Department at the University of California, Berkeley since 2000. I was an
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`Assistant Professor from 2000 to 2005, an Associate Professor from 2005 to 2011,
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`and a Professor from 2011 to the present.
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`13.
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`I have been an adjunct professor at the Sunchon National University in
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`Sunchon, Korea since 2009, leading research in printed electronics.
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`14.
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`I have been an independent consultant in the semiconductor industry since
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`2000, focusing on memory technology, flexible electronics, and RFID technology.
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`15.
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`I have published more than 200 technical papers in journals and at
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`conferences.
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`16.
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`I am a named inventor on over 40 U.S. Patents, many of which are in the
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`field of memory design.
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`IV. Person of Ordinary Skill in the Art and State of The Art
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`17.
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`In my opinion, a person of ordinary skill in the art as of the time of the ’589
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`Patent would have a Master’s degree in Electrical Engineering and at least 2 years’
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`4
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`experience working in the field of semiconductor memory design. I believe this to
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`be a reasonable statement of the level of ordinary skill in the art for the patent and
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`claims at issue. I also believe that I was one of ordinary skill in the art at the time
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`the ’589 Patent was filed.
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`18. The opinions that I provide in this declaration are consistent with the
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`knowledge and experience of one of ordinary skill in the art at the priority date of
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`the ’589 Patent.
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`19. At the time of the ’589 Patent’s priority date, a standard initialization
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`sequence was well known in the art, as specified in the JEDEC standard and as
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`recognized in the specification of the ’589 patent itself. See Ex. 1001 at 1:21-2:5
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`(describing JEDEC initialization sequence as prior art); see also Ex. 1007, JEDEC
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`21-C Standard at 115. It was further well known in the art that within this
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`initialization sequence, at least 200 microseconds needed to elapse after powering
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`on the DRAM in order to stabilize the electrical properties of the DRAM,
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`including voltage. Moreover, those of ordinary skill in the art recognized that a
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`DRAM control circuit could be used to carry out the JEDEC initialization
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`sequence, by sending the various signals specified in the initialization sequence
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`(such a reset signal, a clock enable signal, and a mode register set signal) such that
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`the DRAM was ready for normal operation. See Ex. 1005 at Fig. 1; Ex. 1006 at
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`Fig. 1.
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`5
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`V. Overview of the ’589 Patent
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`20. The ’589 Patent is directed to a Dynamic Semiconductor Random Access
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`Memory (“DRAM”) device and a method for initializing a DRAM device. Ex.
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`1001 at 2:7-14. The device and method purportedly solve a problem in the prior art
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`by providing a way for circuits to be “reliably held in a desired defined state” while
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`the device is powering on. Id. at 1:22-35. This purported advancement is achieved
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`by following a particular initialization sequence. Id. To perform the initialization
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`sequence, the device contains an initialization circuit having a control circuit and
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`an enable circuit. Id. at 2:15-36.
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`21. As seen in Fig. 1 of the ’589 patent, once the initialization circuit performs a
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`switching-on operation and the internal voltage regulation and detection circuit 5
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`detects that the supply voltage at input 6 is stabilized, detection circuit 5 supplies a
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`supply voltage stable signal (POWERON) to the enable circuit 9. Id. at 3:42-4:23.
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`The enable circuit 9 receives the supply voltage stable signal (POWERON) at
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`input 11 and various command signals at input 10. Id. Once the enable circuit
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`receives the supply voltage stable (POWERON) signal and the various command
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`signals in the correct sequence, it outputs an enable signal (CHIPREADY) at
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`output 12 which then unlatches the control circuit 13. Id.
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`22. Fig. 2 of the ’589 patent, illustrates an example of enable circuit 9 in more
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`detail. It contains “three bistable multivibrator stages 14, 15 and 16 each having a
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`6
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`
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`set input S, a reset input R, and also an output Q.” Id. at 4:24-58. The supply
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`voltage stable signal (POWERON), described above, is applied to the enable
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`circuit at input 11. Id. Additionally, the command signals described above at input
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`10 are shown in more detail. Id. Input 10A receives a preparation command for
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`word line activation, called PRE or PRECHARGE. Id. Input 10B receives a refresh
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`command, called ARF or AUTOREFRESH. Id. Input 10C receives a loading
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`configuration register command, called MRS or MODE-REGISTER-SET. Id. The
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`enable signal (CHIPREADY) is output at output 12 after “a predetermined
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`chronological initialization sequence of the command signals PRE, ARF and MRS
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`and activation of the [supply voltage steady] POWERON signal.” Id.
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`VI. Claim Construction
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`23.
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`I have been instructed that under 37 C.F.R. § 42.100(b), a claim in inter
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`partes review is given the “broadest reasonable construction” in light of the
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`specification. See In re Cuozzo Speed Techs., LLC., 793 F.3d 1268, 1276 (Fed. Cir.
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`2015). I have also been instructed that the standard for claim construction at the
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`Patent Office is different (i.e., broader) from that used in a U.S. district court
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`litigation. See In re American Academy of Science Tech Center, 367 F.3d 1359,
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`1364, 1369 (Fed. Cir. 2004). Furthermore, I have reviewed the infringement
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`contentions advanced by Patent Owner for the ’589 Patent against the Petitioner.
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`See Ex. 1008. While I do not agree with Patent Owner’s infringement contentions,
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`7
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`it is my opinion that under the “broadest reasonable construction” for purposes of
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`IPR only, the claims of the ’589 patent must include the functionalities identified
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`as allegedly infringing by the Patent Owner in district court.
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`VII. Certain References Disclose And Render Obvious Claims 11 and 12 of the
`’589 Patent
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`A. Claims 11 and 12 of the ’589 Patent Are Obvious Based on Merritt.
`24.
`I have been advised, and my understanding is, that Merritt is eligible to serve
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`as prior art for the ’589 Patent under 35 U.S.C. § 102 (a), § 102(b), and § 102(e).
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`Merritt was filed on February 18, 1997, more than one year before the priority date
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`of the ’589 patent. See Ex. 1008.
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`25.
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`In my opinion, one of ordinary skill in the art would find every limitation of
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`claims 11 and 12 of the ’589 patent to have been disclosed (taught) or rendered
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`obvious by the semiconductor memory system set forth in Merritt.
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`1.
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`Claim 11
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`a. An improved method for initializing a dynamic
`semiconductor memory device of a random access type
`via an initialization circuit controlling a switching-on
`operation of the dynamic semiconductor memory
`device and of its circuit components, the improvement
`which comprises:
`In my opinion, Merritt discloses a method for initializing a dynamic
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`26.
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`semiconductor memory device of a random access type via an initialization circuit
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`8
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`controlling a switching-on operation of the dynamic semiconductor memory device
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`and of its circuit components.
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`27.
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`I believe that under the broadest reasonable interpretation of this claim
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`limitation, as advanced by Patent Owner in district court, this limitation is satisfied
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`with the disclosure of a DRAM controller that controls the switching-on operation
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`of the DRAM and its circuit components:
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`Ex. 1008 at 1-8 (emphasis added): To the extent that the preamble of Claim 11 is a
`limitation, the 589 Accused Products initialize a dynamic semiconductor memory
`device of a random access type (specifically DDR3 DRAM devices) via an
`initialization circuit in a DDR3 controller, controlling a switching-on operation of
`the DRAM and of its circuit components . . . All Kingston Accused 589 Products
`include one of: a Phison 3108 or 3110 controller, or a Marvell 88SS9293 or
`88SS1074 controller . . . Each such controller includes within it a DDR3 controller
`as an internal functional block. The DDR3 controller controls (including
`initialization) DDR3 DRAM that is external to the Phison or Marvell controller
`and internal to the 589 Accused Product.”).
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`28. Merritt discloses a DRAM controller that controls the switching-on
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`operation of the DRAM and its circuit components:
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`Ex. 1005 at 4:5-8: Control logic 28 controls the various circuitry of SDRAM 10
`based on decoded commands such as during controlled reads or Writes from or to
`bank 0 memory array 22 and bank 1 memory array 24.
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`9
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`29. The Control Logic 28 disclosed in Merritt is a DRAM controller that
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`controls the switching-on operation of the DRAM and its circuit components
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`because it sends various signals that allow the DRAM to function:
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`Ex. 1005 at 14:37-41: when the system reset signal SYSRESET* is provided all of
`the data register circuits, including data register circuit 230, are cleared. Also,
`NOR gate 604 is disabled, causing its output to become a logic low level which
`resets the timing signal generator 210 in the manner that has been described.
`
`Ex. 1005 at 7:26-37: The reset circuit 302 responds to an active low reset signal
`RESET* to initialize the circuits of the three-phase timing signal generator 210.
`Digressing, referring to FIG. 6, the reset signal RESET* is produced by a NOR
`gate 604 and becomes active low state whenever a system reset signal
`SYSRESET* is produced or when programmed latency is changed, as indicated by
`the disabling of a NOR gate 602 by either one of its input signals CL2 or CL3
`becoming a logic high level as will be described. The system reset signal
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`10
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`
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`SYSRESET* is provided at powerup at the start of a write operation or in response
`to precharging of both memory banks at the end of a read function.
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`30. Moreover, those skilled in the art would find that it was inherent and
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`required to have initialization circuitry to control the switching-on operation of the
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`DRAM, as the DRAM could not turn on without such circuitry. Merritt recognizes
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`this understanding in stating that “[p]ower-up and initialization functions of the
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`SDRAM 10 are conducted in the conventional manner.” Ex. 1005 at 4:22-24
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`b. supplying, via the initialization circuit, a supply voltage
`stable signal once a supply voltage has been stabilized
`after the switching-on operation of the dynamic
`semiconductor memory device; and
`In my opinion, Merritt discloses supplying, via the initialization circuit, a
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`31.
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`supply voltage stable signal once a supply voltage has been stabilized after the
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`switching-on operation of the dynamic semiconductor memory device.
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`32.
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`I believe that under the broadest reasonable interpretation of this claim
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`limitation, as advanced by Patent Owner in district court, this limitation is satisfied
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`where an active low synchronous reset signal generated:
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`Ex. 1008, at 9-13: When Kingston (in testing and using the Kingston 589 Accused
`Products) or when other users of the Kingston 589 Accused Products use and turn
`the 589 Accused Products on, the Phison or Marvell controller chips supply a
`voltage stable signal (for example, the Active Low synchronous Reset signal,
`/RESET . . . The /RESET signal must be maintained for 200μs with stable power . .
`. The /RESET signal is supplied by the controller chip to the DDR3 DRAM chip.
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`11
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`33. Merritt discloses generating an active low synchronous reset signal:
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`Ex. 1005, col. 7:26-28: The reset circuit 302 responds to an active low reset signal
`RESET* to initialize the circuits of the three-phase timing signal generator 210.
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`34. Moreover, it was well known to those of skill in the art that once powered
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`on, DRAM needed to be maintained for at least 200 microseconds in order for
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`electrical properties such as voltage to stabilize and allow for proper functioning. If
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`the supply voltage was not allowed to stabilize, the DRAM would not function
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`properly. This knowledge was recognized in the JEDEC standard, and was cited in
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`the specification of the ’589 patent itself:
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`Ex. 1007, JEDEC 21-C Standard at 115:
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`
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`Ex. 1001 at 1:21-2:5: According to the JEDEC standard for SDRAM
`semiconductor memories, a recommended initialization sequence (so-called
`“POWERON SEQUENCE”) is provided as follows: . . . the maintenance of a
`stable supply voltage of a stable clock signal, and of stable NOP input conditions
`for a minimum time period of 200 ms.
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`35. Thus, to the extent it was significant, it would have thus been obvious to one
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`of skill in the art to maintain the reset signal disclosed in Merritt for 200
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`microseconds.
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`12
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`36. Furthermore, Merritt discloses a signal generated by Latency Control 304
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`which delays further operation of the DRAM by one clock cycle:
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`Ex. 1005 at 7:38-41: [Latency Control 304] delays the response of the timing
`signal generator for one cycle of the external clock following the application of the
`reset signal.
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`Ex. 1005 at Fig 3:
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`37.
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`It is further evident from Merritt that a delay of one clock cycle would allow
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`the supply voltage to stabilize.
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`13
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`Ex. 1005 at Fig 3:
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`
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`38. Therefore, it is my opinion that the signal generated by the Latency Control
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`304 is a further example of a “supply voltage stable signal once a supply voltage
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`has been stabilized after the switching-on operation of the dynamic semiconductor
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`memory device” that is disclosed by Merritt.
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`c. supplying, via an enable circuit of the initialization
`circuit, an enable signal, the initialization circuit
`receiving the supply voltage stable signal and further
`command signals externally applied to the dynamic
`semiconductor memory device, after an identification
`of a predetermined proper initialization sequence of the
`further command signals the enable signal being
`generated and effecting an unlatching of a control
`circuit provided for a proper operation of the dynamic
`semiconductor memory device.
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`14
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`39.
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`In my opinion, Merritt discloses supplying, via an enable circuit of the
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`initialization circuit, an enable signal, the initialization circuit receiving the supply
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`voltage stable signal and further command signals externally applied to the
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`dynamic semiconductor memory device, after an identification of a predetermined
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`proper initialization sequence of the further command signals the enable signal
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`being generated and effecting an unlatching of a control circuit provided for a
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`proper operation of the dynamic semiconductor memory device.
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`40.
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`I believe that under the broadest reasonable interpretation of this claim
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`limitation, as advanced by Patent Owner in district court, this limitation is satisfied
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`where, after the initialization sequence described above, certain signals are
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`provided to the DRAM device, specifically a Clock Enable Signal (CKE) as the
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`claimed enable signal, and commands to a Mode Register Set as the claimed
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`“further command signals applied to the dynamic semiconductor memory device”:
`
`Ex. 1008 at 14-15: After the Initialization Sequence, described above, the Phison
`and Marvell controller chips provide, via an enable circuit of the initialization
`circuit (circuitry within the DDR Controller block of the Phison or Marvel
`controller), an enable signal (for example, the Clock Enable signal, CKE) . . . The
`Phison and Marvell controller chips in the Kingston 589 Accused Products provide
`further command signals externally applied to the DDR3 DRAM devices, after the
`identification of the predetermined proper initialization sequence (for example, the
`Mode Register Set (“MRS”) and/or ZQ Calibration (“ZQCL”) commands.
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`41. Merritt discloses a Clock Enable Signal (CKE):
`
`Ex. 1005 at 3:54-62: A system clock (CLK) signal is provided through a CLK
`input pin and a clock enable signal (CKE) is provided through a CKE input pin to
`SDRAM 10. The CLK signal is activated and deactivated based on the state of the
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`15
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`
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`CKE signal. All the input and output signals of SDRAM 10, with the exception of
`the CKE input signal during power down and self refresh modes, are synchronized
`to the active going edge (the positive going edge in the embodiment illustrated in
`FIG. 1) of the CLK signal.
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`42. Merritt also discloses another type of “enable signal.” Specifically, Merritt
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`discloses that the initialization circuit of Fig. 3 is configured “to produce enabling
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`signals En1, En2 and En3, in a known sequence, defining the three-phase timing
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`signals.” Ex. 1005 at 7:66-8:2.
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`See also Ex. 1005 at Fig 3:
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`
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`43. Merritt also discloses a Mode Register 40 that can receive signals/commands
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`to set certain parameters for the DRAM:
`
`Ex. 1005 at 5:61-6:12: Programmability of operating parameters of the
`synchronous dynamic random access memory, such as burst length, burst type,
`read latency, operating mode and a write burst mode, is accomplished through the
`use of a mode register 40 associated with control logic 28 (FIG. 1). The user
`selects the mode register 40 command to select operating parameters, such as burst
`length or latency, for the semiconductor SDRAM, as is known in the art. The mode
`register 40 latches the state of one or more of the address input signals A0-A9, or
`data signals DQ0-DQ7, upon receipt of a write-CAS*-before-RAS* (WCBR)
`programming cycle. In the exemplary embodiment, latency control outputs CL2
`and CL3 provided by the mode register 40 are used to control the required circuits
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`16
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`of the SDRAM. Moreover, the data output multiplexing circuits provide an
`inherent clock latency of one and are programmable to provide a clock latency of
`two or a clock latency of three. This basic implementation requires very little
`additional circuitry to the standard SDRAM.
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`44. Merritt also discloses a Command Decoder 26 that receives numerous other
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`commands that, in my opinion are that can send various commands/signals to the
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`DRAM:
`
`Ex. 1005 at 3:63-4:11: A chip select (CS*) input pin inputs a CS* signal which
`enables, when low, and disables, when high a command decoder 26. Command
`decoder 26 is included in control logic 28. Command decoder 26 receives control
`signals including a row address strobe (RAS*) signal on a RAS* pin, column
`address strobe (CAS*) signal on a CAS* pin, and a write enable (WE*) signal on a
`WE* pin. Command decoder 26 decodes the RAS*, CAS*, and WE* signals to
`place control logic 28 in a particular command operation sequence. Control logic
`28 controls the various circuitry of SDRAM 10 based on decoded commands such
`as during controlled reads or writes from or to bank 0 memory array 22 and bank 1
`memory array 24. A bank address (BA) signal is provided on a BA input pin to
`define which bank memory array should be operated on by certain commands
`issued by control logic 28.
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`45. Moreover, I believe that under the broadest reasonable interpretation of this
`
`claim limitation, as advanced by Patent Owner in district court, “effecting an
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`unlatching of a control circuit provided for a proper operation of the dynamic
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`semiconductor memory device,” is satisfied through the use of a CKE signal:
`
`Ex. 1008 at 19: The CKE signal effects an unlatching of a control circuit provided
`for a proper operation of the DDR3 DRAM device . . .
`
`46. As discussed above, Merritt discloses the use of a CKE a signal, and
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`therefore discloses “effecting an unlatching of a control circuit provided for a
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`proper operation of the dynamic semiconductor memory device,” under the
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`17
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`
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`broadest reasonable interpretation of this claim limitation (for purposes of this
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`IPR).
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`47. Furthermore, Merritt explicitly discloses unlatching, in that NOR latch 406
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`can be unlatched based on clock pulses, which, as explained above, are controlled
`
`by the CKE signal:
`
`Ex. 1005 at 10:56-65: The first external or system clock pulse CLK, following the
`reset operation, sets the NOR latch 406, providing a logic 1 level at its input. This
`clock pulse, through inverter 420, also disables transistor 416 to isolate latch 414
`from latch 418 and enables transistor 412 to couple the logic high level output of
`NOR latch 406 to latch 414. Accordingly, the output of latch 414 becomes a logic
`low level. Transistor 416 is enabled when this clock pulse terminates and couples
`the logic low level provided at the output of the latch 414 to latch 418.
`Consequently, the output of latch 418 becomes a logic high level, allowing the
`NAND 410 gate to follow subsequent system clock pulses CLK.
`
`Ex. 1005 at 8:23-25: The NOR latch circuit 406 is reset in response to each low
`condition (active state) for the reset signal RESET*.
`
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`2.
`
`Claim 12
`
`a. The method according to claim 11, which comprises
`providing at least one of a preparation command signal
`for word line activation, a refresh command signal, and
`a loading configuration register command signal as the
`further command signals.
`
`In my opinion, Merritt discloses providing at least one of a preparation
`
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`48.
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`command signal for word line activation, a refresh command signal, and a loading
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`configuration register command signal as the further command signals.
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`49.
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`I believe that under the broadest reasonable interpretation of this claim
`
`limitation, as advanced by Patent Owner in district court, the “preparation
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`18
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`
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`command signal for word line activation” and the “loading configuration register
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`command signal” (only one of which is required to satisfy this claim limitation) are
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`both disclosed through the use of the Mode Register commands/signals discussed
`
`above:
`
`Ex. 1008 at 24: The Phison and Marvell controllers provide at least one of: (1)
`preparation command signal for word line activation; (2) a refresh command
`signal; and (3) a loading configuration register commend signal as the further
`command signals. Specifically, the MRS command discussed above as a further
`command signals acts as both a preparation signal and as a loading configuration
`register command signal.
`
`50. As discussed above, Merritt discloses a Mode Register 40 and mode register
`
`commands/signals and therefore discloses both the “preparation command signal
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`for word line activation” and the “loading configuration register command signal.”
`
`51. Merritt also explicitly discloses a preparation command signal:
`
`Ex. 1005 at 4:56-62: Address pin A10 provides an input path for a command signal
`which determines whether or not an AUTO-PRECHARGE command is to be
`initiated automatically after the READ command as is known in the art.
`
`PRECHARGE is explicitly recognized as a “preparation command signal for word
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`line activation” in the ’589 patent:
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`Ex. 1001 at 2:46-54: The command signals include a preparation command signal
`for Word line activation (PRECHARGE) . . .
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`52. Moreover, the Precharge, Autorefresh, and Mode-Register commands were
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`well known in the art long before the filing of the ’589 patent. For example, the
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`JEDEC standard disclosed many of these commands. See Ex. 1007, JEDEC 21-C
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`19
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`
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`Standard Rev 4 at 110 & 115 (describing the Auto Precharge and Precharge All
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`Banks commands), 115 (listing “issue a mode register set command to initialize the
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`mode register” as part of the recommended power on sequence for SDRAM); 117
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`(describing the autorefresh command), and 114 (describing the SDRAM Mode
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`Register and that “This Mode Register is located on the Synchronous DRAM
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`(SDRAM) chip. Its purpose is to store the mode of operation data. This data is
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`written after power-on and before normal operation. The data contains the Burst
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`Length, the Burst Type, the CE Latency, and whether it is to be operating in Test
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`Mode, or Normal operating mode.” It would have been obvious and expected for
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`one of ordinary skill in the art to combine the teachings of Merritt and the JEDEC
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`standard by using these standard DRAM commands with the Merritt system (i.e. to
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`enable the use of Merritt with more JEDEC standard DRAM memories).
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`B. Claims 11 and 12 of the ’589 Patent Are Obvious Based on Merritt in
`view of Nagai.
`I have been advised, and my understanding is, that Nagai is eligible to serve
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`53.
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`as prior art for the ’589 Patent under 35 U.S.C. § 102 (a), § 102(b), and § 102(e).
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`Merritt was filed on September 19, 1994, well earlier than one year before the
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`priority date of the ’589 patent. See Ex. 1008.
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`54. U.S. Patent No. 5,448,528 to Nagai discloses an initialization circuit with a
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`200 microsecond delay (plus 8 dummy cycles) during and after the RST signal. See
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`generally Ex. 1006. One of ordinary skill in the art would be motivated to combine
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`20
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`
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`
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`Nagai with Merritt at least because Merritt explains that “Power-up and
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`initialization functions of the SDRAM 10 are conducted in the conventional
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`manner.” Ex. 1005 at 4:22-24. Accordingly, one of ordinary skill would review
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`other prior art initialization circuits, such as the one present in Nagai, to combine
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`with the circuitry of Merritt. Both Merritt and Nagai further employ standard
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`DRAM designs (RAS, CAS, etc.) further bringing the circuitry of Nagai to the
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`attention of one of ordinary skill.
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`55. Therefore, in my opinion, one of ordinary skill in the art would find every
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`limitation of claims 11 and 12 of the ’589 patent to have been disclosed (taught) or
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`rendered obvious by the semiconductor memory system set forth in Merritt.
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`1.
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`Claim 11
`
`a. An improved method for initializing a dynamic
`semiconductor memory device of a random access type
`via an initialization circuit controlling a switching-on
`operation of the dynamic semiconductor memory
`device and of its circuit components, the improvement
`which comprises:
`
`In my opinion, Merritt in view of Nagai discloses a method for initializing a
`
`
`56.
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`dynamic semiconductor memory device of a random access type via an
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`initialization circuit controlling a switching-on operation of the dynamic
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`semiconductor memory device and of its circuit components for at least the same
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`reasons discussed above. See supra ¶¶26-30; infra ¶¶65-68.
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`21
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`
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`
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`57.
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`b. supplying, via the initialization circuit, a supply voltage
`stable signal once a supply voltage has been stabilized
`after the switching-on operation of the dynamic
`semiconductor memory device; and
`
`
`In my opinion, Merritt in view of Nagai discloses supplying, via the
`
`initialization circuit, a supply voltage stable signal once a supply voltage has been
`
`stabilized after the switching-on operation of the dynamic semiconductor memory
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`device for at least the same reasons discussed above. See supra ¶¶31-38.
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`58. As noted above in the discussion of Merritt, the broadest reasonable
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`interpretation of this limitation and the “supply voltage stable signal” is met where
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`a reset signal is generated.
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`59. To the extent that Patent Owner’s assertions that the reset signal must be
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`maintained for 200 microseconds is significant, see Ex. 1008 at 10, Nagai discloses
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`a 200 microsecond voltage stabilization timing, as well as allowing that timing to
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`pass both during and after the reset signal:
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`22
`
`
`
`
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`Ex. 1006 at Fig. 3B:
`
`
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`Ex. 1006 at 1:57-62: Generally, a DRAM cannot be accessed immediately after the
`power source voltage VCC starts up, as shown in FIG. 3A. Namely, after the
`power source voltage VCC reaches a specified value, such as 3.3 V±0.3 V, 200 μs,
`i.e., the time that is required for the substrate bias circuit within the DRAM to
`stabilize, is allowed to pass.
`
`60.
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`It would have been obvious to one of ordinary skill in the art to combine the
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`teachings of Merritt and Nagai and to maintain the reset signal disclosed in Merritt
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`for 200 microseconds because it would necessary to ensure that the memory has
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`reached a stable voltage before it begins normal operation.
`
`c. supplying, via an enable circuit of the initialization
`circuit, an enable signal, the initialization circuit
`receiving the supply voltage stable signal and further
`command signals externally applied to the dynamic
`semiconductor memory device, after an identification
`of a predetermined proper initialization sequence of the
`further command signals the enable signal being
`generated and effecting an unlatching of a control
`circuit provided for a proper operation of the dynamic
`semiconductor memory device.
`
`23
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`
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`
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`
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`61.
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`In my opinion, Merritt in view of Nagai discloses supplying, via an enable
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`circuit of the initialization circuit, an enable signal, the initialization circuit
`
`receiving the supply voltage stable signal and further command signals exte