Trials@uspto.gov
`571-272-7822
`
` Paper 9
`Entered: May 2, 2017
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`KINGSTON TECHNOLOGY COMPANY, INC.,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LTD.,
`Patent Owner.
`____________
`
`Case IPR2017-00238
`Patent 6,157,589
`____________
`
`
`
`Before SALLY C. MEDLEY, BARBARA A. PARVIS, and
`MATTHEW R. CLEMENTS, Administrative Patent Judges.
`
`MEDLEY, Administrative Patent Judge.
`
`DECISION
`Denying Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`571-272-7822
`
` Paper 9
`Entered: May 2, 2017
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`KINGSTON TECHNOLOGY COMPANY, INC.,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LTD.,
`Patent Owner.
`____________
`
`Case IPR2017-00238
`Patent 6,157,589
`____________
`
`
`
`Before SALLY C. MEDLEY, BARBARA A. PARVIS, and
`MATTHEW R. CLEMENTS, Administrative Patent Judges.
`
`MEDLEY, Administrative Patent Judge.
`
`DECISION
`Denying Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`I. INTRODUCTION
`
`Kingston Technology Company, Inc. (“Petitioner”) filed a Petition for
`
`inter partes review of claims 11 and 12 of U.S. Patent No. 6,157,589 (Ex.
`
`1001, “the ’589 patent”). Paper 2 (“Pet.”). Polaris Innovations Ltd.
`
`(“Patent Owner”) filed a Preliminary Response. Paper 7 (“Prelim. Resp.”).1
`
`Institution of an inter partes review is authorized by statute when “the
`
`information presented in the petition . . . and any response . . . shows that
`
`there is a reasonable likelihood that the petitioner would prevail with respect
`
`to at least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a);
`
`see 37 C.F.R. § 42.108. Upon consideration of the Petition and Preliminary
`
`Response, we conclude the information presented does not show there is a
`
`reasonable likelihood that Petitioner would prevail in establishing the
`
`unpatentability of claim 11 or claim 12 of the ’589 Patent.
`
`A. Related Matters
`
`The parties state that the ’589 Patent is the subject of a pending
`
`lawsuit in the Central District of California, i.e., Polaris Innovations Ltd. v.
`
`Kingston Tech. Co., Case No. 8:16–cv-300 (C.D. Cal.). Pet. 2; Paper 4
`
`(Patent Owner’s Mandatory Notices), 1.
`
`B. The ’589 Patent
`
`The ʼ589 Patent is directed to a random access memory device (i.e.,
`
`DRAM) having an initialization circuit which controls a switching-on
`
`operation of the semiconductor memory device and of its circuit
`
`
`
`1 Subsequent to filing its Preliminary Response, Patent Owner filed a Motion
`for pro hac vice admission of Nathan Nobu Lowenstein. Paper 8. Because
`we do not institute trial, we dismiss the motion.
`
`2
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`components. Ex. 1001, 1:9–13. Figure 1 of the ’589 Patent is reproduced
`
`below.
`
`
`Figure 1 illustrates a schematic view of components of an
`
`initialization circuit that controls a switching-on operation of a
`
`semiconductor memory.
`
`As shown in Figure 1 above, the initialization circuit has an input
`
`circuit 1, with input command and clock signals 2. Id. at 3:51–54. Input
`
`command and clock signals 2 are amplified and conditioned and then
`
`received by command decoder 3, whose output 4 includes PRE or
`
`PRECHARGE (preparation command for word line activation), ARF or
`
`AUTOREFRESH (refresh command), and MRS or MODE-REGISTER-
`
`SET (loading configuration register command). Id. at 3:54–61. The
`
`initialization circuit further has a circuit 5 for internal voltage regulation
`
`and/or detection, whose input 6 includes the external supply voltages that are
`
`externally applied to the semiconductor memory. Id. at 3:61–65. Circuit 5
`
`has a first output 7 outputting a POWERON signal and a second output 8
`
`supplying stabilized internal supply voltages. Id. at 3:65–67. In operation,
`
`3
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`“circuit 5 supplies an active POWERUP signal if, after the POWERUP
`
`phase of the SDRAM memory, the internal supply voltages present at the
`
`output 8 have reached the values necessary for proper operation of the
`
`component.” Id. at 4:4–8.
`
`Figure 2 of the ’589 Patent is reproduced below.
`
`
`Figure 2 illustrates a circuit diagram of an enable circuit that supplies
`
`an enable signal (CHIPREADY).
`
`Figure 2 above shows the details of the enable circuit 9. Enable
`
`circuit contains “three bistable multivibrator stages 14, 15 and 16 each
`
`having a set input S, a reset input R, and also an output Q.” Id. at 4:25–28.
`
`An AND gate 17 is connected upstream of reset input R of multivibrator
`
`stage 15 and an AND gate 18 is connected downstream of outputs Q of
`
`multivibrator stages 14, 15, and 16. Id. at 4:25–31. The enable signal
`
`CHIPREADY is output at output 12 of inverter 19 and the enable signal
`
`CHIPREADY is active HIGH, i.e., activated when its voltage level is at a
`
`logic HIGH. The command signals PRE, ARF, MRS applied to respective
`
`set inputs S of 14, 15, and 16 are each active LOW. Id. at 4:31–40. The
`
`4
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`supply voltage stable signal (POWERON) is applied to reset inputs R for
`
`multivibrator stages 14 and 16 and applied to input of AND gate 17 for
`
`multivibrator stage 15. Id. at 4:40–48.
`
`In operation, activation of enable signal CHIPREADY at output 12 to
`
`logic HIGH is generated only when a predetermined chronological
`
`initialization sequence of command signals PRE, ARF, and MRS and
`
`activation of the POWERON signal to the logic level HIGH are detected.
`
`Id. at 4:48–55. “Only then are the control circuits 13 unlatched on account
`
`of the activation of the enable signal CHIPREADY; the control circuits 13
`
`remaining latched prior to this.” Id. at 4:55–58.
`
`C. Illustrative Claim
`
`Petitioner challenges independent claim 11 and dependent claim 12
`
`which depends from claim 11. Independent claim 11, reproduced below, is
`
`illustrative of the claimed subject matter:
`
`initializing a dynamic
`for
`improved method
`11. An
`semiconductor memory device of a random access type via an
`initialization circuit controlling a switching-on operation of
`the dynamic semiconductor memory device and of its circuit
`components, the improvement which comprises:
`
`supplying, via the initialization circuit, a supply voltage stable
`signal once a supply voltage has been stabilized after the
`switching-on operation of
`the dynamic semiconductor
`memory device; and
`
`supplying, via an enable circuit of the initialization circuit, an
`enable signal, the initialization circuit receiving the supply
`voltage stable signal and further command signals externally
`applied to the dynamic semiconductor memory device, after
`an identification of a predetermined proper initialization
`sequence of the further command signals the enable signal
`being generated and effecting an unlatching of a control
`
`5
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`circuit provided for a proper operation of the dynamic
`semiconductor memory device.
`
`Id. at 6:36–54.
`
`D. Asserted Grounds of Unpatentability
`
`Petitioner asserts that claims 11 and 12 are unpatentable based on the
`
`following grounds (Pet. 3):
`
`Reference(s)
`
`Merritt2
`Merritt and Nagai3
`
`Nagai
`
`Basis
`
`Challenged Claims
`
`§ 103(a) 11 and 12
`
`§ 103(a) 11 and 12
`
`§ 103(a) 11 and 12
`
`II. DISCUSSION
`
`A. Claim Construction
`
`In an inter partes review, we construe claim terms in an unexpired
`
`patent according to their broadest reasonable construction in light of the
`
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b).
`
`Consistent with the broadest reasonable construction, claim terms are
`
`presumed to have their ordinary and customary meaning as understood by a
`
`person of ordinary skill in the art in the context of the entire patent
`
`disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir.
`
`2007).
`
`Based on the record before us, we need not interpret explicitly any
`
`claim term for purposes of this decision. See Vivid Techs., Inc. v. Am. Sci. &
`
`Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`
`
`
`2 U.S. Patent No. 6,243,797 B1, issued Jun. 5, 2001 (Ex. 1005) (“Merritt”).
`3 U.S. Patent No. 5,448,528, issued Sep. 5, 1995 (Ex. 1006) (“Nagai”).
`
`6
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`B. Obviousness of Claims 11 and 12 over Merritt
`
`Petitioner contends claims 11 and 12 are unpatentable under
`
`35 U.S.C. § 103(a) as obvious over Merritt. Pet. 11–27. In support of its
`
`showing, Petitioner relies upon the declaration of Dr. Vivek Subramanian.
`
`Id. (citing Ex. 1003).
`
`In its Preliminary Response, Patent Owner argues that Petitioner fails
`
`to account for certain claim 11 limitations. Prelim. Resp. 36–50. In
`
`particular, Patent Owner asserts that Petitioner has not sufficiently accounted
`
`for the following limitation: “supplying, via an enable circuit of the
`
`initialization circuit, an enable signal, the initialization circuit receiving the
`
`supply voltage stable signal and further command signals externally applied
`
`to the dynamic semiconductor memory device, after an identification of a
`
`predetermined proper initialization sequence of the further command signals
`
`the enable signal being generated and effecting an unlatching of a control
`
`circuit provided for a proper operation of the dynamic semiconductor
`
`memory device.” Id. at 44–47. As explained below, we find this issue to be
`
`dispositive and agree with Patent Owner that Petitioner has failed to show
`
`sufficiently that Merritt describes the above limitation.
`
`Merritt
`
`
`
`Merritt describes a multiplexing arrangement for controlling the
`
`transfer of data retrieved from a memory array of a semiconductor memory
`
`to data outputs of the semiconductor memory and provides programmable
`
`latency control in the data transfer operation. Ex. 1005, 2:8–12. Figure 1,
`
`reproduced below, shows a synchronous dynamic random access memory
`
`(SDRAM) 10 incorporating a multiphase timing signal generator and a data
`
`output multiplexing control circuit. Id. at 2:65–67, 3:34–37.
`
`7
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`
`
`Figure 1 of Merritt illustrates a block diagram of a synchronous
`
`
`
`dynamic random access memory incorporating a multiphase timing signal
`
`generator and a data output multiplexing control circuit.
`
`
`
`As illustrated above, Merritt Figure 1 shows SDRAM 10 organized as
`
`a dual 1 Megx8 memory and including a synchronous interface. Id. at 3:37–
`
`39. System clock signal (CLK) is provided through a CLK input pin and a
`
`clock enable signal (CKE) is provided through a CKE input pin of control
`
`logic 28. Id. at 3:54–56, Fig. 1. The CLK signal is activated and
`
`deactivated based on the state of the CKE signal. All input and output
`
`signals with the exception of CKE input signal during power down and self
`
`refresh modes, are synchronized to the active going edge of the CLK signal.
`
`Id. at 3:56–62. “Control Logic 28 controls the various circuitry of SDRAM
`
`10 based on decoded commands such as during controlled reads or writes
`
`8
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`from or to bank 0 memory array 22 and bank 1 memory array 24.” Id. at
`
`4:5–8. Merritt further describes that “[p]ower-up and initialization functions
`
`of the SDRAM 10 are conducted in the conventional manner.” Id. at 4:21–
`
`26.
`
`Figure 3 of Merritt, reproduced below, shows details of the three-
`
`phase generator 210 of output multiplexer 20. Id., Figs. 1–3.
`
`
`
`Figure 3 of Merritt illustrates a block diagram of the multi-phase
`
`
`
`timing signal generator.
`
`Reset circuit 302 “responds to an active low reset signal RESET* to
`
`initialize the circuits of the three-phase timing signal generator 210.” Id. at
`
`7:25–27. Latency control 304 delays the response of timing signal generator
`
`for one cycle of the external clock following the application of the reset
`
`signal. Id. at 7:38–41. Shift register 308 comprises a six-stage, ring
`
`connected shift register and is driven by internal timing of shift pulses TPA
`
`and TPB. Id. at 7:53–59. Signals provided on the outputs 471–476 of shift
`
`register 308 are applied to output circuit 310. Output circuit 310 produces
`
`enabling signals En1, En2, and En3. Id. at 7:64–8:2.
`
`Analysis
`
`Claim 1 recites “supplying, via an enable circuit of the initialization
`
`circuit, an enable signal, the initialization circuit receiving the supply
`
`9
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`voltage stable signal and further command signals externally applied to the
`
`dynamic semiconductor memory device, after an identification of a
`
`predetermined proper initialization sequence of the further command signals
`
`the enable signal being generated and effecting an unlatching of a control
`
`circuit provided for a proper operation of the dynamic semiconductor
`
`memory device.”
`
`Petitioner accounts for the various functions of the initialization
`
`circuit by relying on different circuits as the initialization circuit without any
`
`explanation as to how any of the identified initialization circuits cooperate as
`
`the claimed initialization circuit. For example, Petitioner relies on Merritt’s
`
`figure 1 controller 28 as the initialization circuit (Pet. 12), but also appears to
`
`rely on three-phase timing generator 210 of figure 1 output multiplexer 20,
`
`as the initialization circuit (id. at 17–18, 21). Petitioner, however, does not
`
`identify in any of what Petitioner relies on as the initialization circuit an
`
`“enable circuit of the initialization circuit.”4 We agree with Patent Owner
`
`that Petitioner “never specifically identifies anything in Merritt as the
`
`‘enable circuit.’” Prelim. Resp. 44.
`
`The Petition points to two different signals as the claimed “enable
`
`signal,” the enabling signals En1, En2, and En3 shown in figure 3 of Merritt,
`
`and the Clock Enable Signal (CKE) shown in Merritt figure 1 as an input
`
`
`
`4 Petitioner does not provide a claim construction for the “enable circuit of
`the initialization circuit,” such that we should, for example, ignore the
`phrase in its entirety. See, e.g., Pet. 10–11. Based on the record before us,
`we determine that there is no apparent reason to ignore the claim phrase.
`See e.g., Stumbo v. Eastman Outdoors, Inc., 508 F.3d 1358, 1362 (Fed. Cir.
`2007) (rejecting claim constructions that render phrases in claims
`superfluous).
`
`10
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`into controller 28. Pet. 19–25. The Petition, however, never identifies
`
`which circuit constitutes the enable circuit from which either of the
`
`identified enable signals is supplied. Id. 5 More specifically, with respect to
`
`Petitioner’s contentions that the enabling signals En1, En2, and En3 shown
`
`in Merritt figure 3 meet the “enable signal” limitation, it is not clear which
`
`component(s) of figure 3 allegedly constitutes the enable circuit, or how any
`
`of those circuits shown in figure 3 are “of the initialization circuit.”
`
`Petitioner appears to identify all elements of figure 3 as constituting the
`
`initialization circuit, but never identifies what in figure 3 comprises the
`
`enable circuit as required per 37 C.F.R. § 42.104(b)(4). See, e.g., Pet. 21. In
`
`any event, and with respect to the En1, En2, and En3 signals, the Petition
`
`does not rely on any of those signals to meet the claim 1 limitation that the
`
`enable signal “effect[s] an unlatching of a control circuit provided for a
`
`proper operation of the dynamic semiconductor memory device.”
`
`The Petition also identifies CKE as teaching the enable signal
`
`limitation. Pet. 21. Petitioner appears to rely solely upon the CKE signal as
`
`performing the unlatching function. Id. at 24–25. The CKE signal,
`
`however, is input into what Petitioner identifies elsewhere as the
`
`initialization circuit (controller 28) and, therefore, has not been demonstrated
`
`by Petitioner as being “suppl[ied], via an enable circuit of the initialization
`
`circuit,” as claimed.
`
`
`
`5 We also have considered the paragraphs of Dr. Subramanian’s declaration
`in support of the Petition to which we are directed. Dr. Subramanian also
`does not identify in Merritt an “enable circuit of the initialization circuit.”
`See, e.g., Ex. 1003 ¶¶ 39–47.
`
`11
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`For all of these reasons, we are not persuaded that Petitioner has
`
`established a reasonable likelihood that Petitioner would prevail in its
`
`challenge to claim 11 or claim 12 which depends from claim 11 based on
`
`Merritt.
`
`C. Obviousness of Claims 11 and 12 over Nagai
`
`Petitioner contends claims 11 and 12 are unpatentable under
`
`35 U.S.C. § 103(a) as obvious over Nagai. Pet. 37–45. In support of its
`
`showing, Petitioner relies upon the declaration of Dr. Subramanian. Id.
`
`(citing Ex. 1003).
`
`In its Preliminary Response, Patent Owner argues that Petitioner fails
`
`to show that claims 11 and 12 are rendered obvious in view of Nagai.
`
`Prelim. Resp. 50–59. In particular, Patent Owner asserts that Petitioner has
`
`not sufficiently accounted for the following limitation: “supplying, via an
`
`enable circuit of the initialization circuit, an enable signal, the initialization
`
`circuit receiving the supply voltage stable signal and further command
`
`signals externally applied to the dynamic semiconductor memory device,
`
`after an identification of a predetermined proper initialization sequence of
`
`the further command signals the enable signal being generated and effecting
`
`an unlatching of a control circuit provided for a proper operation of the
`
`dynamic semiconductor memory device.” Id. at 55–57. As explained below,
`
`we find this issue to be dispositive and agree with Patent Owner that
`
`Petitioner has failed to show sufficiently that Nagai describes the above
`
`limitation.
`
`Nagai
`
`
`
`Nagai describes a synchronous DRAM that performs data input/output
`
`in sync with a clock and that has an initial mode setting circuit. Ex. 1006,
`
`12
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`1:6–8. Figure 2 of Nagai is reproduced below.
`
`
`
`Figure 2 of Nagai shows a block diagram showing the overall
`
`configuration of a synchronous DRAM.
`
`
`
`Nagai figure 2 shows an overall configuration of the synchronous
`
`DRAM and is provided with DRAM core 40 of bank 0 and DRAM core 41
`
`of bank 1. Id. at 3:30–34. Control of data input/output is executed, in sync
`
`with clock signal CLK supplied to clock buffer 46. Id. at 3:49–51. Clock
`
`CLK becomes validated in clock buffer 46 when clock enable signal CKE is
`
`set to ‘1’. Id. at 3:63–65. Initial mode setting circuit 30 is shown in more
`
`detail in figure 1, reproduced below.
`
`13
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`
`
`
`
`Figure 1 of Nagai shows a circuit that is related to mode setting within
`
`a synchronous DRAM.
`
`
`
`Nagai figure 1 shows “initial mode setting circuit 30 that performs
`
`initial setting of the mode, that is normally used in the system, in the mode
`
`register 10 at the time of power up.” Id. at 3:68–4:2. Initial mode setting
`
`circuit 30 is provided with a reset signal generating circuit 31 that generates
`
`a one-pulse reset signal RST that is output at start up after detecting that
`
`power source voltage VCC has reached a specific value. Id. at 4:3–7, 34–38.
`
`The outputted reset signal is supplied to the reset input end of D flip flops 11
`
`14
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`to 13 of mode register 10 to clear contents of D flip flops 11 to 13 to 0. Id.
`
`at 4:37–40.
`
`Analysis
`
`Claim 1 recites “supplying, via an enable circuit of the initialization
`
`circuit, an enable signal, the initialization circuit receiving the supply
`
`voltage stable signal and further command signals externally applied to the
`
`dynamic semiconductor memory device, after an identification of a
`
`predetermined proper initialization sequence of the further command signals
`
`the enable signal being generated and effecting an unlatching of a control
`
`circuit provided for a proper operation of the dynamic semiconductor
`
`memory device.”
`
`Petitioner accounts for the various functions of the initialization
`
`circuit by relying on different circuits as the initialization circuit without any
`
`explanation as to how any of the identified initialization circuits comprise or
`
`cooperate as the claimed initialization circuit. For example, Petitioner relies
`
`on the clock buffer (CLOCK BUF 46), command decoder (COM DEC 20),
`
`and initial mode setting circuit 30 (MODE INI. SET 30) of figure 2 of Nagai
`
`as meeting the initialization circuit. See, e.g., Ex. 1003 ¶ 67; see also Pet.
`
`38–40 (relying on the circuit that supplies RST, i.e., initial mode setting
`
`circuit 30, as the “initialization circuit”), 40–44 (relying on the circuit that
`
`supplies CKE, unspecified in Nagai, and the circuit that supplies Mode
`
`Register Setting signal, i.e., command decoder 20, as the “enable circuit of
`
`the initialization circuit”). Petitioner, however, does not identify in any of
`
`what Petitioner relies on as the initialization circuit an “enable circuit of the
`
`initialization circuit.” We agree with Patent Owner that Petitioner fails to
`
`account sufficiently for the claimed enable circuit. Prelim. Resp. 55–57.
`
`15
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`The Petition identifies the clock enable signal CKE as meeting the
`
`enable signal limitation and relies solely upon the clock enable signal CKE
`
`as performing the unlatching function. Pet. 40–44. The clock enable signal
`
`CKE, however, is input into what Petitioner identifies as the initialization
`
`circuit (clock buffer (CLOCK BUF) 46 of figure 2), and has not been
`
`demonstrated by Petitioner as being “suppl[ied], via an enable circuit of the
`
`initialization circuit,” as claimed. Id.6 Importantly, the Petition does not
`
`identify any element of Nagai that comprises the enable circuit as required
`
`per 37 C.F.R. § 42.104(b)(4).
`
`For all of these reasons, we are not persuaded that Petitioner has
`
`established a reasonable likelihood that Petitioner would prevail in its
`
`challenge to claim 11 or claim 12 which depends from claim 11 based on
`
`Nagai.
`
`D. Obviousness of Claims 11 and 12 over Merritt in view of Nagai
`
`Petitioner contends claims 11 and 12 are unpatentable under
`
`35 U.S.C. § 103(a) as obvious over Merritt and Nagai. Pet. 27–36. In
`
`support of its showing, Petitioner relies upon the declaration of Dr.
`
`Subramanian. Id. (citing Ex. 1003).
`
`Fundamentally, the Petition never identifies what is being relied on in
`
`Merritt or Nagai to meet the claim limitations. For example, in addressing
`
`each claim limitation, the Petition contends that “Merritt in view of Nagai
`
`discloses this limitation for at least the same reasons discussed above for
`
`
`
`6 We also have considered the paragraphs of Dr. Subramanian’s declaration
`in support of the Petition to which we are directed. Dr. Subramanian also
`does not identify in Nagai an “enable circuit of the initialization circuit.”
`See, e.g., Ex. 1003 ¶¶ 73–78.
`
`16
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`Merritt.” See, e.g., Pet. 28, 29, 31. Based on such statements, it is unclear
`
`which prior art reference Petitioner relies upon to teach the separate
`
`limitations, or whether Petitioner relies upon a combination of Merritt and
`
`Nagai to meet the claim limitations. Based on the record, we do not know if
`
`the teachings of Merritt and Nagai are equivalent, duplicative, or if the
`
`teachings of one of the references is meant to address a feature that is
`
`missing in the other reference.
`
`Because the Petition is imprecise, it is not possible for us to discern
`
`what Petitioner asserts to be its alleged combination. Identifying where
`
`limitations may be found in prior art references is not sufficient to
`
`demonstrate a reasonable likelihood of success in showing the obviousness
`
`of the claims without explaining how and why the specific teachings of the
`
`references would have been combined. Moreover, and as explained above
`
`with respect to the challenge to claims 11 and 12 as rendered obvious based
`
`on Merritt alone or based on Nagai alone, the Petition does not address
`
`certain limitations of claim 11. Combining the two references as presented
`
`in the Petition does not cure those noted deficiencies.
`
`For all of these reasons, we are not persuaded that Petitioner has
`
`established a reasonable likelihood that Petitioner would prevail in its
`
`challenge to claim 11 or claim 12 which depends from claim 11 based on the
`
`combination of Merritt and Nagai.
`
`III. CONCLUSION
`
`For the foregoing reasons, we determine that Petitioner has not shown
`
`a reasonable likelihood that it would prevail in showing that either one of
`
`claims 11 or 12 of the ’589 patent are unpatentable.
`
`
`
`17
`
`
`
`IPR2017-00238
`Patent 6,157,589
`
`
`
`IV. ORDER
`
`
`
`For the foregoing reasons, it is
`
`ORDERED that the Petition is denied as to all challenged claims, and
`
`no trial is instituted; and
`
`FURTHER ORDERED that Patent Owner’s Motion for Pro Hac Vice
`
`Admission of Nathan Nobu Lowenstein (Paper 8) is dismissed.
`
`
`
`PETITIONER:
`
`David Hoffman
`hoffman@fr.com
`
`Martha Hopkins
`mhopkins@sjclawpc.com
`
`PATENT OWNER:
`
`Kenneth Weatherwax
`weatherwax@lowensteinweatherwax.com
`
`
`18
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
