United States Patent
`Holtey
`
`[19]
`
`US005442704A
`[ii] Patent Number:
`[45] Date of Patent:
`
`5,442,704
`Aug. 15, 1995
`
`[54] SECURE MEMORY CARD WITH
`PROGRAMMED CONTROLLED SECURITY
`ACCESS CONTROL
`[75]
`Inventor:
`Thomas O. Holtey, Newton, Mass.
`[73] Assignee: Bull NH Information Systems Inc.,
`Billerica, Mass.
`[21] Appl. No.: 181,691
`[22] Filed:
`Jan. 14, 1994
`[51]
`Int. CI.*
`H04L 9/32; G07F 7/08
`[52] U.S. CI
`380/23; 235/380
`[58] Field of Search
`380/23, 24, 25;
`235/380, 382
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,819,204 4/1989 Schrenk
`4,882,474 11/1989 Anderl et al
`4,885,788 12/1989 Takaragi et al
`5,285,200 2/1994 Kuriyama
`5,313,520 5/1994 Han
`
`235/380 X
`235/380
`235/380 X
`235/380
`380/23
`
`Primary Examiner—Gilberto Barron, Jr.
`Attorney, Agent, or Firm—Faith F. Driscoll; John S.
`Solakian
`[57]
`ABSTRACT
`A secure memory card includes a microprocessor on a
`
`single semiconductor chip which interconnects through
`an internal bus to a number of non-volatile addressable
`memory chips. The microprocessor includes an ad¬
`dressable non-volatile memory for storing information
`including a number of key values and program instruc¬
`tion information. Each chip's memory is organized into
`a number of blocks, each block including a number of
`rows of byte locations. Each row of each block further
`includes a lock bit location, the total number of which
`provide storage for a lock value uniquely coded to
`utilize a predetermined characteristic of the memory to
`ensure data protection. Each memory chip is con¬
`structed to include security control logic circuits which
`include a security access control unit and a volatile
`access control memory containing a plurality of access
`control storage elements. Under the control of a prede¬
`termined set of instructions, the security access control
`unit performs a predetermined key validation operation
`by comparing key values against the bit contents of lock
`bit locations read out a bit at a time during an authenti¬
`cation procedure with a host computer. After the suc¬
`cessful performance of the key validation procedure,
`the microprocessor sets one of the storage elements of
`the volatile access control memory for enabling user
`access to block data.
`
`20 Claims, 8 Drawing Sheets
`
`r-
`
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`-43
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`SECURITY LOGIC
`
`SECURITY
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` 5
`
`

`
`U.S. Patent
`
`Aug. 15, 1995
`
`sheet 5 of 8
`
`5,442,704
`
`INITIALIZATION
`RESET TO
`ZERO
`
`TYPE OF COMMAND
`START INST.
`STEP INST.
`NO ACTION
`LOAD WITH
`Oth BIT
`OF BLOCK
`(LMBO)
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`RESET TO
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`RESET TO
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`RESET TO
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`BLOCK LOCK MEMORY
`OUTPUT BIT COMPARES
`(EQUALS) TO
`PRESENTED BIT OR
`ELSE RESET TO ZERO
`(cid:127) NO ACTION IF
`ADDRESSED BLOCK
`LOCK MEMORY
`OUTPUT BIT COMPARES
`(EQUALS) TO
`PRESENTED BIT OR
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`
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`ADDRESS
`LATCH
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`NOT
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`SIGNIFICANT
`
`LOAD WITH
`FIRST BIT OF
`BLOCK
`(LMBO)
`LOAD MOST
`SIGNIFICANT
`BITS OF
`ADDRESS
`FROM INST. &
`MAKE MIDDLE
`SIGNIFICANT
`BITS ZERO
`
`ACTION TABLE
`
`Fig. 5
`
` 6
`
`

`
`U.S. Patent
`
`Aug. 15, 1995
`
`Sheet 6 of 8
`
`5,442,704
`
`1st LOADING OR
`FABRICATION
`
`600
`
`1st BLOCK
`
`ERASE BLOCK
`
`ÿ602
`
`/ PROTECT \
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`CONTENTS
`
`A NEXT
`BLOCK?
`
`ÿ614
`
`616
`
`Fig.6a
`
` 7
`
`

`
`U.S. Patent
`
`Aug. 15, 1995
`
`Sheet 7 of 8
`
`5,442,704
`
`NORMAL
`POWER UP
`
`INITIALIZE
`(cid:127)CLEAR ACM43
`(cid:127)RESET END CTR
`(cid:127)ACCUM FLIP-FLOP
`ETC.
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`
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`-624
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`626
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`
`YES
`
`A NEXT BLOCK?
`
`-638
`
`END
`
`Fig. 6b
`
` 8
`
`

`
`U.S. Patent
`
`Aug. 15, 1995
`
`Sheet 8 of 8
`
`5,442,704
`
`SELECTIVE
`BLOCK ERASE
`
`ADDRESS SELECTED
`BLOCK
`
`640
`
`(cid:127)ERASE BLOCK
`(cid:127)SET LOCK WRITE
`ALLOW F/F
`
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`
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`
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`
`4 NO
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`
`ÿ-650
`
`-652
`
`LOAD BLOCK
`CONTENTS
`
`ÿ656
`
`Fig. 6c
`
` 9
`
`

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`
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`
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`
`SECURE MEMORY CARD WITH PROGRAMMED
`CONTROLLED SECURITY ACCESS CONTROL
`
`2
`device is also under the control of the thief. To make
`matters worse, technology now allows and encourages
`the carrying of enormous amounts of sensitive informa¬
`tion on one's person where it is subject to mishap.
`RELATED PATENT APPLICATION
`Also, today's notebook and subnotebook sized com-
`Puters provide a free standing environment having sig-
`The patent application of Thomas O. Holtey and
`nificant computing power which has created a need for
`Peter J. Wilson entitled, "Secure Memory Card," filed
`additional data storage capability. This need has initially
`on Oct. 14, 1992,bearing Ser. No. 07/960,748, now U.S.
`been met by miniature hard disk devices which can hold
`Pat. No. 5,293,424 which is assigned to the same as-
`10 both programs and data. While password protection is
`signee as this patent application.
`often used in these systems, it does not completely pro-
`The patent application of Thomas O. Holtey entitled,
`tect sensitive data because, first, the authentication
`"A Secure Application Card for Sharing Application
`agent is vulnerable. But, more significantly, the disk
`Data and Procedures Among a Plurality of Micro-
`device containing the data can be physically removed
`processors, filed on Jan. 14, 1994, bearing Ser. No.
`08/181,684, which is assigned to the same assignee as 15 and accessed in a setting more conducive to analysis. In
`this patent application.
`this case, data has been protected by employing some
`form of encryption. The nature of disk access makes this
`...
`.
`BACKGROUND OF THE INVENTION
`.jj ÿ
`d a
`r*t> <-vr txtt-, ai: the txta ;T.,TTTr,vT
`possible without encountering undue cost or perfor-
`1. Field of the Invention
`mance barriers. An example of this type of system is
`This invention relates to the field of portable personal 20 described in U.S. Pat. No. 4,985,920 entitled "Inte-
`computers and more particularly to systems for main-
`grated Circuit Card".
`taining data security in a portable digital information
`The recent emergence of the flash memory and re-
`environment.
`movable "memory cards" have allowed major reduc-
`2. Prior Art
`tions in size and power requirements of the portable of
`The security of personal information has always been
`tjje p0rtable computer. The flash memory combines the
`concern. Historically, it has been safeguarded through
`fiexibiHty of random access memories (RAMs) with the
`the use of signatures credentials and photographs.
`permanence of disks. Today, the combining of these
`Hectromc devices such as automatic banking machines
`technologies allows u t0 20 minion bytes of data to be
`have added encoded cards and personal identification
`in a credlt card size removable
`stQred without
`.
`r '
`numbers (PINs) to the repertoire of security tools. 30
`,
`v
`v
`package. This data can be made to appear to a host
`;.
`.
`,
`r
`Computers continue to use passwords.
`,
`system either as if it were stored on a conventional disk
`*(cid:127)
`,
`...
`. .
`/ .
`More recently, the Smart Card has been used as a
`drive or if it were stored in an extension of the host
`~
`,
`security tool. Ine omart Card is a small microcom-
`system s memory.
`,
`puter with writable, non-volatile memory and a simple
`Jhese technological developments havemade further
`input/output interface, fabricated as a single chip and 35
`reductions m system size possible to the extent that the
`embedded in a plastic "credit card". It has exterior pins
`system and data can be earned on one s person. This has
`to allow it be connected to specially designed equip-
`made the data and its host system more vulnerable to
`ment. The program contained in the card's microcom-
`*oss or t eÿ and also more difficult to protect memory
`puter interacts with this equipment and allows its non-
`volatile memory data to be read or modified according 40 data by encryption since this presents major cost and
`performance barriers.
`to a desired algorithm which may optionally include a
`Accordingly, it is a primary object of the present
`password exchange. Special techniques have been im-
`invention to provide a portable digital system with a
`plemented to protect the memory data and to allow
`secure memory subsystem.
`permission variations according to the situation. For
`11is a further object of the present invention to pro-
`example, U.S. Pat. No. 4,382,279 entitled, "Single Chip 45
`vide a memory card whose contents can be protected if
`Microprocessor with On-Chip Modifiable Memory"
`removed from a portable digital system.
`discloses an architecture which permits automatic pro-
`ft is still a further object of the present invention to
`gramming of a non-volatile memory which is included
`provide a memory card in which the data contents of
`on the same chip as a processing and control unit. As in
`other systems, the microprocessor only protects mem- 50 the chips of the card are protected if removed from
`such card.
`ory on the same chip.
`It is a more specific object of the present invention to
`The "Smart Card" has been usedbothto facilitate the
`provide a secure memory subsystem which can be eas-
`process of identification and to be the actual site of the
`ily fabricated due to simplicity in design.
`valued information. In this situation, as in most prior
`situations, physical presence of a "key" as well as some 55
`SUMMARY OF THE INVENTION
`special knowledge has been used as part of the verifica¬
`The above and other objects of the present invention
`tion or authentication process. Insuch cases, identifica-
`are achieved in the preferred embodiment of a secure
`tion has involved a dialog between the person desiring
`memory card described in the above reference related
`access and a fixed agent such as a security guard and an
`60 patent application to Thomas O. Holtey, et al. The
`automatic teller machine.
`secure memory card includes a microprocessor on a
`The current state of portability of free standing com-
`single semiconductor chip and one or more non-volatile
`puting devices makes it possible for both the physical
`addressable memory chips. The microprocessor chip
`key and the authentication agent to be small, portable
`and non-volatile memory chips connect in common to
`and hence more subject to loss or theft. Further, com-
`puting devices make it possible to perform repeated 65 an internal bus for transmitting address, data and con-
`trol information to such non-volatile memory chips.
`attempts to guess or deduce the special knowledge or
`The microprocessor
`passwords associated with the identification process.
`includes an addressable non-
`This is especially true if the authentication agent or
`volatile memory for storing information including a
`
` 10
`
`

`
`number of key values and program instruction informa¬
`tion for controlling the transfer of address, data and
`control information on the internal bus.
`According to the teachings of the present invention,
`the chip memory is organized into a number of blocks,
`each block having a number of rows, each containing a
`plurality of addressable byte locations. Each row fur¬
`ther includes a single lock bit location which collec¬
`tively with the other row lock bit locations provide
`storage for a significant number of lock bits within each
`block with little increase to the size of the chip memory.
`The lock bits are uniquely coded to utilize a predeter¬
`mined characteristic of the non-volatile memory which
`ensures data protection.
`Also, according to the present invention, each mem¬
`ory chip is constructed to include security control logic
`circuits which include a volatile access control memory
`having a plurality of access control storage elements
`and a programmable security access control unit con¬
`taining a small number of circuits for carrying out a key
`validation operation. More specifically, under the con¬
`trol of a predetermined set of instructions, the security
`access control unit performs a predetermined key vali¬
`dation operation for a protected block by serially com¬
`paring the bits of a key value against the bit contents of
`lock bit positions of the memory block read out in re¬
`sponse to such instructions.
`This validation operation is carried out with a host
`computer as part of a predetermined authentication
`procedure. It is only after the successful performance of
`such procedure, can the microprocessor set the associ¬
`ated volatile access control memory access control
`element of a block for enabling the user access to read
`out information from the protected block.
`As in the case of the related patent application, peri¬
`odically, the user can be required to successfully per¬
`form an authentication procedure with the host com¬
`puter, and allowed to continue reading information as
`allowed by the access control memory. Inthe preferred
`embodiment, the host computer couples to the memory
`card through a standard interface such as an interface
`which conforms to the Personal Computer Memory
`Card International Association (PCMCIA) standards.
`The security logic circuits of the preferred embodi¬
`ment contain a minimum amount of logic circuits which
`include a number of lock bit locations corresponding to
`one per memory row of each block, an end counter, a
`comparator and a compare accumulation flip-flop and
`an access control memory containing one bit location or
`flip-flop for each memory block. The end counter is
`used to count successive ONE bits in the lock bit loca¬
`tions of a block for detecting the end of a stored key
`value. The comparator and compare accumulation flip-
`flop respectively, compares each data bit presented by
`an instruction to the lock bit stored in a corresponding
`one of the lock bit locations and accumulates the result
`of the series of successive comparisons made therebe¬
`tween.
`The present invention eliminates the need for parallel
`data paths, parallel data comparators and large register
`widths for storing long key values selected to provide
`greater protection against guessing. In the preferred
`embodiment, each block can provide a maximum key
`length of 8 kilobits. This is done without having to be
`concerned with the problems of providing wider paral¬
`lel paths or large register widths. Further, with the
`speed of today's microprocessors, the time required to
`process large key lengths remains well under the sub-
`
`50
`
`+2,704
`
`30
`
`4
`second range. Moreover, such processing normally
`only takes place during system initialization.
`According to the teachings of the present invention,
`the key values are selected so that the first bit of every
`5 key value is set to a predetermined state which utilizes
`a predetermined characteristic of the memory chip.
`More specifically, in the memory of the preferred em¬
`bodiment, when the memory is erased all bits are set to
`ones and writing into the memory can only change the
`10 ones to zeros but can not change the zeros back to ones.
`The present invention uses this characteristic by requir¬
`ing that the first bit of every key be set to this predeter¬
`mined state (i.e. zero) which will serve as the protection
`bit for each block. Further, the keys are coded accord-
`15 ing to a predetermined protocol which further ensures
`protection. In the preferred embodiment, the protocol
`uses rules similar to those utilized in a well known com¬
`munications protocol such as the High-level Data Link
`Control (HDLC) communications protocol. That is,
`20 each key value bit sequence is coded to contain less than
`a predetermined number of successive ONE bits with
`the exception of a flag field which contains the prede¬
`termined number of successive ONE bits. If any bits of
`the end code are tampered with, it will not be possible
`to detect the end of the key value and gain access to a
`particular block. And, if any other bits of the key value
`are tampered with, there will be a mismatch between
`the lock and key values preventing access.
`Also, according to the present
`invention, a small
`number of different types of instructions are utilized to
`carry out a key validation operation. These include a
`first type of instruction which is performed once by the
`microprocessor to begin a key validation operation. If
`35 the memory block is not protected, this is the only in¬
`struction required to be executed. The microprocessor
`executes a second type of instruction, one for each bit in
`the sequence of key bits. Each second type of instruc¬
`tion causes one bit of the key bit sequence to be com-
`40 pared with a corresponding lock bit of the sequence of
`lock bits stored in the block lock bit locations. The
`microprocessor completes the key validation operation
`by executing a third type of instruction. This instruction
`causes the sampling of the accumulated comparison
`45 result stored in the accumulation comparison flip-flop,
`tests the end counter, and sets the block access control
`memory bit only when the results are correct (i.e. when
`the counter and accumulation comparison flip-flop are
`in the correct states).
`Also in the preferred embodiment, the same set of
`instructions can be modified when required to be used
`during the fabrication of the memory card or during a
`selective block erase operation. That is, instead of read¬
`ing out the bits of a key value, the instructions can be
`55 used to cause the writing of the key value bit sequence
`into the lock bit positions of a memory block following
`an erase operation.
`The present invention expands the capabilities of the
`secure card of the related patent application by provid-
`60 ing an independent lock for each block of memory.
`Also, it permits the use of variable length key values as
`a function of the amount of protection to be accorded to
`the information being protected. Further, the present
`invention requires substantially less circuitry, making it
`65 easier to construct and less costly. As in the case of the
`related patent application, it melds the "Smart Card"
`and "memory card" technologies which is key to allow¬
`ing the protection of large amounts of data made possi-
`
` 11
`
`

`
`ble by flash memory technology inthe "security harsh"
`environments created by electronic miniaturization.
`The present invention also retains the features of the
`secure card of the related patent application relative to
`being capable of operating in both secure and non¬
`secure modes, eliminating the need for encrypting and
`decrypting data, and protectingmemory data ifthe card
`or its host processor is lost, stolen, powered off or left
`unattended. In the event of theft, the memory data is
`protected from access even if the memory card is
`opened and probed electronically or the memory chips
`are removed and placed in another device.
`The above objects and advantages of the present
`invention will be better understood from the following
`description when taken in conjunction with the accom¬
`panying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1is a block diagram of a system which incorpo¬
`rates a memory card constructed according to the pres¬
`ent invention.
`FIG. 2 shows in greater detail, the access control
`processor (ACP) of FIG. Iincluding the organization
`of its non-volatile memory.
`FIG. 3 shows in block diagram form the standard
`flash memory of FIG. 1 modified according to the
`teachings of the present invention.
`FIG. 4 shows in greater detail, the flash memory of
`FIG. 3 constructed according to the teachings of the
`present invention.
`FIG. 5 is a table used to explain the operation of the
`memory card of the present invention.
`FIGS. 6a through 6c are flow charts used to explain
`the modes of operation of the memory card of the pres¬
`ent invention.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`FIG. 1is a block diagram of a secure portable hand¬
`held computing system 1usable as a personal computer
`or as a transaction processor. System 1includes a mem¬
`ory card 3 constructed according to the present inven¬
`tion which connects to a host processor 5 by a bus 102.
`The host processor 5 may take the form of a palm top
`personal computer, such as the HP 95LX manufactured
`by Hewlett-Packard Company. The host processor 5
`includes a liquid crystal display (LCD) 5-2, a keyboard
`5-4, a memory 5-8, and a serial interface 5-10, all cou¬
`pled in common to a bus 106. The memory 5-8 includes
`a one megabyte read only memory (ROM) and a 512
`kilobyte random access memory (RAM).
`The connection between the memory card 3 and host
`processor 5 is established through a standard bus inter¬
`face. In the preferred embodiment, the bus 102 con¬
`forms to the Personal Computer Memory Card Interna¬
`tional Association (PCMCIA) standard. The interface
`102provides a path for transferring address, control and
`data information between host processor 5 and the
`memory card system 3 via a standard interface chip 104
`and a memory card bus 105. Each of the buses 102, 105,
`and 106 include a data bus, a control bus and an address
`bus and provide continuous signal paths through all like
`buses. For example, bus 105 includes address bus 105a,
`data bus 1056, and control bus 105c.
`The PCMCIA bus standard has evolved from a stan¬
`dard which supports disk emulation on memory cards
`to a substantially different standard which allow ran¬
`dom access to memory data. The memory card of the
`
`1-2,704
`
`35
`
`6
`invention provides a protection technique
`present
`which supports this new standard by providing rapid
`access to random memory locations without resort to
`encryption techniques. By controlling the data paths
`5 which carry the data from the memory array to the
`host, the memory card of the present invention protects
`the data without imposing any time-consuming buffer¬
`ing, decryption or other serial processing in this path.
`Typically, a user operates system 1from the key-
`10 board 5-4 to perform the typical operations such as
`spreadsheet and database functions which display infor¬
`mation on display 5-2 and update information stored in
`files in memory card 3. The host processor 5 sends
`address information over bus 102 to retrieve informa-
`15 tion and if desired, updates the information and sends it,
`along with the necessary address and control informa¬
`tion back to memory card 3.
`As shown, in FIG. 1, the memory card 3 of the pres¬
`invention includes an access control processor
`ent
`20 (ACP) 10 which couples to bus 105 and a number (n) of
`CMOS flash memory chips 103a through 103/:, each
`coupled to bus 105.ACP 10is typically the same type of
`processing element as is used in the "Smart Card". The
`CMOS flash memories 103a through 103/: may take the
`25 form of flash memory chips manufactured by IntelCor¬
`poration. For example, they may take the form of the
`Intel flash memory chip designated as Intel 28F001BX
`1M which includes eight 128 KilobyteX 8-bit CMOS
`flash memories. Thus, a 4 Megabyte flash memory card
`30 could include 32 such flash memories (i.e. n=32). For
`further information regarding flash memory compo¬
`nents, reference may be made to the article entitled,
`"Flash Memory Goes Mainstream," published in the
`October, 1993 issue of the IEEE Spectrum publication.
`ACCESS CONTROL PROCESSOR 10
`FIG. 2 shows inblock diagram form, the access con¬
`trol processor (ACP) 10 of the preferred embodiment.
`As shown, ACP 10 includes a protected non-volatile
`40 memory 10-2, a random access memory (RAM) 10-4, a
`microprocessor 10-6, an interval counter 10-8 and an
`interface block 10-10 connected to bus 105. Non¬
`volatile memory 10-2 dedicates a number of addressed
`locations in which to store authentication information
`45 and programs. More specifically, memory locations
`10-2a store one or more personal identification numbers
`(PINs), protocol sequences or other identification infor¬
`mation for verifying that the user has access to the
`system, and for identifying the blocks inflash memories
`50 103a through 103/: that the user may access in addition
`to a time interval value used for reauthentication.
`Memory locations 10-26 store the key values used for
`protecting each of the flash memories 103a through
`103/: or the codes used to protect the individual blocks
`55 of each of the flash memories 103a through 103n. Mem¬
`ory locations 10-2c store the program instruction se¬
`quences for performing the required authentication
`operations and for clearing the system if the preset
`conditions for failure are met.
`Certain program instructions enable the user to con¬
`trol the setting of the interval counter 10-8 which estab¬
`lishes when user reauthentication takes place. The reau¬
`thentication interval defines the time between interrup¬
`tions and for sending an interrupt to the host processor
`65 5 requiring verification of the user's identity by having
`the user reenter the PIN or other password. The inter¬
`val counter 10-8 receives clock pulses from the host
`processor 5 over bus 102 and can be set by the user
`
`60
`
` 12
`
`

`
`5,442,704
`
`... „ .ÿ
`
`1
`
`lA
`
`w
`
`x
`
`; . ...... ,
`
`8
`7
`The write state machine 61 controls the block erase
`according to the work environment. For example, at
`and program algorithms. The program/erase voltage
`home, the user may turn the timer off (i.e., set it to a
`system 62 is used for erasing blocks of the memory
`maximum value), or set the time interval to one hour.
`array 54 or the programming bytes of each block as a
`On an airplane the user may set it for ten minutes for
`increased protection. The user can be prompted to re- 5 function of the voltage level of VPP.
`.
`examine the setting of this interval at every "power on"
`„
`....
`.
`.
`Security Section 1038
`f
`thereby forcing periodic reauthentication to enforce
`As seen from FIG. 3, section 103S includes a security
`security.
`access control unit 30, shown ingreater detail in FIG. 4,
`FLASH MEMORIE8 103a through 103n
`io a lock write allow storage element 32, and a volatile
`access control memory 43 interconnected as shown.
`FIG. 3 shows in block diagram form, flash memory
`The output of the access control memory 43 is applied
`103a which is identical in construction to the remaining
`as an enabling input to output buffer 52 during each
`flash memories 1036 through 103a. As shown, memory
`memory read cycle when the contents of a byte location
`103a includes two sections, a memory section 103M
`organized according to the present invention and a 15 of any block of memory array 53 is being read out. That
`is> a read cycle may occur> however, the data read out
`security logic section 103S containing the security ac-
`18 inhibited from passing through output buffer 52 m the
`cess control circuits of the present invention. Both sec-
`absence of the appropriate block's access control mem¬
`tions are shown in greater detail in FIG. 4.
`ory gating signal.
`Memory Section 103M
`20 More specifically, in the preferred embodiment, ac-
`control memory 43 includes sixteen individually
`As seen from FIG. 3, section 103M includes a mem-
`addressable bit storage elements, an input address 4 to
`ory array 54 organized into sixteen blocks as shown in
`\6 blt decoder connected to the input of each storage
`FIG. 4, a command register 50, input/output logic cir-
`eleme?t and a 1 t0
`output multiplexer circuit con-
`cuits 60, an address counter 56, a write state machine 61,
`M 25 nected to the output 01 each storage element. The tour
`...
`~
`an erase voltage system 62, an output multiplexer 53, a
`«x-
`high or most significant bits of each address of certain
`r_-
`.i_-.r
`i.jj
`hirrh /\r mnor pi/mirtoitir hirr /~\ r anoh oddr/src nr /Marroin
`A
`data register 55, an input buffer 51, an output buffer 52,
`. . „
`'
`.
`types of instructions added to the set of memory com-
`*
`,. , ,
`,
`, ,, ,
`and a status register 58, arranged as shown. The basic
`. .
`r_ ,
`,.
`, ,
`® „
`mands described herein, are decoded and used to select
`,
`logic circuits of flash memory 103a, as discussed above,
`. ,
`,
`the storage element for the block whose contents are to
`f
`take the form of the type of circuits included m flash 3Q be chan d similarI
`the same four bits are used t0
`memories manufactured by Intel Corporation Since
`sdect the
`{ of the
`g dement for the block
`such circuits can be considered conventional in design,
`containi
`location bei
`the me
`read.
`they will only be described to the extent necessary. For
`It wi]1 be notgd that {his sectIon receives command
`further information regarding such circuits, reference
`control signals designated by various hexadecimal val-
`may be made to the publication entitled, "Memory 35 Ues (i.e. 31Hthrough 33H) from command register 50 of
`Products, O