United States Patent
`
`1191
`
`[11]
`
`Patent Number:
`
`5,081,454
`
`llll111l1|11l11|1111111111111111111
`USO05081454A
`
`
`
`
`
` Campbell, Jr. et al. [45] Date of Patent: Jan. 14, 1992 '
`
`[54] AUTOMATIC A/D CONVERTER
`0pERAT1Oj\' USING PROGRAMMABLE
`
`75
`
`[
`
`]
`
`I
`
`nvemors
`
`D_
`
`341/122
`6/1987 Naito
`4,677,422
`341/141
`.
`6/1990 Hauge el al.
`4,933,676
`6/1990 Kommer ........................... .. 341/1 18
`4,937,575
`Primary Exam1'ner——A.
`Pellinen
`b 11 J .. ‘V-“'
`: J 1 D. C
`Assistant Examiner—’1\/Iarc S. Hoff
`filugon; M121}? 1: i,{e:,_;1e, £1119;-I
`iidttorney, Agent, or F1rm—Wa1t Nielsen; Jonathan P.
`Austin’ Tex
`eyer
`[57]
`ABSTRACT
`[73] Assignee: Motorola, Inc., Schaumburg, I11.
`.
`.
`.
`.
`.:
`,22
`An analog~to-digital conversion system module and
`[21] App} No
`577
`2
`method provides programmable times for sampling
`[22] Filed:
`561?-411990
`analog input signals. Software involvement
`is mini-
`H03M 1/12
`[5]]
`Int C15
`[52] us. ci. C7"'""""""'Tfffffffffffffff"iii/141;341/155 Wed 13>] P'°Vid%n3, 3 °°mma“f W.°rd Wllllich in°1“d=S
`
`[531 Field of Search .................:...... 341/122, 141, 155
`aar:;'S‘tI:;o‘r1“r;:m'{)r: t:‘;11T;m1§‘;‘:
`.
`y
`,
`1561
`References Cited
`command word or words may specify the conversion
`U15. pA-1-ENT DOCUMENTS
`time per analog input channel or group of channels];agd
`3,821,696
`6/1974 Hm ................................ 341/14.
`§;,§;“g;;:;g7,<;;;°§g,;rS;;;';;;qlggjgggoggggggog
`4,264,898
`4/1981 Barman et al.
`.. 341/141
`d
`d (CCWP) E hpccw d .
`1
`4,338,665
`7/1982 Aono et al.
`341/141
`°°“‘.““"“ W“ 5
`.
`5:
`3°
`.
`°5‘g““ f“ °°“'
`4381498 4/1983 Goodale
`341/141
`version parameters including the input sample time.
`4,613,848 10/1936 Parfitt ............
`341/141
`4,654,632
`3/1987 Yoshida et al.
`................... .. 341/141
`
`27 Claims, 14 Drawing Sheets
`
`
`
`
`
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`mm
`53
`8
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`
`CONTROL REGISTER I
`
`AND LOGIC
`
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`| I
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`33
`57
`55
`DATA FORMAT fl
`i
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`31
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`EXTERNAL
`TRIGGER
`
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`35
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`VDDA
`37
`
`VD
`SSA
`
`BUS INTERFACE
`UNIT
`
`Apple 1043
`
`U.S. Pat. 9,189,437
`
`Apple 1043
`U.S. Pat. 9,189,437
`
`

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`

`
`U.S. Patent
`
`Jan. 14, 1992
`
`Sheet 4 of 14
`
`5,081,454
`
`SIGNAL NAME
`
`MNEMONIC
`
`[MB I/0
`
`SYSTEM CLOCK
`MASTER REsET
`SYSTEM REsET
`FREEZE
`TEsT
`INTERNAL PERIPHERAL SELECT
`UUUULE MAPPING
`
`I
`
`'
`
`I
`
`-
`
`FUNCTION CODES
`CYCLE START
`NRITE
`ADDRESS BUS
`ADDRESS STROBE
`ADDRESS ACKNOWLEDGE
`SIZE
`DATA STROBE
`
`DATA BUS
`DATA TRANSFER ACKNOWLEDGE
`BUS ERRoR
`
`INTERRUPT REQUEST LEVEL
`INTERRUPT ARBITRATION
`
`ICLOCK
`INsTRsTB
`ISYSRSTB
`IFREEZEB
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`INUUNAP
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`IASB
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`IDSB
`
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`IDTAC B
`IBERRB
`IRQ[7:1]
`IARB[1:0]
`
`FIG. 5
`
`75 —,
`
`INPUT TRoN INB
`INPUT ERoN IMB
`INPUT ERUN IUB
`INPUT FROM INB
`INPUT FROM IUB
`INPUT ERUU INB
`INPUT FROM IUB
`
`INPUT ERUN IUR
`INPUT ERoU IMB
`INPUT ERou IMB
`INPUT FROM IUB
`INPUT TRoN INB
`OUTPUT To IUB
`INPUT FROM IUB
`INPUT ERoN IHB
`
`INPUT/oUTPUT ERUN/To IHB
`UUTPUT To IUB
`OUTPUT To INB
`oUTPUT To TUB
`INPUT/oUTPUT FROM/T0 IMB
`
`FIG. 41
`
`
`
`RESERVED
`
`.
`
`CONVERSION CONNAND WORD TABLE
`32 WORDS
`
`8x000
`
`80{
`
`SXOZO
`81
`
`‘ GAO
`X 83
`
`‘
`
`‘ 120
`X 85
`
`3 1A0
`X 89
`
`RESERVED
`CONVERSION RESULT TABLE: RIGHT JUSTIFIED DATA:
`
`32 WORDS
`
`
`
`RESERVED
`CONVERSION RESULT TABLE. LEFT JUSTIFIED. SIGNED DATA:
`
`
`32 WORDS
`
`
`
`
`
`RESERVED
`CONVERSION RESULT TABLE, LEFT JUSTIFIED, UNSIGNED DATA:
`
`32 WORDS
`
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`

`
`U.S. Patent
`
`Jan. 14, 1992
`
`Sheet 7 of 14
`
`84
`
`A/D
`CONVERTER
`
`
`
`FIRST CONVERSION
`.COMMAND
`
`FIRST RESULT
`WORD
`
`rCONVEEflON
`
`flmflmflfl)WDRD(0fiW
`SBHS
`
`0 BEGIN QUEUE 1
`
`BQ2 BEGIN QUEUE 2
`
`REHHE
`
`REGEHERS
`NBHS
`
`BEGIN QUEUE 1
`
`O
`
`BEGIN QUEUE 2
`
`
`
` SECOND
`
`CONVERSION
`COMMAND
`
`SECOND
`RESULT
`WORD
`
`62
`
`64
`
`FIG. 8
`
`

`
`U.S. Patent
`
`Jan. 14, 1992
`
`Sheet 8 of 14
`
`5,081,454
`
`CCW
`CHAN
`BITS
`
`‘
`
`-
`
`MUX=00
`INTMUX
`CHANNEL
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`
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`CHANNEL
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`
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`EXTMUX.
`CHANNEL
`SELECTED
`
`00000
`
`END OF OUEUE
`
`END OF OUEUE
`
`END OF OUEUE
`
`END OF QUEUE
`
`ETRIG1/AN1
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`ANY
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`

`
`U.S. Patent
`
`Jan. 14, 1992
`
`Sheet 9 of 14
`
`5,081,454
`
`Illllllllllllllll
`
`RIGHT JUSTIFIED, UNSIGNED
`
`RESULT
`
`LEFT JUSTIFIED, UNSIGNED
`
`RESULT n
`
`LEFT JUSTIFIED, SIGNED
`
`RESULT -.
`
`35
`
`37
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`as
`
`FIG. 11
`
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`
`suvv me
`
`92
`
`FIG. 12
`
`FIG. 13
`
`SUPERVISOR
`SPACEONLY
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`94
`
`MODULE CONFIGURATION REGISTER
`
`TEST REGISTER
`INTERRUPT REGISTER
`
`PORTS A 6: B DATA REGISTER
`
`PORTS A & B DATA DIRECTION REGISTER
`
`CONTROL REGISTER O
`CONTROL REGISTER 1
`CONTROL REGISTER 2
`STATUS REGISTER
`
`RESERVED
`
`

`
`U.S. Patent
`
`Jan. 14, 1992
`
`Sheet 10 of 14
`
`5,081,454
`
`15
`
`8
`
`an 96
`
`7
`
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`
`98
`
`FIG. 14
`
`15
`
`8
`
`102
`
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`
`7
`
`104
`
`FIG. 15
`
`APB - PORT B INPUT DATA
`
`15
`
`A
`
`8
`
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`
`7
`
`108
`
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`
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`
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`
`15
`
`— IST1
`
`8
`
`110
`
`7
`
`0
`
`— PRES
`
`112
`
`FIG- 17
`
`

`
`U.S. Patent
`
`Jan. 14, 1992
`
`Sheet 11 of 14
`
`5,081,454
`
`15
`
`8
`
`cxajmmn
`
`7
`
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`
`FIG- 18
`
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`
`15
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`8
`
`cm
`
`7
`
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`
`124
`
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`
`FIG. 20
`
`

`
`U.S. Patent
`
`Jan. 14, 1992
`
`I Sheet 12 of 14
`
`5,081,454
`
`D
`
`fig
`gg
`55
`
`.:
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`OADC RESULT REG 0 RsLTo)
`OADC RESULT REG 1
`RSLT1)
`QADC RESULT REG 2 RSLT2
`QADC RESULT REc 3 RSLT3
`323% IESBII REE:
`I333
`QADC RESULT REG 6 RSLT6
`OADC RESULT REc 7 RSLT7
`I
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`
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`
`I I
`
`QADC RESULT REG 0
`RSLTO)
`QADC RESULT REG 1
`RSLT1)
`OADC RESULT REc S2 RSLT2
`OADC RESULT REG 3 RSLT3
`QADC RESULT REG 4 RSLT4
`OADC RESULT REG5 RSLT5
`QADC RESULT REG 6
`RSLT6
`OADC RESULT REG 7 RSLT7
`I
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`

`
`U
`
`Jan. 14, 1992
`
`Sheet 13 of 14
`
`5,081,454
`
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`
`U.S. Patent
`
`Jan. 14, 1992
`
`Sheet 14 of 14
`
`5,081,454
`
`FROMRESULTS
`
`
`
`TABLE(10BITS)
`
`
`
`BUST0INTERMODULEBUS
`
`DATAI/0BUFFERS(16BITS)
`
` BUS
`
`

`
`1
`
`5,081,454
`
`AUTOMATIC A/D CONVERTER OPERATION
`USING PROGRAMMABLE SAMPLE TIME
`
`RELATED INVENTIONS
`
`1. Automatic Selection of External Multiplexer
`Channels By A/D Converter Integrated Circuit,
`in-
`vented by Jules D. Campbell, Jr. et al., U.S. Ser. No.
`07/577,249, filed concurrently herewith and assigned to
`the assignee of the present invention.
`2. Automatic A/D Converter Operation Using A
`Programmable Control Table, invented by William D.
`Huston et al., U.S. Ser. No. 07/577,223, filed concur-
`rently herewith and assigned to the assignee of the pres-
`ent invention.
`3. Automatic A/D Converter Operation With Select-
`able Result Format, invented by Jules D. Campbell, Jr.
`et al., U.S. Ser-. No. 07/577,247, filed concurrently here-
`with and assigned to the assignee of the present inven-
`tion.
`
`TECHNICAL FIELD OF THE INVENTION
`
`This invention relates generally to analog-to-digital
`converters, and, more particularly,
`to an A/D con-
`verter system which provides programmable times for
`sampling analog signals.
`BACKGROUND INFORMATION
`
`The present invention has utility in applications re-
`quiring the conversion of an analog signal into a digital
`signal, for example for computer sensing of analog in-
`formation in an automotive control system. To further
`illustrate,
`in an automotive engine control system, a
`microcomputer requires analog signal information from
`various transducers to be converted into digital signal
`information before it can be processed by the mi-
`crocomputer. Examples of such analog signal informa-
`tion are the outputs of sensors for manifold pressure,
`oxygen, rotational speed, operator input, battery volt-
`age, anti-knock, etc.
`In a typical automotive application, many different
`analog signals need to be converted. The analog signals
`originate from many different sources and typically
`have different source impedances.
`Most known A/D converter systems have a fixed
`input sample time which is determined by the hardware
`design of the system. The sample time should be some
`multiple (such as 10) of the “RC” time constant to en-
`sure sampling to the desired accuracy. In an unbuffered
`charge distribution A/D converter system, a fixed sam-
`ple time places restrictions on either the conversion
`time or the source impedance.
`In prior art A/D converter systems, high impedance
`sources often require amplifying or long sample times,
`which could be adversely affected by rapidly changing
`signals. Long sample times also restrict the number of
`samples per second that can be converted. Short sample
`times require low source impedances, which constrain
`the driving circuitry.
`A known A/D converter system (TI TMS37O avail-
`able from Texas Instruments Corp.) utilizes software
`control bits by which processor software initiates sam-
`pling and then the software initiates conversion a mea-
`sured time later. This is unduly burdensome on the host
`system software.
`Thus there is a significant need to provide an A/D
`converter system with a variable sample time in which
`the host system software is freed from the responsibility
`
`2
`of initiating the sampling operation and later the con-
`version operation.
`BRIEF SUMMARY OF INVENTION
`
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`The present invention fulfills the above-mentioned
`requirement by providing an A/D converter system
`and method in which a sampling operation on each of a
`plurality of analog channels may be initiated automati-
`cally by the A/D converter module, and a conversion
`operation is subsequently initiated, without involving
`the main system CPU. It should be understood that the
`term “module" is used herein to indicate either an inte-
`grated circuit or a portion of an integrated circuit.
`In a preferred embodiment, the A/D converter mod-
`ule is provided with means for storing information re-
`garding sample time. The storage means may be imple-
`mented in a number of different ways, taking the form,
`for example, of a single register, multiple registers, a
`table in memory, etc.
`In a preferred embodiment the sample period infor-
`mation is stored in one or more automatic conversion
`sequences or queues. Each queue specifies a sequence of
`sampling operations on one or more channels.
`A queue comprises a table of Conversion Command
`Words (CCW’s) stored in memory, located either in the
`A/D converter or in the CPU address space. Regarding
`the present
`invention, each CCW contains an input
`sample time field (IST);
`in addition, other fields are
`provided to control such parameters as analog channel,
`reference selection, conversion resolution, result data
`justification, and so on.
`In general, the host system software programs the
`characteristics of the queued operation during a soft-
`ware initialization sequence. Thereafter,
`the queues
`execute autonomously, depending upon the external
`system or internal module events which have been pro-
`grammed to initiate the conversion sequences.
`One or more bits in the CCW and/or in a control
`register can be pre-programmed to vary the input sam-
`ple time. The sample time can be varied in numerous
`ways——e.g. per channel or group of channels, per con-
`version, per conversion scan, and so forth.
`Programmable sample time allows operation without
`a loss of accuracy and a higher overall conversion
`throughput. It
`is particularly useful for applications
`with widely varying source impedances.
`The A/D converter can issue an interrupt when the
`conversion scan sequence is complete, allowing the host
`system software to read the results.
`Thus the present invention frees the host system soft-
`ware from the responsibility of initiating the sample and
`conversion operations of the A/D converter.
`The present invention also allows the flexibility of
`working with a range of source impedances and a
`charge-redistribution capacitive D/A converter. The
`invention enables operation with higher source imped-
`ances without a loss of accuracy.
`Accordingly, it is an object of the present invention
`to provide an A/D converter system and method which
`control the duration of the sampling of analog inputs
`while minimizing the involvement of host system soft-
`ware.
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`65
`
`It is another object of the present invention to pro-
`vide an A/D converter system and method in which
`parameters for controlling the input sample times are
`initially loaded into a table or register, and thereafter
`the A/D conversion system autonomously carries out
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`3
`the desired sampling and conversion without further
`involvement of host system software.
`These and other objects are achieved in accordance
`with a preferred embodiment of the invention by pro-
`viding an analog-to-digital conversion system compris-
`ing an analog-to-digital converter, at least one analog
`input terminal, means for reading at least one command
`word, the command word designating an input sample
`time. means responsive to the reading means for sam-
`pling an analog signal on the at least one analog input
`terminal for the duration of the input sample time; and
`means responsive to the sampling means for converting
`the sampled value of the analog signal into a digital
`value.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The invention is pointed out with particularity in the
`appended claims. However, other features of the inten-
`tion will become more apparenfand the invention will
`be best understood by referring to the following de-
`tailed description in conjunction with the accompany-
`ing drawings in which:
`FIG. 1 shows an A/D converter system, comprising
`an A/D converter module and one or more multiplexer
`integrated circuits, in accordance with a preferred em-
`bodiment of the present invention.
`FIG. 2 shows a block diagram ofthe A/D converter
`module of the present invention.
`»
`FIG. 3 shows a block diagram of the Control Regis-
`ter and Logic circuit 60 illustrated in FIG. 2.
`FIG. 4 defines the Intermodule Bus (IMB) signals of
`the A/D converter module of the present invention.
`FIG. 5 shows an address map for the control regis-
`ters, Conversion Command Word table, and the Con-
`version Result Table of the A/D converter module.
`FIG. 6 is a more detailed address map showing the
`formats of the Control, Port, and Status Registers 80
`shown in FIG. 5.
`FIG. 7 shows the format of a Conversion Command
`Word (CCW) of the A/D converter module.
`FIG. 8 is a conceptual diagram showing how Con-
`version Command Words are used to produce Result
`Words which are stored in the Conversion Result Ta-
`ble.
`FIG. 9 is a table illustrating how the CCW CHAN
`bits specify the functions of the various I/O pins for O,
`1, 2, or 3 external multiplexer IC‘s.
`FIG. 10 is a table illustrating the number of analog
`channels available with different numbers of external
`multiplexer IC’s,
`in terms of the number of I/O pins
`allocated to the A/D converter module.
`FIG. 11 illustrates the data format options of Result
`Words stored in the Conversion Result Table.
`FIG. 12 shows the format of the Module Configura-
`tion Register of the A/D converter module.
`FIG. 13 illustrates the use of the SUPV bit of the
`Module Configuration Register of the A/D converter
`module.
`FIG. 14 shows the format of the Interrupt Register of
`the A/D converter module.
`FIG. 15 shows the formats of the Port A and Port B
`Data Registers of the A/D converter module.
`FIG. 16 shows the format ofthe Port A Data Direc-
`tion Register of the A/D converter module.
`FIG. 17 shows the format of Control Register 0 ofthe
`A/D converter module.
`FIG. 18 shows the format of Control Register 1 ofthe
`A/D converter module.
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`FIG. 19 shows the format of Control Register 2 ofthe
`A/D converter module.
`FIG. 20 shows the format of the Status Register of
`the A/D converter module.
`FIG. 21 illustrates the addresses required to read
`Result Words stored in the Conversion Result Table in
`at least three different data format options.
`FIGS. 22A and 22B show a detailed logic implemen-
`tation of the Data Format logic 68 shown in FIG. 2.
`
`DESCRIPTION OF PREFERRED EMBODIMENT
`
`Overview
`
`FIG. 1 shows an A/D converter system, comprising
`an A/D converter integrated circuit (IC) and one or
`more multiplexer integrated circuits. A Queued A/D
`Converter module (QADC) 1 is shown coupled to one
`or more external multiplexers (MUX’s) 10, 12, and 14.
`In a preferred embodiment QADC 1 and the external
`MUX‘s are implemented as integrated circuits. External
`multiplexers are commercially available from Motorola,
`Inc..
`for example,
`as part numbers MCl4051 or
`MC74HC405l.
`The Queued A/D Converter module (QADC) 1 is
`described herein as “queued”, because, as will be de-
`scribed in greater detail below, it operates in response to
`one or more queues of Conversion Command Words.
`QADC 1 comprises a plurality of I/O pins, shown
`generally by reference numeral 2, an analog MUX por-
`tion 4, an analog converter portion 6, and a portion for
`performing control and storing digital results 8.
`The I/O pin configurations of QADC vary from a
`l2-pin version to an 20-pin version. Also coupled to
`appropriate pins of QADC 1 are power supplies V55,;
`and VDDA, references ‘VRHQ and VRLO, alternate refer-
`ences VRH; and VRL1, and external triggers ETRIG1
`and ETRIG2.
`,
`
`Eight of the I/O pins of QADC 1 function as Port A
`I/O pins and are labeled PAO—PA7, while eight others
`function as Port B input pins and are labeled PBO—PB7.
`The prefix “PA” designates Port A, and the prefix
`“PB” designates Port B.
`The external MUX’s 10, 12, and 14 are shown com-
`prising eight analog input channels each. For example,
`MUX 10 has analog input channels AN16, AN18,
`AN20, AN22, AN24, AN26, AN28, and AN30.
`The external MUX’s are addressed via address lines
`MAO-MA2. The prefix “MA" designates Multiplexed
`Address. The outputs of MUX’s 10, 12, and 14 are cou-
`pled to lines ANx, ANy, and ANz, respectively. The
`prefix “AN” designates Analog Input.
`As will be discussed further below, many of the I/O
`pins 2 are programmable to perform multiple functions.
`As will be shown and described below, QADC I
`automatically reads analog signals being input
`into
`MUX’s 10, 12, and 14 and converts the analog values
`into digital values which are stored in the digital results
`portion 8 of QADC 1.
`
`60
`
`QUEUED A/D CONVERTER MODULE
`
`65
`
`FIG. 2 shows a block diagram of the A/D converter
`module of the present
`invention. The Queued A/D
`Converter module (QADC) 1 comprises Port A, indi-
`cated by reference numeral 21, including pins PAO—-
`PA7, and Port B, indicated by reference numeral 22,
`including pins PBO—PB7. Ports A and B are coupled to
`bus 30. A pair of primary reference voltages VRLO 27
`and VRHO 29 are also coupled to bus 30.
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`6
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`5
`Also coupled to bus 30 are a Reference MUX (4:2) 26;
`a Channel MUX (l6:2) 28; an External Trigger circuit
`32; Port A I/O circuit 34; and Port B input circuit 36.
`Address Decode circuit 38 is coupled to Port A 1/0
`circuit 34 and Port B input circuit 36.
`The Queued A/D Converter module 1 comprises a
`10-bit
`successive approximation converter portion
`which includes Sample-and-Hold circuits 40 and 42; a
`2:1 MUX 44; l0-bit Capacitive Digital-to-Analog Con-
`verter
`(CDAC)
`(charge
`redistribution type)
`52;
`Dummy CDAC 54; Comparator 56; and Successive
`Approximation Register (SAR) 58.
`It will be apparent to those of ordinary skill in the art
`that the successive approximation converter may com-
`prise more or fewer than 10 bits. It will also be apparent
`that
`the Digital-to-Analog Converter may be of the
`resistive-only type,
`the capacitive-only type, or the
`resistive/capacitive type.
`Charge Pump and Bias circuit 24 provides bias volt-
`ages to MUX’s 26, 28, and 44.
`to Sample-and-Hold
`circuits 40 and 42, to CDAC 52 and Dummy CDAC 54,
`and to Comparator 56.
`The Queued A/D Converter module 1 further com-
`prises a Bus Interface Unit (BIU) 70 coupled to an Inter-
`module Bus 72. The Intermodule Bus 72, which trans-
`mits clock, data, control, and address information bi-
`directionally, may be coupled to a host data processing
`system (not shown).
`Coupled to Bus Interface Unit 70 via internal address
`bus 31 are_Address Decode circuit 38; Control Register
`and Logic circuit 60; Data Format circuit 68; and Ad-
`dress Decode circuit 66.
`-
`Also coupled to Bus Interface Unit 70 via internal
`data bus 33 are Port A I/O circuit 34; Port B Input
`circuit 36; Control Register and Logic circuit 60; and
`Data Format circuit 68.
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`CONTROL REGISTER AND LOGIC CIRCUIT
`
`FIG. 3 shows a block diagram of Control Register
`and Logic circuit (shown generally within the dashed
`line and indicated by reference numeral 60) and various
`signal paths between it and Bus Interface Unit 70, CCW
`Table 62, Results Table 64, Address Decode circuit 66,
`and other circuitry shown in FIG. 2.
`Control Register and Logic circuit 60 comprises
`Trigger Select & Priority circuit 200, Registers 210,
`Register Control & Decode circuit 220, Interrupt Logic
`230, Queue Control & CCW Addressing circuitry 240,
`and ADC Sample Control & Conversion Control (indi-
`cated generally by reference numeral 250).
`The Trigger Select & Priority circuit 200 is responsi-
`ble for determining the type of trigger for initiating an
`A/D conversion sequence, in response to mode infor-
`matio_n from the Register circuitry 210. It is also respon-
`sible for selecting Queue 1 or Queue 2 for the conver-
`sion sequence in response to control information de-
`coded by the control registers.
`The Trigger Select & Priority circuit 200 is respon-
`sive to external trigger signals ETRIG1 and ETRIG2
`via lines 203 and 204, respectively. Trigger Select &
`Priority circuit 200 is also coupled to the Periodic
`Timer 48 via line 205. Trigger Select & Priority circuit
`200 is responsive to mode control signals from the con-
`trol
`registers via line 213 and to an End-of-Queue
`(EOQ) signal from Queue Control & CCW Addressing
`circuitry 240 via line 242. Trigger Select & Priority
`circuit 200 generates control signals to Queue Control
`& CCW Addressing circuitry 240 via signal path 206.
`It will be understood by those of ordinary skill in the
`art that the terms “signal path” or “line”, as used herein,
`may refer to a single conductor or a multiple-conductor
`bus, or other suitable signal path, as appropriate to the
`implementation.
`Register circuitry 210 comprises the registers shown
`in FIG. 6 and _not otherwise shown in FIG. 2;
`i.e., a
`Module Configuration Register, a Test Register, an
`Interrupt Register, Control Registers 0-2, and a Status
`Register. The function of the Register circuitry 210 is to
`enable the automatic control of the operation of the
`QADC, once the registers are loaded by the host system
`software.
`
`Register circuitry 210 generates control signals to the
`Sample Timer 46 via line 211, to the Prescaler 50 via
`line 212, to Trigger Select & Priority circuit 200 via line
`213, to the Queue Control & CCW Addressing circuit
`240 via line 214, and to Interrupt Logic 230 via line 221.
`Register circuitry 210 receives control signals from
`Register Control & Decode circuit 220 via signal path
`215 and an End-of-Queue (EOQ) signal from Queue
`Control & CCW Addressing circuit 240 via line 242.
`Register circuitry 210 is also coupled to Bus Interface
`Unit 70 via bi-directional bus 217.
`Register Control & Decode circuit 220 receives con-
`trol and address information via busses 218 and 219,
`respectively, from Bus Interface Unit 70 and generates
`control signals to Register circuitry 210 via signal path
`215. The function of Register Control & Decode circuit
`220 is to provide control and addressing circuitry for
`the various registers within Register circuitry 210.
`Interrupt Logic 230 operates to generate an interrupt
`signal to the host CPU upon conclusion of a conversion
`sequence (if enabled). Interrupt Logic 230 receives
`control signals from Register circuitry 210 via signal
`path 221 and an EOQ signal from Queue Control &
`
`Also coupled to Control Register and Logic circuit
`60 are External Trigger 32; Sample Timer 46; Periodic
`Timer 48; Prescaler circuit 50; a random access memory
`(RAM) storing a table of Command Control Words
`(CCW‘s) 62 and a Results Table 64; an Address Decode
`circuit 66; SAR 58; 2:1 sample and hold MUX 44; and
`16:2 Channel MUX 28.
`
`Also coupled to the Queued A/D Converter module
`1 are suitable analog power supply voltages via pins
`VDDA 35 and VSSA 37.
`
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`EXTERNAL PINS
`
`l6 analog channels are
`In a preferred embodiment,
`provided in the internal multiplexing circuitry of the
`QADC module 1. The number of channels available
`externally depends upon package pin availability, and
`whether external multiplexing is employed. The num-
`ber of channels in an expanded, externally multiplexed
`mode is 27 in a preferred embodiment (with a 5-bit
`CCW CHAN field there are also four internal channels
`and an End-of-Queue control word). It should be un-
`derstood by one of ordinary skill
`in the art that the
`channel field may optionally be increased or decreased
`to allow more or fewer channels.
`The QADC module 1 has up to twenty external pins
`as shown in FIGS. 1 and 2. All of these pins except the
`power and reference pins can be used as general pur-
`pose digital port pins. Lower pin-count versions of the
`QADC module 1 can be produced by reducing the
`number of channel/port pins. Versions with as few as
`twelve pins may comprise eight analog channels, two
`power pins, and two reference pins.
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`is also
`It
`CCW Addressing circuit 240 via line 242.
`coupled to the Bus Interface Unit 70 via signal path 231.
`Queue Control & CCW Addressing circuitry 240 is
`responsible for controlling CCW addressing and the
`start of sampling and conversion operations. The Queue
`Control & CCW Addressing circuitry 240 receives
`control signals from the Trigger Select & Priority cir-
`cuit 200 via line 206, from the Register circuitry 210 via
`line 214, and from the ADC Conversion Control circuit
`254 via line 256. It generates control signals to the Trig-
`ger Select & Priority circuit 200, to the Register cir-
`cuitry 210, and to the Interrupt Logic circuitry 230 via
`line 242. It also generates control signals to the Address
`Decode circuitry 66 via line 244, to the ADC Conver-
`sion Control circuit 254 via line 258,_and to the ADC
`Sample Control 252 via line 251.
`ADC Sample Control 252 is responsible for notifying
`the S/H circuits 40 and 42 (refer to FIG. 2), via the
`Sample Timer 46, to begin sampling. It is also responsi-
`ble for notifying the ADC Conversion Control 254
`when sampling is completed. The ADC Sample Con-
`trol 252 receives control signals from Sample Timer 46
`via line 262, from Queue Control & CCW Addressing
`circuit 240 via line 251, and from the CCW Table via
`line 253 (Input Sample Time) and line 255 (Re-sample
`Inhibit).
`It generates control signals to the Sample
`Timer 46 via line 261 and to the ADC Conversion Con-
`trol 254.
`The ADC Conversion Control 254 is responsible for
`initiating a conversion operation by the SAR 58 and for
`informing the Queue Control & CCW Addressing cir-
`cuit 240 upon conclusion of the conversion operation.
`The ADC Conversion Control 254 receives control
`signals from the ADC Sample Control 252. It also re-
`ceives control signals from the Queue Control & CCW
`Addressing circuit 240 via line 258, and it generates
`control signals to the SAR 58 via line 257.
`As shown in FIG. 3, in response to a decoded CCW
`a REF control signal may be transmitted to the REF.
`MUX 26 via line 263, and a CHAN control signal may
`be transmitted to the CHAN. MUX 28 via line 264.
`Upon conclusion of a conversion operation, a digital
`value is transmitted via line 265 from SAR 58 and stored
`in Results Table 65.
`
`INTERMODULE BUS (IMB) INTERFACE
`
`FIG. 4 is a table defining the Intermodule Bus (IMB)
`signals of the A/D converter module of the present
`invention.
`The address bus IADDR and data bus IDATA,
`along with their associated control and handshake lines,
`are used to transfer data between the IMB 72 and the
`QADC module 1.
`The reset signal IMSTRSTB initializes certain regis-
`ter bits to their default states. These default states are
`described inithe register descriptions below. The master
`reset
`signal
`IMSTRSTB and system reset
`signal
`ISYSRSTB are used to reset the BIU (Bus Interface
`Unit) state machine.
`ISIZ and IADDR are used to determine the size of
`data (byte or word). The QADC module 1 has certain
`bits that are only accessible in test mode, and the ITST-
`MODB line is used for test mode operation.
`ADDRESS MAP
`
`FIG. 5 shows an address map (indicated generally by
`reference numeral 75) for the control registers, Conver-
`
`8
`sion Command Word table, and the Conversion Result
`Table of the A/D converter module.
`The QADC module 1 utilizes 512 bytes, or 256
`words, of address space, as shown in FIG. 5. Of the
`words actually implemented, 9 words are control, sta-
`tus, and port registers (indicated generally by reference
`numeral 80), 32 words are Conversion Command
`Words (indicated generally by reference numeral 81),
`and 32 words are used for each data format type ofthe
`result table (indicated generally by reference numerals
`83, 85, and 89, respectively). The remaining words are
`reserved for possible future expansion.
`The first block 80 of the address map 75 contains the
`9 words used for control, status, and port information.
`These permit a h_ost data processing system (not shown)
`to initialize the QADC module 1 into the desired con-
`figuration and mode of operation. Also included are
`status bits that the host system may read to identify an
`interrupt and to determine other information about the
`conversion operation of the QADC module 1. The
`content of these registers is shown in somewhat greater
`detail in FIG. 6.
`The next block 81 of the address map