MT-090
`TUTORIAL
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`Sample-and-Hold Amplifiers
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`INTRODUCTION AND HISTORICAL PERSPECTIVE
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`The sample-and-hold amplifier, or SHA, is a critical part of most data acquisition systems. It
`captures an analog signal and holds it during some operation (most commonly analog-digital
`conversion). The circuitry involved is demanding, and unexpected properties of commonplace
`components such as capacitors and printed circuit boards may degrade SHA performance.
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`When the SHA is used with an ADC (either externally or internally), the SHA performance is
`critical to the overall dynamic performance of the combination, and plays a major role in
`determining the SFDR, SNR, etc., of the system.
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`Although today the SHA function has become an integral part of the sampling ADC,
`understanding the fundamental concepts governing its operation is essential to understanding
`ADC dynamic performance.
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`When the sample-and-hold is in the sample (or track) mode, the output follows the input with
`only a small voltage offset. There do exist SHAs where the output during the sample mode does
`not follow the input accurately, and the output is only accurate during the hold period (such as
`the AD684, AD781, and AD783). These will not be considered here. Strictly speaking, a sample-
`and-hold with good tracking performance should be referred to as a track-and-hold circuit, but in
`practice the terms are used interchangeably.
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`The most common application of a SHA is to maintain the input to an ADC at a constant value
`during conversion. With many, but not all, types of ADC the input may not change by more than
`1 LSB during conversion lest the process be corrupted—this either sets very low input frequency
`limits on such ADCs, or requires that they be used with a SHA to hold the input during each
`conversion.
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`From a historial perspective, it is interesting that the ADC described by A. H. Reeves in his
`famous PCM patent of 1939 (Reference 1) was a 5-bit 6-kSPS counting ADC where the analog
`input signal drove a vacuum tube pulse-width-modulator (PWM) directly—the sampling
`function was incorporated into the PWM. Subsequent work on PCM at Bell Labs led to the use
`of electron-beam encoder tubes and successive approximation ADCs; and Reference 2 (1948)
`describes a companion 50-kSPS vacuum tube sample-and-hold circuit based on a pulse
`transformer drive circuit.
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`There was increased interest in sample-and-hold circuits for ADCs during the period of the late
`1950s and early 1960s as transistors replaced vacuum tubes. One of the first analytical treatments
`of the errors produced by a solid-state sample-and-hold was published in 1964 by Gray and
`Kitsopolos of Bell Labs (Reference 3). Edson and Henning of Bell Labs describe the results of
`experimental work done on a 224-Mbps PCM system, including the 9-bit ADC and a companion
`12-MSPS sample-and-hold. References 4, 5 , and 6 are representative of work done on sample-
`and-hold circuits during the 1960s and early 1970s.
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`Rev.0, 10/08, WK
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`Apple 1023
`U.S. Pat. 9,189,437
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`In 1969, the newly acquired Pastoriza division of Analog Devices offered one of the first
`commercial sample-and-holds, the SHA1 and SHA2. The circuits were offered on PC boards,
`and the SHA1 had an acquisition time of 2 µs to 0.01%, dissipated 0.9 W, and cost
`approximately $225. The faster SHA2 had an acquisition time of 200 ns to 0.01%, dissipated 1.7
`W, and cost approximately $400. They were designed to operate with 12-bit successive
`approximation ADCs also offered on PC boards.
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`Modular and hybrid technology quickly made the PC board sample-and-holds obsolete, and the
`demand for sample-and-holds increased as IC ADCs, such as the industry-standard AD574, came
`on the market. In the 1970s and into the 1980s, it was quite common for system designers to
`purchase separate sample-and-holds to drive such ADCs, because process technology did not
`allow integrating them together onto the same chip. IC SHAs such as the AD582 (4-µs
`acquisition time to 0.01%), AD583 (6-µs acquisition time to 0.01%), and the AD585 (3-µs
`acquisition time to 14-bit accuracy) served the lower speed markets of the 1970s and 1980s.
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`Hybrid SHAs such as the HTS-0025 (25-ns acquisition time to 0.1%), HTC-0300 (200-ns
`acquisition time to 0.01%), and the AD386 (25-µs acquisition time to 16-bits) served the high-
`speed, high-end markets. By 1995, Analog Devices offered approximately 20 sample-and-hold
`products for various applications, including the following high-speed ICs: AD9100/AD9101 (10-
`ns acquisition time to 0.01%), AD684 (quad 1-µs acquisition time to 0.01%) and the AD783
`(250-ns acquisition time to 0.01%).
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`However, ADC technology was rapidly expanding during the same period, and many ADCs
`were being offered with internal SHAs (i.e., sampling ADCs). This made them easier to specify
`and certainly easier to use. Integration of the SHA function was made possible by new process
`developments including high-speed complementary bipolar processes and advanced CMOS
`processes. In fact, the proliferation and popularity of sampling ADCs has been so great that
`today (2003), one rarely has the need for a separate SHA.
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`The advantage of a sampling ADC, apart from the obvious ones of smaller size, lower cost, and
`fewer external components, is that the overall dc and ac performance is fully specified, and the
`designer need not spend time ensuring that there are no specification, interface, or timing issues
`involved in combining a discrete ADC and a discrete SHA. This is especially important when
`one considers dynamic specifications such as SFDR and SNR.
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`Although the largest applications of SHAs are with ADCs, they are also occasionally used in
`DAC deglitchers, peak detectors, analog delay circuits, simultaneous sampling systems, and data
`distribution systems.
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`BASIC SHA OPERATION
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`Regardless of the circuit details or type of SHA in question, all such devices have four major
`components. The input amplifier, energy storage device (capacitor), output buffer, and switching
`circuits are common to all SHAs as shown in the typical configuration of Figure 1.
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`Figure 1: Basic Sample-and-Hold Circuit
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`The energy-storage device, the heart of the SHA, is a capacitor. The input amplifier buffers the
`input by presenting a high impedance to the signal source and providing current gain to charge
`the hold capacitor. In the track mode, the voltage on the hold capacitor follows (or tracks) the
`input signal (with some delay and bandwidth limiting). In the hold mode, the switch is opened,
`and the capacitor retains the voltage present before it was disconnected from the input buffer.
`The output buffer offers a high impedance to the hold capacitor to keep the held voltage from
`discharging prematurely. The switching circuit and its driver form the mechanism by which the
`SHA is alternately switched between track and hold.
`
`There are four groups of specifications that describe basic SHA operation: track mode, track-to-
`hold transition, hold mode, hold-to-track transition. These specifications are summarized in
`Figure 2, and some of the SHA error sources are shown graphically in Figure 3. Because there
`are both dc and ac performance implications for each of the four modes, properly specifying a
`SHA and understanding its operation in a system is a complex matter.
`
`HOLD-TO-SAMPLE
`TRANSITION
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`DYNAMIC:
`Acquisition Time
`Switching
`Transient
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`(cid:139)(cid:139)
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`HOLD MODE
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`STATIC:
`Droop
`Dielectric
`Absorption
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`(cid:139)(cid:139)(cid:139)
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`DYNAMIC:
`Feedthrough
`Distortion
`Noise
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`(cid:139)(cid:139)(cid:139)
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`SAMPLE-TO-HOLD
`TRANSITION
`STATIC:
`Pedestal
`Pedestal
`Nonlinearity
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`(cid:139)(cid:139)
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`DYNAMIC:
`Aperture Delay Time
`Aperture Jitter
`Switching Transient
`Settling Time
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`(cid:139)(cid:139)(cid:139)(cid:139)
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`SAMPLE MODE
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`STATIC:
`Offset
`Gain Error
`Nonlinearity
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`(cid:139)(cid:139)(cid:139)
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`DYNAMIC:
`Settling Time
`Bandwidth
`Slew Rate
`Distortion
`Noise
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`(cid:139)(cid:139)(cid:139)(cid:139)(cid:139)
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`Figure 2: Sample-and-Hold Specifications
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`MT-090
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`APERTUREAPERTURE
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`JITTERJITTER
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`ERRORERROR
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`Figure 3: Some Sources of Sample-and-Hold Errors
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`TRACK MODE SPECIFICATIONS
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`Since a SHA in the sample (or track) mode is simply an amplifier, both the static and dynamic
`specifications in this mode are similar to those of any amplifier. (SHAs which have degraded
`performance in the track mode are generally only specified in the hold mode.) The principle
`track mode specifications are offset, gain, nonlinearity, bandwidth, slew rate, settling time,
`distortion, and noise. However, distortion and noise in the track mode are often of less interest
`than in the hold mode.
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`TRACK-TO-HOLD MODE SPECIFICATIONS
`
`When the SHA switches from track to hold, there is generally a small amount of charge dumped
`on the hold capacitor because of non-ideal switches. This results in a hold mode dc offset voltage
`which is called pedestal error as shown in Figure 4. If the SHA is driving an ADC, the pedestal
`error appears as a dc offset voltage which may be removed by performing a system calibration. If
`the pedestal error is a function of input signal level, the resulting nonlinearity contributes to hold-
`mode distortion.
`
`Pedestal errors may be reduced by increasing the value of the hold capacitor with a
`corresponding increase in acquisition time and a reduction in bandwidth and slew rate.
`
`Switching from track to hold produces a transient, and the time required for the SHA output to
`settle to within a specified error band is called hold mode settling time. Occasionally, the peak
`amplitude of the switching transient is also specified.
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`Figure 4: Track-to-Hold Mode Pedestal, Transient,
`and Settling Time Errors
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`Perhaps the most misunderstood and misused SHA specifications are those that include the word
`aperture. The most essential dynamic property of a SHA is its ability to disconnect quickly the
`hold capacitor from the input buffer amplifier. The short (but non-zero) interval required for this
`action is called aperture time. The various quantities associated with the internal SHA timing are
`shown in the Figure 5.
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`Figure 5: SHA Circuit Showing Internal Timing
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`The actual value of the voltage that is held at the end of this interval is a function of both the
`input signal and the errors introduced by the switching operation itself. Figure 6 shows what
`happens when the hold command is applied with an input signal of arbitrary slope (for clarity,
`the sample to hold pedestal and switching transients are ignored). The value that finally gets held
`is a delayed version of the input signal, averaged over the aperture time of the switch as shown in
`Figure 6. The first-order model assumes that the final value of the voltage on the hold capacitor
`is approximately equal to the average value of the signal applied to the switch over the interval
`during which the switch changes from a low to high impedance (ta).
`
`
`The model shows that the finite time required for the switch to open (ta) is equivalent to
`introducing a small delay in the sampling clock driving the SHA. This delay is constant and may
`either be positive or negative. It is called effective aperture delay time, aperture delay time, or
`simply aperture delay, (te) and is defined as the time difference between the analog propagation
`delay of the front-end buffer (tda) and the switch digital delay (tdd) plus one-half the aperture time
`(ta/2). The effective aperture delay time is usually positive, but may be negative if the sum of
`one-half the aperture time (ta/2) and the switch digital delay (tdd) is less than the propagation
`delay through the input buffer (tda). The aperture delay specification thus establishes when the
`input signal is actually sampled with respect to the sampling clock edge.
`
`Aperture delay time can be measured by applying a bipolar sinewave signal to the SHA and
`adjusting the synchronous sampling clock delay such that the output of the SHA is zero during
`the hold time. The relative delay between the input sampling clock edge and the actual zero-
`crossing of the input sinewave is the aperture delay time as shown in Figure 7.
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`Figure 6: SHA Waveforms
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`Figure 7: Effective Aperture Delay Time
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`Aperture delay produces no errors, but acts as a fixed delay in either the sampling clock input or
`the analog input (depending on its sign). If there is sample-to-sample variation in aperture delay
`(aperture jitter), then a corresponding voltage error is produced as shown in Figure 8. This
`sample-to-sample variation in the instant the switch opens is called aperture uncertainty, or
`aperture jitter and is usually measured in picoseconds rms. The amplitude of the associated
`output error is related to the rate-of-change of the analog input. For any given value of aperture
`jitter, the aperture jitter error increases as the input dv/dt increases.
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`Figure 8: Effects of Aperture or Sampling Clock
`Jitter on SHA Output
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`Measuring aperture jitter error in a SHA requires a jitter-free sampling clock and analog input
`signal source, because jitter (or phase noise) on either signal cannot be distinguished from the
`SHA aperture jitter itself—the effects are the same. In fact, the largest source of timing jitter
`errors in a system is most often external to the SHA (or the ADC if it is a sampling one) and is
`caused by noisy or unstable clocks, improper signal routing, and lack of attention to good
`grounding and decoupling techniques. SHA aperture jitter is generally less than 50-ps rms, and
`less than 5-ps rms in high speed devices. Details of measuring aperture jitter of an ADC can be
`found in Chapter 5 of Reference 11.
`
`Figure 9 shows the effects of total sampling clock jitter on the signal-to-noise ratio (SNR) of a
`sampled data system. The total rms jitter will be composed of a number of components, the
`actual SHA aperture jitter often being the least of them.
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`ENOB
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`18
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`16
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`14
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`12
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`10
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`8 6 4
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`SNR = 20log 10
`SNR = 20log 10
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`1
`1
`2πftj
`2πftj
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`tj = 50fs
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`tj = 0.1ps
`tj = 1ps
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`tj = 10ps
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`tj = 100ps
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`tj = 1ns
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`120
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`100
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`80
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`60
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`40
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`20
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`SNR
`(dB)
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`1
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`100
`3
`30
`10
`FULL-SCALE SINEWAVE ANALOG INPUT FREQUENCY (MHz)
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`Figure 9: Effects of Sampling Clock Jitter on SNR
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`HOLD MODE SPECIFICATIONS
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`During the hold mode there are errors due to imperfections in the hold capacitor, switch, and
`output amplifier. If a leakage current flows in or out of the hold capacitor, it will slowly charge
`or discharge, and its voltage will change as shown in Figure 10. This effect is known as droop in
`the SHA output and is expressed in V/µs. Droop can be caused by leakage across a dirty PC
`board if an external capacitor is used, or by a leaky capacitor, but is most usually due to leakage
`current in semiconductor switches and the bias current of the output buffer amplifier. An
`acceptable value of droop is where the output of a SHA does not change by more than ½ LSB
`during the conversion time of the ADC it is driving, although this value is highly dependent on
`the ADC architecture. Where droop is due to leakage current in reversed biased junctions
`(CMOS switches or FET amplifier gates), it will double for every 10°C increase in chip
`temperature—which means that it will increase a thousand fold between +25°C and +125°C.
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`Droop can be reduced by increasing the value of the hold capacitor, but this will also increase
`acquisition time and reduce bandwidth in the track mode. Differential techniques are often used
`to reduce the effects of droop in modern IC sample-and-hold circuits that are part of the ADC.
`
`Figure 10: Hold Mode Droop
`
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`Even quite small leakage currents can cause troublesome droop when SHAs use small hold
`capacitors. Leakage currents in PCBs may be minimized by the intelligent use of guard rings. A
`guard ring is a ring of conductor which surrounds a sensitive node and is at the same potential.
`Since there is no voltage between them, there can be no leakage current flow. In a non-inverting
`application, such as is shown in Figure 11, the guard ring must be driven to the correct potential,
`whereas the guard ring on a virtual ground can be at actual ground potential (Figure 12). The
`surface resistance of PCB material is much lower than its bulk resistance, so guard rings must
`always be placed on both sides of a PCB—and on multi-layer boards, guard rings should be
`present in all layers.
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`Figure 11: Drive the Guard Shield with the Same Voltage as the Hold Capacitor to
`Reduce Board Leakage
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`Figure 12: Using a Guard Shield on a Virtual
`Ground SHA Design
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`Hold capacitors for SHAs must have low leakage, but there is another characteristic which is
`equally important: low dielectric absorption. If a capacitor is charged, then discharged, and then
`left open circuit, it will recover some of its charge as shown in Figure 13. The phenomenon is
`known as dielectric absorption, and it can seriously degrade the performance of a SHA, since it
`causes the remains of a previous sample to contaminate a new one, and may introduce random
`errors of tens or even hundreds of mV.
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`Figure 13: Dielectric Absorption
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`Different capacitor materials have differing amounts of dielectric absorption—electrolytic
`capacitors are dreadful (their leakage is also high), and some high-K ceramic types are bad,
`while mica, polystyrene and polypropylene are generally good. Unfortunately, dielectric
`absorption varies from batch to batch, and even occasional batches of polystyrene and
`polypropylene capacitors may be affected. It is therefore wise to pay 30-50% extra when buying
`capacitors for SHA applications and buy devices which are guaranteed by their manufacturers to
`have low dielectric absorption, rather than types which might generally be expected to have it.
`
`Stray capacity in a SHA may allow a small amount of the ac input to be coupled to the output
`during hold. This effect is known as feedthrough and is dependent on input frequency and
`amplitude. If the amplitude of the feedthrough to the output of the SHA is more than ½ LSB,
`then the ADC is subject to conversion errors.
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`In many SHAs, distortion is specified only in the track mode. The track mode distortion is often
`much better than hold mode distortion. Track mode distortion does not include nonlinearities due
`to the switch network, and may not be indicative of the SHA performance when driving an ADC.
`Modern SHAs, especially high speed ones, specify distortion in both modes. While track mode
`distortion can be measured using an analog spectrum analyzer, hold mode distortion
`measurements should be performed using digital techniques as shown in Figure 14. A spectrally
`pure sinewave is applied to the SHA, and a low distortion high speed ADC digitizes the SHA
`output near the end of the hold time. An FFT analysis is performed on the ADC output, and the
`distortion components computed.
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`SHA noise in the track mode is specified and measured like that of an amplifier. Peak-to-peak
`hold mode noise is measured with an oscilloscope and converted to an rms value by dividing by
`6.6. Hold mode noise may be given as a spectral density in nV/√Hz, or as an rms value over a
`specified bandwidth. Unless otherwise indicated, the hold mode noise must be combined with
`the track mode noise to yield the total output noise. Some SHAs specify the total output hold
`mode noise, in which case the track mode noise is included.
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`Figure 14: Measuring Hold Mode Distortion
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`HOLD-TO-TRACK TRANSITION SPECIFICATIONS
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`When the SHA switches from hold to track, it must reacquire the input signal (which may have
`made a full scale transition during the hold mode). Acquisition time is the interval of time
`required for the SHA to reacquire the signal to the desired accuracy when switching from hold to
`track. The interval starts at the 50% point of the sampling clock edge, and ends when the SHA
`output voltage falls within the specified error band (usually 0.1% and 0.01% times are given).
`Some SHAs also specify acquisition time with respect to the voltage on the hold capacitor,
`neglecting the delay and settling time of the output buffer. The hold capacitor acquisition time
`specification is applicable in high speed applications, where the maximum possible time must be
`allocated for the hold mode. The output buffer settling time must of course be significantly
`smaller than the hold time.
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`Acquisition time can be measured directly using modern digital sampling scopes (DSOs) or
`digital phosphor scopes (DPOs) which are insensitive to large overdrives.
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`SHA ARCHITECTURES
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`As with op amps, there are numerous SHA architectures, and we will examine a few of the most
`popular ones. The simplest SHA structure is shown in Figure 15. The input signal is buffered by
`an amplifier and applied to the switch. The input buffer may either be open- or closed-loop and
`may or may not provide gain. The switch can be CMOS, FET, or bipolar (using diodes or
`transistors) and is controlled by the switch driver circuit. The signal on the hold capacitor is
`buffered by an output amplifier. This architecture is sometimes referred to as open-loop because
`the switch is not inside a feedback loop. Notice that the entire signal voltage is applied to the
`switch, therefore it must have excellent common-mode characteristics.
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`
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`Figure 15: Open-Loop SHA Architecture
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`An implementation of this architecture is shown in Figure 16, where a simple diode bridge is
`used for the switch. In the track mode, current flows through the bridge diodes D1, D2, D3, and
`D4. For fast slewing input signals, the hold capacitor is charged and discharged with the current,
`I. Therefore, the maximum slew rate on the hold capacitor is equal to I/CH. Reversing the bridge
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`drive currents reverse biases the bridge and places the circuit in the hold mode. Bootstrapping the
`turn-off pulses with the held output signal minimizes common-mode distortion errors and is key
`to the circuit. The reverse bias bridge voltage is equal to the forward drops of D5 and D6 plus
`the voltage drops across the series resistors R1 and R2. This circuit is extremely fast, especially
`if the input and output buffers are open-loop followers, and the diodes are Schottky ones. The
`turn-off pulses can be generated with high frequency pulse transformers or with current switches
`as shown in Figure 17. This circuit can be used at any sampling rate, because the diode switching
`pulses are direct-coupled to the bridge. Variations of this circuit have been used since the mid
`1960s in high speed PC board, modular, hybrid, and IC SHAs.
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`II
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`II
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`D1D1
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`D2D2
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`II
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`R1R1
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`D5D5
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`D6D6
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`R2R2
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`II
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`D3D3
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`D4D4
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`CHCH
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`BOOTSTRAPBOOTSTRAP
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`Figure 16: Open-Loop SHA Using Diode Bridge Switch
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`I
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`+15V
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`Q1
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`Q2
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`6.2V
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`6.2V
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`D1
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`D3
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`A = 1
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`6.2V
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`6.2V
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`D2
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`D4
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`CH
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`A = 1
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`R1
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`D5
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`D6
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`R2
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`T
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`(ECL)
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`H
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`Q3
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`Q4
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`H
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`T
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`(ECL)
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`I
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`–15V
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`Figure 17: Open-Loop SHA Implementation
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`The SHA circuit shown in Figure 18 represents a classical closed-loop design and is used in
`many CMOS sampling ADCs. Since the switches always operate at virtual ground, there is no
`c
`-mode signal across them.
`ommon
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`Figure 18: Closed-Loop SHA Based on Inverting
`Integrator Switched at the Summing Point
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`Switch S2 is required in order to maintain a constant input impedance and prevent the input
`signal from coupling to the output during the hold time. In the track mode, the transfer
`characteristic of the SHA is determined by the op amp, and the switches do not introduce dc
`injection
`errors because they are inside the feedback loop. The effects of charge
` can be
`ized by using the differential switching techniques shown in Figure 19.
`inim
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`m
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`g Reduces Charge Injection
`Figure 19: Differential Switchin
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`INTERNAL SHA CIRCUITS FOR IC ADCS
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`CMOS ADCs are quite popular because of their low power and low cost. The equivalent input
`circuit of a typical CMOS ADC using a differential sample-and-hold is shown in Figure 20.
`While the switches are shown in the track mode, note that they open/close at the sampling
`frequency. The 16-pF capacitors represent the effective capacitance of switches S1 and S2, plus
`the stray input capacitance. The CS capacitors (4 pF) are the sampling capacitors, and the CH
`capacitors are the hold capacitors. Although the input circuit is completely differential, this ADC
`nce, however, is
`structure can be driven either single-ended or differentially. Optimum performa
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`generally obtained using a differential transformer or differential op amp drive.
`CH
`S6
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`4pF
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`S4
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`S5
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`S7
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`A
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`+ -
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`CH
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`4pF
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`S1
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`S2
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`S3
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`16pF
`CP
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`CP
`16pF
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`CS
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`4pF
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`CS
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`4pF
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`SWITCHES SHOWN IN TRACK MODE
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`VINA
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`VINB
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`
` Switched
`Figure 20:
`Simplified Input Circuit for a Typical
`Capacitor CMOS Sample-and-Hold
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`In the track mode, the differential input voltage is applied to the CS capacitors. When the circuit
`enters the hold mode, the voltage across the sampling capacitors is transferred to the CH hold
`capacitors and buffered by the amplifier A (the switches are controlled by the appropriate
`sampling clock phases). When the SHA returns to the track mode, the input source must charge
`or discharge the voltage stored on CS to a new input voltage. This action of charging and
`discharging CS, averaged over a period of time and for a given sampling frequency fs, makes the
`input impedance appear to have a benign resistive component. However, if this action is
`analyzed within a sampling period (1/fs),
` the input impedance is dynamic, and certain input drive
`so
`urce precautions should be observed.
`
`The resistive component to the input impedance can be computed by calculating the average
`charge that is drawn by CH from the input drive source. It can be shown that if CS is allowed to
`fully charge to the input voltage before switches S1 and S2 are opened that the average current
`into the input is the same as if there were a resistor equal to 1/(CSfS) connected between the
`inputs. Since CS is only a few
`picofarads, this resistive component is typically greater than
`veral kΩ for an fS = 10 MSPS.
`se
`
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`Figure 21 shows a simplified circuit of the input SHA used in the AD9042 12-bit,41-MSPS ADC
`introduced in 1995 (Reference 7). The AD9042 is fabricated on a high speed complementary
`bipolar process, XFCB. The circuit comprises two independent SHAs in parallel for fully
`differential operation—only one-half the circuit is shown in the figure. Fully differential
`operation reduces the error due to droop rate and also reduces second-order distortion. In the
`track mode, transistors Q1 and Q2 provide unity-gain buffering. When the circuit is placed in the
`hold mode, the base voltage of Q2 is pulled negative until it is clamped by the diode, D1. The
`on-chip hold capacitor, CH, is nominally 6 pF. Q3 along with CF provide output current
`bootstrapping and reduce the VBE variations of Q2. This reduces third-order signal distortion.
`Track mode THD is typically –93 dB at 20 MHz. In the time domain, full-scale acquisition time
`to 12-bit accuracy is 8 ns. In the hold mode, signal-dependent pedestal variations are minimized
`by the voltage bootstrapping action of Q3 and the A = 1 buffer along with the low feedthrough
`parasitics of Q2. Hold mode settling time is 5 ns to 12-bit accuracy. Hold-mode THD at a clock
`
`te of 50 MSPS and a 20-MHz input signal is –90 dB. ra
`
`
`I
`
`Q1
`
`Q3
`
`I
`
`A=1
`
`H
`
`T
`
`Q2
`
`CIRCUIT SHOWN
`IN TRACK MODE
`
`D1
`
`I
`
`CH
`
`FULLY DIFFERENTIAL,
`ONLY ONE-HALF SHOWN
`
`Q5
`
`T
`
`H
`
`Q4
`
`CF
`
`2I
`
`Figure 21: SHA Used in AD9042 12-Bit, 41 MSPS ADC Introduced in 1995
`
`
`
`
`
`Figure 22 shows a simplified schematic of one-half of the differential SHA used in the AD6645
`14-bit, 105-MSPS ADC recently introduced (Reference 9) gives a complete description of the
`ADC including the SHA). In the track mode, Q1, Q2, Q3, and Q4 form a complementary emitter
`follower buffer which drives the hold capacitor, CH. In the hold mode, the polarity of the bases of
`Q3 and Q4 is reversed and clamped to a low impedance. This turns off Q1, Q2, Q3, and Q4, and
`results in double isolation between the signal at the input and the hold capacitor. As previously
`discussed, the clamping voltages are bootstrapped by the held output voltage, thereby
`inimizing nonlinear effects.
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`Page 16 of 21
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`Track mode linearity is largely determined by the VBE modulation of Q3 and Q4 when charging
`CH. Hold mode linearity depends on track mode linearity plus nonlinear errors in the track-to-
`hold transitions caused by imbalances in the switching of the base voltages of Q3 and Q4 and the
`sulting imbalance in charge injection through their base-emitter junctions as they turn off.
`re
`
`
`T+
`
`H+
`
`Q5
`
`Q6
`
`Q2
`
`Q1
`
`H+
`
`T+
`
`CLAMP
`
`FULLY DIFFERENTIAL,
`ONLY ONE-HALF SHOWN
`
`Q3
`
`RCH
`
`CH
`
`Q4
`
`T–
`
`H–
`
`Q7
`
`Q8
`
`H–
`
`T–
`
`Figure 22: SHA Used in AD6645 14-Bit, 105 MSPS ADC Introduced in 2000
`
`
`
`HA APPLICATIONS
`
` S B
`
`y far the largest application of SHAs is driving ADCs. Most modern ADCs designed for signal
`processing are sampling ones and contain an internal SHA optimized for the converter design.
`Sampling ADCs are completely specified for both dc and ac performance and should be used in
`lieu of discrete SHA/ADC combinations wherever possible. In a very few selected cases,
`e dynamic range and low distortion, there may be advantages to
`especially those requiring wid
`sing a discrete combination.
`
`u A
`
` similar application uses a low distortion SHA to minimize the effects of code-dependent DAC
`glitches as shown in Figure 23. Just prior to latching new data into the DAC, the SHA is put into
`the hold mode so that the DAC switching glitches are isolated from the output. The switching
`transients produced by the SHA are not code-dependent, occur at the update frequency, and are
`easily filterable. This technique may be useful at low frequencies to improve the distortion
`
`performance of DACs, but has little value when using high speed low-glitch low distortion
`ACs designed especially for DDS applications where the update rate is several hundred MHz.
`
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`Figure 23: Using a SHA as a DAC Deglitcher
`
`
`
`
`
`c
`
`
`
`
`Rather than use a single ADC per channel in a simultaneous sampled system, it is often more
`economical to use multiple SHAs followed by an analog multiplexer and a single ADC (Figure
`24). Similarly, in data distribution systems multiple SHAs can be used to route the sequential
`Figure 25; although this is not as
`outputs of a single DAC to multiple channels as shown in
`ommon, as multiple DACs usually offer a better solution.
`
`
`Figure 24: Si
`multaneous Sampling Us
`SHAs and a Single ADC
`
`ing Multiple
`
`
`
`Page 18 of 21
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`MT-090
`
`Figure 25: Data Distribution System Using Multiple
`SHAs and a Single DAC
`
`
`
`
`
` A
`
`
`
` final application for SHAs is shown in Figure 26, where SHAs are cascaded to produce analog
`delay in a sampled data system. SHA 2 is placed in hold just prior to the end of the hold interval
`for SHA 1. This results in a total pipeline delay greater than the sampling period T. This
`technique is often used in multi-stage pipelined subranging ADCs to allow for the conversion
`delays of successive stages. In pipelined ADCs, a 50% duty cycle sampling clock is common,
`thereby allowing alternating clock phases to drive each SHA in the pipeline (see tutorial MT-024
`for details on pipelined ADCs).
`
`Figure 26: SHAs Used for Analog Pipelined Delay
`
`
`
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`REFERENCES:
`
`
`1. Alec Harley Reeves, "Electric Signaling System," U.S. Patent 2,272,070, filed November 22, 1939, issued
`February 3, 1942. Also French Patent 852,183 issued 1938, and British Patent 538,860 issued 1939. (the
`classic patents on PCM including descriptions of a 5-bit, 6-kSPS vacuum tube ADC and DAC).
`
`2. L. A. Meacham and E. Peterson, "An Experimental Multichannel Pulse Code Modulation System of Toll
`Quality," Bell Sy