United States Patent [19J
`Johnson et al.
`
`I lllll llllllll Ill lllll lllll lllll lllll lllll 111111111111111111111111111111111
`US005909463A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,909,463
`Jun.1,1999
`
`[54] SINGLE-CHIP SOFTWARE CONFIGURABLE
`TRANSCEIVER FOR ASYMMETRIC
`COMMUNICATION SYSTEM
`
`[75]
`
`Inventors: Terence L. Johnson; Peter R. Molnar;
`Howard E. Levin; Jeffrey P. Gleason;
`Robin Wiprud; Sujit Sudhaman, all of
`Austin; Jody Everett, Buda; Michael
`R. May, Austin; Carlos A. Greaves,
`Austin; Mathew A. Rybicki, Austin;
`Matthew A. Pendleton, Cedar Park;
`John M. Porter, Round Rock, all of
`Tex.
`
`[73] Assignee: Motorola, Inc., Schaumburg, Ill.
`
`[21] Appl. No.: 08/741,634
`
`[22]
`
`Filed:
`
`Nov. 4, 1996
`
`[51]
`
`[52]
`
`[58]
`
`Int. Cl.6
`
`............................... H04B 1/38; H04B 1/56;
`H04L 5/14; H04L 5/16
`U.S. Cl. .......................... 375/220; 375/220; 375/219;
`375/221; 375/222; 370/276; 370/295; 370/464;
`370/480; 455/73
`Field of Search ..................................... 375/220, 219,
`375/221, 222, 223; 370/276, 295, 296,
`464, 480, 389, 395, 403, 404, 402, 400,
`401; 455/73
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,438,511
`4,597,073
`4,679,227
`4,731,816
`4,890,316
`
`3/1984 Baran ........................................ 370/94
`6/1986 Staples ...................................... 370/24
`7/1987 Hughes-Hartogs ....................... 379/98
`3/1988 Hughes-Hartogs ....................... 379/98
`12/1989 Walsh et al. .............................. 379/98
`
`4,980,897 12/1990 Decker et al. ............................ 375/38
`5,586,121 12/1996 Moura et al. ........................... 370/404
`
`OTHER PUBLICATIONS
`
`Adiraensen et al., Single chip DMT-modem transceiver for
`ADSL, Proceedings of the 9th IEEE International ASIC
`Conference and Exhibit, pp. 123-126, Sep. 23, 1996.
`Alliance
`for Telecommunications
`Industry Solutions,
`"Asymmetric Digital Subscriber Line (ADSL) Metallic
`Interface", Draft American National Standard for Telecom(cid:173)
`munications, Network and Customer Installation Interfaces,
`T1El.4/94-007R7, pp. i-xii and pp. 2-171.
`
`Primary Examiner-Stephen Chin
`Assistant Examiner-Michael W. Maddox
`Attorney, Agent, or Firm-Paul J. Polansky
`
`[57]
`
`ABSTRACT
`
`A transceiver (5) for an asymmetric communication system
`such as asymmetric digital subscriber line (ADSL) includes
`a configuration register (71) defining operation at either a
`central office (CO) or a remote terminal (RT). The configu(cid:173)
`ration register (71) includes a control bit (72) for selecting
`either CO or RT mode. The transceiver (5) includes a signal
`processing module (70) configured according to the state of
`the control bit (72). For example, a digital interface (70)
`converts transmit data into transmit symbols and converts
`received symbols into receive data. The digital interface (70)
`uses a large memory (158) as a buffer in the transmit path
`and a small memory (160) as a buffer in the receive path in
`CO mode. In RT mode, the digital interface (70) uses the
`small memory (160) in the transmit path and the large
`memory (158) in the receive path. The selective configura(cid:173)
`tion allows a single integrated circuit to be used in both CO
`and RT equipment.
`
`40 Claims, 9 Drawing Sheets
`
`RESET
`
`DSP
`CORE
`
`60
`
`62
`
`PDB
`YDB
`XDB
`
`PIO EB
`
`MEMORY
`64
`
`ANALOG
`FRONT-END
`78
`
`TXA
`PORT
`
`RXA
`PORT
`
`--,
`I
`I
`I
`I
`I
`I
`I
`DSP PERIPHERALS
`69
`I
`1..--------------~
`
`FFT
`73
`
`CES
`74
`
`CRYSTAL
`
`vcxo
`66
`
`HPI
`68
`
`DIGITAL
`INTERFACE 70
`
`CONTROL
`PORT
`
`INTERLEAVER DIGITAL
`MEMORY
`PORTS
`PORT
`
`TEQ
`76
`
`CSCO-1016
`Cisco Systems v. TQ Delta, IPR2016-01760
`Page 1 of 24
`
`

`

`\C = \C
`
`~
`0--,
`~
`....
`
`....
`Ul
`
`\C
`
`'"""' 0 .....,
`~ .....
`'Jl =(cid:173)~
`
`\C
`\C
`'"""'
`\C
`'"""' ~
`~ = ?
`
`~ = ......
`~ ......
`~
`•
`\JJ.
`d •
`
`STREAM
`INPUT
`DIGITAL
`
`I
`I
`
`. 36\
`
`)
`
`I
`
`0
`
`32)
`
`TERMINAL 30 ~ 34
`
`REMOTE
`
`,.----j SOFTWARE L_J SOFTWARE H LOW RATE I (
`
`INTERFACE
`DIGIT AL 1--L-
`
`FILTERS rn IFFT
`
`~ * , 40
`
`CANCELLER
`
`ECHO
`
`15 INTERFACE
`AND LINE
`
`td ANALOG
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`STREAM
`OUTPUT
`DIGITAL
`
`INTERFACE
`DIGIT AL
`HIGH RATE
`
`50 ') t
`
`MEMORY
`LARGE
`
`44,
`
`MEMORY
`SMALL
`
`42,
`
`FIG.1
`
`HARDWARE
`
`FFT
`
`FILTERS
`L-..J HARDWARE
`
`FILTERS
`SOFTWARE.._
`
`SOFTWARE
`
`FFT
`
`48,
`
`46,
`
`22
`
`20
`
`INTERFACE
`AND LINE
`ANALOG
`
`12\
`
`CANCELLER
`
`ECHO
`
`116
`
`•
`
`STREAM
`OUTPUT
`DIGITAL
`
`INTERFACE
`DIGIT AL
`LOW RATE
`
`~----1.........1.----,,
`
`18
`
`MEMORY
`SMALL
`
`114
`
`MEMORY
`LARGE
`
`18
`
`1--
`
`FILTERS
`
`IFFT
`
`INTERFACE
`
`6
`~ OFFICE 10
`CENTRAL
`
`4
`
`STREAM
`INPUT
`DIGITAL ~
`
`2
`
`1
`
`~Ht~~I~:~tl
`) ~H· HARDW:E m" HARDWARE
`
`CSCO-1016
`Cisco Systems v. TQ Delta, IPR2016-01760
`Page 2 of 24
`
`

`

`\C = \C
`
`~
`0--,
`~
`....
`
`....
`Ul
`
`\C
`0 .....,
`N
`~ .....
`'Jl =(cid:173)~
`
`\C
`\C
`'"""'
`\C
`'"""' ~
`~ = ?
`
`~ = ......
`~ ......
`~
`•
`\JJ.
`d •
`
`FIG.2
`
`PORTS
`INTERLEAVER DIGITAL
`
`PORT
`MEMORY
`
`'
`
`CONTROL
`
`PORT
`
`'-.--------------~
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`,---~-----------,
`
`69
`
`DSP PERIPHERALS
`
`76
`TEQ
`
`'
`
`74
`CES
`
`73
`FFT
`
`'
`
`I
`
`'
`INTERFACE 70
`DIGITAL
`~ lcoNR'TI I I
`\..
`
`,.-
`
`1r ~2
`
`REGISTER 71
`
`' CONFIGURATION '
`
`68
`HP!
`
`I
`
`66
`vcxo
`
`-
`
`CRYSTAL
`
`PORT
`RXA
`
`PORT
`TXA
`
`78
`FRONT-END
`
`ANALOG
`
`64
`MEMORY
`
`-
`
`PIO EB
`
`1
`
`62\
`
`XDB
`YDB
`PDB
`
`60 r---
`
`CORE
`DSP
`
`-
`
`-
`
`RESET
`
`s,
`
`CSCO-1016
`Cisco Systems v. TQ Delta, IPR2016-01760
`Page 3 of 24
`
`

`

`\C = \C
`
`~
`0--,
`~
`....
`
`....
`Ul
`
`FIG.3
`
`HIGH PASS
`
`FILTER
`
`I
`
`••
`
`STRIP
`TEQ/AND
`
`CP
`
`106
`
`FFT
`
`I
`
`•
`
`FEQ ••
`
`\C
`0 .....,
`~
`
`~ .....
`'Jl =(cid:173)~
`
`\C
`\C
`'"""'
`\C
`'"""' ~
`~ = ?
`
`~ = ......
`~ ......
`~
`•
`\JJ.
`d •
`
`OMA
`
`92
`
`100
`
`102
`
`CORRECTION
`FILTER/DROOP
`HIGH PASS
`
`FILTER
`
`OMA
`
`PREFIX (CP)
`
`ADDER
`CYCLIC
`
`86
`
`SCALE FILTER
`CLIP I CLIP
`
`85
`
`SCALE
`
`IFFT
`
`FREC
`
`87
`
`83
`
`81
`
`OMA
`
`DETECTOR
`
`PHASE
`
`104
`
`DATA
`INPUT
`
`DATA
`OUTPUT
`
`BLOCK
`GAINS
`
`80
`
`OFFICE 10 ----...._
`CENTRAL
`
`CSCO-1016
`Cisco Systems v. TQ Delta, IPR2016-01760
`Page 4 of 24
`
`

`

`\C = \C
`
`~
`0--,
`~
`....
`
`....
`Ul
`
`\C
`0 .....,
`.i;;..
`
`~ .....
`'Jl =(cid:173)~
`
`\C
`\C
`'"""'
`\C
`'"""' ~
`~ = ?
`
`~ = ......
`
`~ ......
`~
`•
`\JJ.
`d •
`
`DMA
`
`PORT
`TXA
`
`DMA
`
`FIG.4
`
`CP STRIP DMA PASS FILTER
`FILTER AND
`HIGH PASS
`138
`
`TEQ/HIGH
`
`WRITE
`CES
`
`130
`
`CORRECTION
`
`FILTER
`DROOP
`
`128
`
`PASS FILTER
`CLIPPING I T T•I AND HIGH
`CP ADDER
`
`126
`
`124
`
`146
`
`FEQ
`
`FREC
`
`132
`
`DATA
`OUTPUT
`
`IFFT
`
`BLOCKS
`GAINS
`
`122
`
`120
`
`TERMINAL 30 ~
`
`REMOTE
`
`CSCO-1016
`Cisco Systems v. TQ Delta, IPR2016-01760
`Page 5 of 24
`
`

`

`U.S. Patent
`
`Jun.1,1999
`
`Sheet 5 of 9
`
`5,909,463
`
`OUTPUT
`DATA
`
`CONSTELLATION
`CIRCUIT
`
`INPUT
`DATA
`
`,-10
`
`154
`
`0
`
`CONRT
`
`0
`
`1
`
`156
`
`158
`MEMORY
`
`LARGE
`
`72
`
`160
`SMALL MEMORY
`
`150
`
`1
`
`1
`
`72
`
`CONRT
`
`166
`TRANSMIT
`CIRCUIT
`
`168
`RECEIVE
`CIRCUIT
`
`FRAME BUFFER
`CIRCUIT
`
`174
`
`0
`
`176
`LARGE
`
`MEMORY
`
`CONRT
`72
`
`182
`
`1
`
`0
`
`CON RT
`
`72
`
`0
`
`172
`
`72
`
`CONRT
`
`178
`SMALL MEMORY
`
`170
`
`0
`
`FIG.5
`
`FRAME
`FRAME
`INPUT OUTPUT
`
`CSCO-1016
`Cisco Systems v. TQ Delta, IPR2016-01760
`Page 6 of 24
`
`

`

`\C = \C
`
`~
`0--,
`~
`....
`
`....
`Ul
`
`-
`
`\C
`0 .....,
`O'I
`~ .....
`'Jl =(cid:173)~
`
`\C
`\C
`'"""'
`\C
`'"""' ~
`~ = ?
`
`~ = ......
`~ ......
`~
`•
`\JJ.
`d •
`
`220
`
`218
`
`r
`
`216
`CONTROL
`PROCESS
`
`-
`
`FIG.6
`
`-DATA BUFFER
`
`OUTPUT
`/
`22· ~
`
`MAC
`
`'
`22.i-
`
`SUBTRACT
`
`TERMS
`
`f 212
`
`,
`,
`22
`
`SUBTRACT OR
`
`,. 210
`
`I .
`22
`
`PAST DATA
`
`BUFFER
`
`f 214
`
`'
`22.i-
`
`-DATA BUFFER
`
`PRESENT
`
`208,
`
`1---
`
`-
`
`206
`CONTROL -
`DECODE
`
`r---204
`
`.--..202
`
`r-200
`
`22
`
`I
`
`REGISTER
`AND STATUS
`COMMAND
`
`,.-
`
`...---.. REGISTERS
`PARAMETER
`
`COEFFICIENT
`
`MEMORY
`
`AND
`
`,....__
`
`1---
`
`74
`(
`
`~ _7
`
`INTERRUPTS
`
`FROM CORE
`CONTROL
`A[ 11:0]
`
`12
`
`/62
`PIO EB
`
`D[23:0]
`
`~ 24 ,
`
`CSCO-1016
`Cisco Systems v. TQ Delta, IPR2016-01760
`Page 7 of 24
`
`

`

`U.S. Patent
`
`Jun.1,1999
`
`Sheet 7 of 9
`
`5,909,463
`
`~
`
`MCAB(5:0)
`MDAB(5:0)
`CONTROL FROM CORE
`
`v-300
`
`REGISTER
`DECODE
`
`,-13
`
`'
`302,
`COMMAND
`AND STATUS
`REGISTER
`
`,
`
`,
`
`FFT
`CONTROL
`304
`-
`
`306,
`
`~
`IN
`REGISTER
`
`R,
`,
`
`PIO EB 62
`-
`LJ
`
`24,
`
`I
`
`I 24
`
`MDDB
`\.
`GDB_
`
`~
`
`' ' R,
`
`OUT
`REGISTER
`310 _,/
`
`,
`
`,
`
`24
`,
`. ,
`24
`
`....
`
`~
`
`IRQ1
`DRQ1
`IRQ2
`DRQ2
`IRQ3
`
`-
`
`-
`
`,
`'
`
`TRANSFORM
`ENGINE
`308
`-
`
`FIG.7
`
`CSCO-1016
`Cisco Systems v. TQ Delta, IPR2016-01760
`Page 8 of 24
`
`

`

`\C = \C
`
`~
`0--,
`~
`....
`
`....
`Ul
`
`\C
`0 .....,
`00
`~ .....
`'Jl =(cid:173)~
`
`\C
`\C
`'"""'
`\C
`'"""' ~
`~ = ?
`
`~ = ......
`~ ......
`~
`•
`\JJ.
`d •
`
`I'
`
`t..
`
`>
`2,2
`
`;<
`
`'C PIO_EB
`
`62
`
`I I
`
`I
`
`FROM CORE --t---1-
`CONTROL
`
`MAC
`
`.. I
`
`B
`
`A
`
`,t 22
`
`"22
`
`MEMORY
`SAMPLE
`RECEIVE
`408
`
`•COEFFICIENT
`I
`
`TAP
`
`MEMORY
`
`404~
`
`,-16
`
`I
`
`I
`
`PROCESS I
`
`•I CONTROL
`
`1
`
`412 .......
`
`r--~
`2:1
`MUX 22
`
`406
`
`22
`
`' <
`22
`
`•!COEFFICIENT
`400,
`
`REGISTER
`
`I
`
`,
`22 ,
`
`I
`
`FIG.B
`
`418
`
`I
`
`'-410
`
`,
`22
`
`: I AND ST A TUS I
`I • I REGISTER ___ t-416
`L OUTPUT
`
`REGISTER
`COMMAND
`
`I
`
`CSCO-1016
`Cisco Systems v. TQ Delta, IPR2016-01760
`Page 9 of 24
`
`

`

`\C = \C
`
`~
`0--,
`~
`....
`
`....
`Ul
`
`\C
`0 .....,
`\C
`~ .....
`'Jl =(cid:173)~
`
`\C
`\C
`'"""'
`\C
`'"""' ~
`~ = ?
`
`~ = ......
`~ ......
`~
`•
`\JJ.
`d •
`
`I
`I
`1ATTEN
`I
`
`FIL T~ 1-l.--
`LC Hpl
`608
`
`I
`
`606
`
`HYBRID
`
`604
`
`620~ POTS I
`
`SPLITTER
`
`,.--78
`
`TXLD
`
`ON-CHIP: OFF-CHIP
`
`c::::J---600
`
`.,
`
`I
`
`I
`I
`
`..
`
`FIG.9
`
`.. 1 VCX0(23:0)
`
`PIO EB
`
`520
`
`v c x 0 I
`
`BLOCK
`CLOCKs-·-1 CLOCK
`DIGITAL
`
`"---------CONRT
`
`518
`
`CLOCKS
`ANALOG
`
`I.
`
`516
`
`DECIMATION
`513
`
`FILTER
`
`IDRIVER
`
`9Ac1 ANALOG
`
`c 507
`
`506
`
`MODULA TOR
`
`I FILTER
`SMOOTHING
`
`DAC(23:0)
`
`502
`
`500
`
`504
`
`(GDB)
`
`CONRT
`
`REGISTER
`CONTROL
`
`522
`
`510
`
`.-----1 ADC(23:0)
`
`INTERPOLATING
`
`FILTER
`
`PIO EB
`
`62
`
`CSCO-1016
`Cisco Systems v. TQ Delta, IPR2016-01760
`Page 10 of 24
`
`

`

`5,909,463
`
`1
`SINGLE-CHIP SOFTWARE CONFIGURABLE
`TRANSCEIVER FOR ASYMMETRIC
`COMMUNICATION SYSTEM
`
`CROSS REFERENCE TO RELATED,
`COPENDING APPLICATIONS
`
`This application is related to a commonly assigned
`copending patent application No. 08/741,635, entitled "An
`Apparatus and Method for Auto-Configuring a Communi(cid:173)
`cation System" invented by Terence L. Johnson et al and
`filed of even date herewith.
`
`FIELD OF THE INVENTION
`
`10
`
`This invention relates generally to communications, and
`more particularly, to a transceiver for an asymmetric com- 15
`munication system.
`
`2
`FIG. 3 illustrates, in partial block and partial logic dia(cid:173)
`gram form, the ADSL transceiver of FIG. 2 configured to
`operate at a central office;
`FIG. 4 illustrates, in partial block and partial logic dia-
`5 gram form, the ADSL transceiver of FIG. 2 configured to
`operate at a remote terminal;
`FIG. 5 illustrates, in block diagram form, the digital
`interface of the ADSL transceiver of FIG. 2;
`FIG. 6 illustrates, in block diagram form, the circular echo
`synthesis module of the ADSL transceiver of FIG. 2;
`FIG. 7 illustrates, in block diagram form, the fast Fourier
`transform module of the ADSL transceiver of the present
`invention;
`FIG. 8 illustrates, in block diagram form, the time domain
`equalization module of the ADSL transceiver of the present
`invention; and
`FIG. 9 illustrates, in block diagram form, the analog
`front-end of the ADSL transceiver of the present invention.
`
`BACKGROUND OF THE INVENTION
`In order to make high data rate interactive services such 20
`as video and internet access available to more residential and
`small business customers, high-speed data communications
`paths are required. Although fiber optic cable is the preferred
`transition media for such high data rate services, it is not
`readily available in existing communication networks and 25
`the expense of installing fiber optic cabling is prohibitive.
`Current telephone wiring connections, which consist of
`copper twisted-pair media, were not originally designed to
`support the data rates or bandwidth required for interactive
`services such as video on demand or even high speed 30
`internet connections. Asymmetric Digital Subscriber Line
`(ADSL) technology has been developed to increase the
`effective bandwidth of existing twisted-pair connections,
`allowing interactive services to be provided without requir(cid:173)
`ing the installation of fiber optic cable.
`Discrete multi-tone (DMT) is a multi-carrier technique
`which divides the available bandwidth of twisted-pair cop(cid:173)
`per media connections into mini-subchannels or bins. The
`DMT technique has been adopted in the ANSI Tl.413
`standard (ADSL standard). In the ADSL standard, DMT is 40
`used to generate 250 separate 4.3125 kilohertz subchannels
`from 26 kilohertz to 1.1 megahertz for downstream trans(cid:173)
`mission to an end user. Likewise, DMT is used to generate
`26 subchannels from 26 kilohertz to 138 kilohertz for
`upstream transmission by an end user. The asymmetric
`transmission protocol implemented by the ADSL standard
`requires a higher rate of data transmission from a central
`office to a remote terminal and a lower rate of data trans(cid:173)
`mission from a remote terminal to a central office. As a
`result, different processing sequences are required at the
`remote terminal and central office ends. Currently available
`systems utilize printed circuit board designs which are
`configured to operate as either a central office end or a
`remote terminal end and may not be used interchangeably as
`an opposite end. Thus, because such separate system designs 55
`are necessary, these separate systems must include separate
`design overhead, separate data bases and separate firmware
`files. Furthermore, each of the separate data bases, separate
`designs, and separate firmware files must all be designed,
`produced, and maintained with finite resources.
`
`DETAILED DESCRIPTION OF THE DRAWINGS
`
`According to the present invention, an ADSL transceiver
`includes a flexible architecture that allows the ADSL trans(cid:173)
`ceiver to be configured through software so that identical
`hardware blocks may be used to perform multiple tasks.
`Thus, the ADSL transceiver may be configured through
`software to operate as either a central office or a remote
`terminal without requiring a substantial amount of added
`circuitry. Therefore, although the ADSL standard requires
`that a transmission data rate at a remote terminal be signifi-
`cantly lower than a transmission data rate at the central
`office, the amount of processing that is performed at either
`the central office end or the remote terminal end is nearly
`35 identical. For example, when the central office end is pro(cid:173)
`cessing data provided at a high rate in its transmit path, the
`remote terminal end is processing high rate data in its
`receive path. Similarly, when the remote terminal end is
`processing data provided at a low rate in its transmit path,
`the central office end is processing low rate data in its receive
`path. The ADSL transceiver recognizes that processing
`functions in the transmit and receive paths of each of the
`central office and remote terminal ends are similar in nature.
`Thus, hardware processing circuitry designed to accommo-
`45 date data transmitted and received at higher data rates may
`also be used to handle data transmitted at lower rates. Stated
`another way, an ADSL transceiver according to the present
`invention recognizes that a particular processing function
`may be utilized in either a transmit or receive data path
`50 depending on whether the ADSL transceiver of the present
`invention is configured to be the central office or the remote
`terminal end.
`In the illustrated embodiment, the transceiver architecture
`is designed using a digital signal processor (DSP) core. It
`should be noted however that other types of processor cores
`could also be implemented. According to the present
`invention, peripheral modules, or processing elements, of
`the transceiver communicate with the DSP processor and are
`implemented as peripheral modules to the DSP processor.
`60 The DSP processor may access each of the peripheral
`modules through a standard memory read/write operation or
`through one of six programmable DMA channels. The DSP
`processor core may be implemented as a core of an
`DSP56301 single chip DSP, which is available from
`65 Motorola, Inc., of Austin, Tex.
`One of the peripheral modules of the transceiver is a host
`processor interface which allows an external user to issue
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 illustrates, in block diagram form, an Asymmetric
`Digital Subscriber Line (ADSL) system in accordance with
`the present invention;
`FIG. 2 illustrates, in block diagram form, an ADSL
`transceiver in accordance with the present invention;
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`performs the same algorithm at both the central office and
`the remote terminal. However, the CES module may be
`configured by the DSP processor core to interpolate its input
`data when it is provided at the remote terminal or to
`5 decimate its output data when it is provided at the central
`office to match the asymmetric data transmission rates
`specified in the ADSL standard. Operation and configuration
`of the CES module will subsequently be described in greater
`detail.
`The present invention also implements an analog circuit
`which provides similar data conversion signal conditioning
`and line interface functions at both the central office and the
`remote terminal. Each of the analog functions described
`above is software configurable to handle differing signaling
`15 characteristics at both the central office and remote terminal
`ends. Operation of the analog module will subsequently be
`described in greater detail.
`In the prior and subsequent descriptions, the term soft(cid:173)
`ware and firmware are used. It is understood that for the
`20 purposes of this discussion the terms software, and firmware
`are used interchangeably.
`
`3
`commands to configure the transceiver for operation as
`either the central office or the remote terminal. Furthermore,
`the host interface may also be accessed by the DSP proces(cid:173)
`sor core. It should be noted that the firmware required for
`performing processing tasks associated with both the central
`office and remote terminal is resident on the single-chip
`transceiver implementation of the present invention. The use
`of both firmware and the recognition that hardware
`resources may be reused allows an ADSL transceiver
`according to the present invention to selectively transfer data
`between the hardware resources and allows memory asso(cid:173)
`ciated with the transceiver to comply with the standard set
`forth in the ADSL standard.
`As previously mentioned, the peripheral modules of the
`transceiver are designed to be configurable by the DSP
`processor core to process tasks as either the central office or
`the remote terminal. One such peripheral module, a digital
`interface, must be able to communicate data at both a high
`rate and a low rate. For a high rate data path, large memories
`are required for frame and constellation buffers used therein.
`Small memories are adequate to handle the status storage in
`a low rate data path. Therefore, the digital interface of the
`present invention includes a single large memory and a
`single small memory for a frame buffer, and another large
`memory and a small memory for the constellation buffer. 25
`When at the central office, the digital interface peripheral is
`configured to have the large memories in the transmit path
`and the small memories in the receive path. At the remote
`terminal, the configuration is reversed. A more detailed
`description of operation of the digital interface peripheral 30
`will subsequently be provided.
`In addition to the digital interface, a hardware fast Fourier
`transform (FF1) module is designed to be able to perform
`both a fast Fourier transform operation and an inverse fast
`Fourier transform operation. When the transceiver of the 35
`present invention is designed to operate as a central office,
`it is placed in the transmit path and is configured to perform
`an inverse fast Fourier transform operation. When the trans(cid:173)
`ceiver of the present invention is configured to operate as a
`remote terminal, the transceiver is placed in the receive path 40
`and is configured to perform a fast Fourier transform opera(cid:173)
`tion. The operation of the FFT module will subsequently be
`described in greater detail.
`Another peripheral module is a time domain equalizer
`(TEQ) module. The TEQ module includes a general finite 45
`impulse response (FIR) filter followed by a biquadratic
`(biquad) infinite impulse response (IIR) filter stage. Each of
`these filters may be set to perform a desired filter operation
`depending on the use of the transceiver as either a central
`office or a remote terminal. The operation of these filters 50
`may be modified by changing the filter coefficients which are
`downloaded by the DSP processor core. At the central office,
`TEQ filter hardware is placed in the transmit path and the
`FIR filter is configured to perform roll off compensation for
`the interpolating filter that follows and the IIR filter is 55
`configured to operate as a high-pass filter. At the remote
`terminal end, the TEQ hardware is placed in the receive
`path, the FIR filter is configured to perform a channel
`shortening function (time-domain equalization), and the IIR
`is configured to operate as a high-pass POTS (plain old 60
`telephone system) filter. Again, operation of the TEQ mod(cid:173)
`ule will subsequently be described in greater detail.
`The transceiver also implements a circular echo synthesis
`(CES) module whose function is modified in response to
`whether the transceiver is configured to a central office or a 65
`remote terminal. The CES module resides between the
`transmit and receive paths of a single transceiver and
`
`Connectivity of the Embodiment
`
`In the following description of the connectivity of the
`present invention, the term "bus" will be used to refer to a
`plurality of signals or conductors which may be used to
`transfer one or more various types of information, such as
`data, addresses, control, or status. The terms "assert" and
`"negate" will be used in referring to the rendering of a
`signal, status bin, or similar apparatus into its logically true
`or logically false state respectively. If the logically true state
`is a logic level one, the logically false state will be a logic
`level zero. And, if the logically true state is a logic level zero,
`the logically false state will be a logic level one.
`Furthermore, the symbol "$" preceding a number indicates
`that the number is represented in its hexadecimal or base 16
`form. The symbol"%" preceding a number indicates that the
`number is represented in its binary or base 2 form.
`FIG. 1 illustrates an ADSL communication system 1.
`ADSL system 1 includes a central office 10 and a remote
`terminal 30 which are connected together via a twisted pair
`of copper wires forming a telephone line 15. Central office
`10 includes a high rate digital interface 2, a hardware IFFT
`(Inverse Fast Fourier Transform) 4, a hardware filters block
`6, a large memory 8, an analog and line interface 12, a small
`memory 14, an echo canceller 16, a low rate digital interface
`18, a software FFT (Fast Fourier Transform) 20, and a
`software filter 22. In central office 10, high rate digital
`interface 2 receives a digital input stream. High rate digital
`interface 2 is bidirectionally coupled to large memory 8 and
`transfers information to hardware IFFT 4. Hardware IFFT 4
`has an output coupled to each of hardware filters block 6 and
`echo canceller 16. Hardware filters block 6 has an output
`coupled to analog and line interface 12. Analog and line
`interface 12 is bidirectionally coupled to telephone line 15,
`and has an output coupled to software filters 22. Both echo
`canceller 16 and software filters 22 have outputs coupled to
`an input of software FFT 20. Software FFT 20 has an output
`coupled to low rate digital interface 18. Low rate digital
`interface 18 is bidirectionally coupled to small memory 14,
`and has an output for providing a digital output stream.
`Remote terminal 30 includes a software filters block 32,
`a software inverse fast Fourier transform (IFFT) 34, a low
`rate digital interface 36, an analog and line interface 38, an
`echo canceller 40, a small memory 42, a large memory 44,
`a hardware filters block 46, a hardware fast Fourier trans-
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`form (FFT) 48, and a high rate digital interface 50. Low rate
`digital interface 36 receives a DIGITAL INPUT STREAM.
`In remote terminal 30, low rate digital interface 36 is
`bidirectionally coupled to small memory 42, and has an
`output coupled to software IFFT 34. Software IFFT 34 has 5
`an output coupled to both the software filters 32 and echo
`canceller 40. Software filters block 32 has an output coupled
`to analog and line interface 38. Analog and line interface 38
`is bidirectionally coupled to telephone line 15 and has an
`output coupled to hardware filters block 46. Both echo
`canceller 40 and hardware filters block 46 are coupled to an
`input of hardware FFT 48. Hardware FFT 48 has an output
`coupled to high rate digital interface 50. High rate digital
`interface 50 is bidirectionally coupled to large memory 44.
`High rate digital interface 50 provides a DIGITAL OUTPUT 15
`STREAM.
`FIG. 2 illustrates an ADSL transceiver 5 in accordance
`with the present invention. ADSL transceiver 5 is a single
`integrated circuit which includes a DSP core 60, a memory
`64, a voltage controlled oscillator (VCXO) 66, a host 20
`processor interface (HPI) 68, a plurality of DSP peripherals
`69, a digital interface 70, and an analog front-end (AFE) 78.
`Note the terms "analog front end" and "analog and line
`interface" are used interchangeably in this specification.
`Digital interface 70 includes a configuration register 71 25
`storing a control bit 72 labeled "CONRT". DSP peripherals
`69 are hardware peripherals including a fast Fourier trans(cid:173)
`form (FFT) module 73, a circular echo synthesis (CES)
`module 74, and a time domain equalizer (TEQ) module 76.
`DSP core 60 has an input terminal for receiving a reset 30
`signal labeled "RESET". DSP core 60 is bidirectionally
`coupled to memory 64 via three dedicated buses labeled
`"PDE", "YDB", and "XDB". DSP core 60 is also bidirec(cid:173)
`tionally coupled to a peripheral bus labeled "PIO_EB" bus
`62. VCXO 66 has an input terminal for connection to a 35
`crystal and receives a signal labeled "CRYSTAL" thereon.
`HPI 68 bidirectionally communicates with an external host
`processor via a port labeled "CONTROL PORT" and bidi(cid:173)
`rectionally communicates with digital interface 70. Digital
`interface 70 bidirectionally communicates with external 40
`memory via a port labeled "INTERLEAVER MEMORY
`PORT" and additional ports which supply or receive labeled
`"DIGITAL PORTS". DSP core 60 bidirectionally commu(cid:173)
`nicates with HPI 68, digital interface 70, FFT module 73,
`CES module 74, TEQ module 76, and analog front-end 78 45
`via PIO_EB bus 62. Analog front-end 78 provides infor(cid:173)
`mation via a signal labeled "TXA PORT" and receives
`information via a signal labeled "RXA PORT".
`FIG. 3 illustrates, in block diagram form, a configuration
`of ADSL transceiver 5 when operating as central office 10. 50
`When configured as central office 10, ADSL transceiver 5
`comprises a digital interface 70, a gains block 80, an inverse
`fast Fourier transform (IFFT) 82, a clip scale 84, a clip filter
`85, cyclic prefix ( CP) adder 86, a high pass filter/droop
`correction filter 88, an analog front-end 78, a high pass filter 55
`92, a circular echo synthesis (CES) module 94, an adder 96,
`an adder 98, a time domain equalizer (TEQ) module 100, a
`fast Fourier transform (FFT) module 102, a phase detector
`104, and a frequency domain equalizer (FEQ) 106. Central
`office 10 also comprises a FREC 81, an IFFT 83, and a scale 60
`87.
`Digital interface 70 has an output coupled to gains block
`80 to provide a signal labeled "OUTPUT DATA". Gains
`block 80 has an output coupled to IFFT 82 and FREC 81.
`FREC 81 has an output coupled to IFFT 83. IFFT 83 has an 65
`output coupled to scale 87. Scale 87 has an output coupled
`to adder 98. IFFT 82 has an output coupled to clip scale 84
`
`6
`and clip filter 85. IFFT 82 is coupled to clip scale 84 to
`implement an IFFT scale factor. Clip scale 84 is coupled to
`scale 87. An output of clip filter 85 is coupled to cyclic prefix
`adder 86 and CES module 94. Cyclic prefix (CP) adder 86
`has an output coupled to high pass filter/droop correction
`filter 88. High pass filter/droop correction filter 88 has an
`output coupled to analog front-end 78. Analog front-end 78
`has an input for receiving a signal labelled "RXAPORT", an
`output for providing a signal labeled "TXA PORT", and an
`output coupled to high pass filter 92. High pass filter 92 has
`an output coupled to adder 96. CES module 94 has an output
`coupled to adder 96. Adder 96 has an output coupled to
`adder 98. Adder 98 has an output coupled to TEQ/CP strip
`module 100. TEQ module 100 has an output coupled to FFT
`module 102. FFT module 102 has an output coupled to both
`FEQ 106 and phase detector 104. Phase detector 104 has an
`output coupled to analog front-end 78. FEQ 106 has an
`output coupled to digital interface 70 providing a signal
`labeled "INPUT DATA".
`FIG. 4 illustrates ADSL transceiver 5 configured to oper(cid:173)
`ate as a remote terminal 30. Remote terminal 30 comprises
`a digital interface 70, a gains block 120, an inverse fast
`Fourier transform (IFFT) module 122, a clipping block 124,
`a CP adder and high pass filter 126, a droop correction filter
`128, a circular echo synthesis (CES) write 130, an FREC
`132, a circular echo synthesis (CES) module 134, an analog
`front-end 78, a time domain equalization (TEQ)/high pass
`filter module 136, a high pass filter and CP stripper 138,
`adder 142, a fast Fourier transform (FF1) module 140, adder
`144, and frequency domain equalizer (FEQ) 146.
`Digital interface 70 has an output coupled to gains block
`120 to provide the OUTPUT DATA signal. Gains block 120
`has an output coupled to IFFT module 122. IFFT module
`122 has an output coupled to clipping block 124. Clipping
`block 124 has an output coupled to FREC 132, CES write
`130, and cycle prefix (CP) adder and high pass filter 126. CP
`adder and high pass filter 126 has an output coupled to droop
`correction filter 128. Droop correction filter 128 has an
`output coupled to analog front-end 78. Analog front-end 78
`has an input for receiving the RXA PORT signal, an output
`for providing the TXA PORT signal, and an output coupled
`to TEQ/high pass filter module 136. TEQ/high pass filter
`module 136 has an output coupled to high pass filter and CP
`strip 138. High pass filter and CP stripper 138 has an output
`coupled to adder 142. CES write 130 has an output coupled
`to CES module 134. CES module 134 has an output coupled
`to adder 142. Adder 142 has an output coupled to FFT
`module 140. FFTmodule 140 has an output coupled to adder
`144. FREC 132 has an output coupled to adder 144. Adder
`144 has an output coupled FEQ 146. FEQ 146 has an output
`coupled to digital interface 70 to provide an INPUT DATA
`signal.
`FIG. 5 illustrates digital interface 70 in greater detail.
`Digital interface 70 generally includes a constellation circuit
`150, a transmit circuit 166, a receive circuit 168, and a frame
`buffer circuit 170. Constellation circuit 150 includes a
`CONRT bit 72, a multiplexer 156, a multiplexer 154, a large
`memory 158, a small memory 160, multiplexer 162, and a
`multiplexer 164. Frame buffer circuit 170 comprises a
`multiplexer 172, a multiplexer 174, a large memory 176, a
`small memory 178, a multiplexer 180, and a multiplexer
`182.
`The INPUT DATA signal is provided to a first input of
`multiplexer 156 and a first input of multiplexer 154. An
`output of transmit circuit 166 is coupled to a second input of
`each of multiplexers 154 and 156. CONRT bit 72 is coupled
`to an enable input of multiplexer 154, multiplexer 156,
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`multiplexer 162, multiplexer 164, multiplexer 172, multi(cid:173)
`plexer 174, multiplexer 180, and multiplexer 182. An output
`