`
`3L “1+4? 0
`
`‘
`
`Approved for use through 01/31/2001. OMB 0651- 0037
`Patent and Trademark Office; U. 8. DEPARTMENT OF COMMERCE
`
`AW PTO/SB/16 (2-98)
`
`his is a request for filing a PROVISIONAL APPLICATION under 37 C.F.R. §1.S3(c).
`
`PROVISIONAL APPLICATION COVER SHEET
`
`WW
`
` 0060/10WWWNWOIL'II‘DLLEOD
`
`
`
`Docket Number
`
`8011-7
`
`Type a plus sign (+)
`inside this box a
`
`INVENTOR(S)/APPLICANT(S)
`
`MIDDLE
`INITIAL
`
`RESIDENCE (CITY AND EITHER STATE OR FOREIGN COUNTRY)
`
`+
`
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`
`
`
`
`
`
`LAST NAME
`
`FIRST NAME
`
`
`
`
`a);
`11 Wamous Close, Armonk, New York 10504
`James
`Fallon
`g
`
`
`
`
`~:§§
`362 Christopher Street, Oceanside, New York 11572
`John
`Buck
`;§
`
`
`:Dc—q
`225 Stewart Avenue, Bethpage, New York 11714
`Paul
`Pickel
`g5
`
`
`
`
`
`ijégi‘
`\\
`McEerlain
`Stephen
`325 East 17"h Street, New York, New York 10003
`
`
`ég
`Nolf-Sonkin
`Yury
`160 Kings Point Road, Kings Point, New York 11024
`512;;
`
`
`
`TITLE OF THE INVENTION (280 characters max)
`
`DATA STORAGE AND RETRIEVAL ACCELERATOR
`
`
`CORRESPONDENCE ADDRESS
`
`CHAU & ASSOCIATES, LLP
`
`
`1900 FHem-stead Turn-ike, Suite 501
`
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`11554
`mum _
`that a-cly)
`ENCLOSED APPLICATION PARTS (check all
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`Specification & Drawings
`Number of Pages
`108
`3
`Small Entity Statement
`
`
`Other (specify)
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`
`METHOD OF PAYMENT (check one)
`
`PROVISIONAL
`
`E
`A check in the amount of $ 75.00 to cover the filing fee
`
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`FILING FEE
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`D Charge fee to Deposit Account Number 50-0679.
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`Please charge any deficiency as well as any other fee(s)
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`No. 50-0679.
`TWO (2) COPIES OF THIS SHEET ARE ENCLOSED.
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`
`CERTIFICATION UNDER 37 C.F.R.
`1.10
`I hereby certify that this Provisional Application Cover Sheet and the documents referred to as enclosed therein
`are being deposited with the United States Postal Service on this date February 3, 2000 in an envelope as “Express
`Mail Post Office to Addressee" Mail Label Number EL433927955US addressed to: Commissioner of Patents and Trademarks,
`Box Provisional Application, Washington, D.C.
`20231.
`
`Frank V. DeRosa
`(Type or print name of person mailing paper)
`
`
`
`page 1 of 2
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`W(
`
`Signature of person mailing paper)
`
`Realtime 2010
`
`Page 1 of 112
`
`Realtime 2010
`Page 1 of 112
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`

`

`4
`
`The invention was made by an agency of the United States Government o r under a contract with an agency of the United
`States Government.
`
`El N o .
`0 Ye s , the name of the U.S. Government agency and the Government contract number are:
`
`Respectfully submitted,
`
`SIGNATURE
`TYPED or PRINTED NAME Frank V. DeRosa R e
`
`g
`
`i
`
`s
`
`t
`
`r
`
`a
`
` No. 43.584
`( i f appropriate)
`El Additional inventors are being named on separately numbered sheets attached hereto.
`
`Date
`i
`
`t
`
`o
`
`n
`
`page 2 of 2
`
`Realtime 2010
`Page 2 of 112
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`

`

`FATENT
`Attorneys Docket No. 8011-7
`
`Applicant or ?alcove:
`Serial or Patent No.: 0 / 110aSsigned
`•
`
`Filed or Issued: _ S s u l g u a i d i
`F o r : _ 1 2 Z a & f : E Q B Z b a k A N J 2 j g a l t y A L A c a l y . , M M R _ _ _ _
`VERIFIED STATEMLNT CLAIMING SMALL ENTITY
`STATUS (37 CFR 1.9(1) and 1,27(c)) • SMALL BUSINESS CONCERN
`I hereby declare that I am
`El the owner of the aaI1 business concern identified hclow:
`
`kg an official of the small business enneern etnpowered to act on behalf of the
`concern identified below:
`NAME OF SMALL BUSINESS CONCERN Ikealdme Data,,LLC,
`ADDRESS OF SMALL BUSINESS CONCERN _2ZLE,1,103 Str t New Yprk. Nw York 10021
`
`I hereby declare that the above identified small business concern qualities as a small business concern as
`defined in 13 CFR 121.12, and reproduced in 37 CFR 1.9(d), for purposes of paying reduced fees to
`the United States Patent and Ttarienhitk Office under Section 41(a) and (b) of Title 35, United States
`Code. in 011it the number of employees of the concern, including those of its affiliates, does not exceed
`500 persons. For purposes of this suitement, (1) the number of employees of the business concern is the
`average over the previous fiscal year of the concern of the persons employed on a full-time, part-time or
`temporary basis during each of the pay periods of the fiscal year, and (2) concerns are affiliates of each
`other when either, directly or indirectly, one concern controls or has the power to control the other, or a
`third-party or parties controls or has the power to control both.
`[hereby declare that rights under contract or law have been conveyed to, and remain with, the small
`business concern identified above, with regard to the invention described in
`
`the specification filed hcrcwith.
`
`Cl application serial no, 0 I _ , tiled
`0 patent no.
`, issued
`If the rights held by the above identified small business concern are not exclusive, each individual,
`concern or organization having rights in the invention is listed below* and no rights to the invention are
`held by any person, Othur than the inventor, who would not qualify as an independent irrventor under 37
`CPR 1,9(c) if that person made the invention, or by any concern which would not qualify as s small
`business concern under 37 CFR 1.9(d) or a nonprofit organization under 37 CFR I .9(c).
`"NOTE: Separate verified statements amr. required from each named person, conern
`or organization having rights t o the inveintion averrtotf to their status as small
`entities, (37 CFR 1,27),
`
`(Small Entity•SMAII BlAiliteAA C7-41--Nge 1 o f 2)
`
`4
`
`Realtime 2010
`Page 3 of 112
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`

`

`Each such oemom concern or organization having any rights in the invention is listed below:
`
`El N o such pamm, concern, Of organi2atton emu,
`
`a E t h e It such person, concern or Of gatitzation is listed nelow.
`
`FULL NAME
`
`ADDRESS
`
`0 Individual C I Small Busutes1 Coocern C l Nonprofit Organization
`FULL NAME
`ADDRESS
`CI Individual
`
`0 Small
`
` Business Concern 0 Nonprofit Organization
`
`I acknowledge the duty to file, in this application or patent, netificarion of any change in status resuhing in loss of
`entitlement En =all entity status Prior to paying. or at the time of paying. the earliest of the issue fee or any
`maintenance fee due after (he date on which status as a strain business entity Is no longer appropriate. (37 CFR
`I S M .
`I hereby declare that all statements made herein of my own knowledge are true and that all statetecnu made on
`information and belief are believed to he true: and ?Oiler that these statements weft made with the knowledge that
`willful false statements and the like 30 made arc punishable by fine or IMprittennienti or.both, under Section 1001 of
`Title 18 of the United States Code. and that such w.flful MSc statements may jeopardize the validity of the application,
`any potent issuing theston, or any patent to which this veritled statement ia directed,
`
`NAME OF MASON SIONINO J a r n e $ , I Fithou
`TITLE OF PERSON 11: 071,101'.111AN OWNER Q u i n l a n
`
`ADDRESS OF FERSON NIONING 11 Watnnus O w . ArtroAls. New York 10504
`
`(Small Entity-Sircsit EuSW6SS17-4)--pagc 2 of 2)
`
`Realtime 2010
`Page 4 of 112
`
`

`

`DATA STORAGE
`RETRIEVAL ACCELERATOR
`
`Realtime 2010
`Page 5 of 112
`
`

`

`PREFACE
`This manual describes the principles of operation, performance specifications, and detailed design of the
`Realtime Data, LLC UltraDMA Data Storage and Retrieval Accelerator (hereinafter affectionately
`referred to as the DSRA). This document begins with a brief introduction to fundamental performance
`limitations of current disk drives and the dramatic benefits provided by our DSRA. This is followed by a
`detailed DSRA performance specification. Next, a system overview is presented from a logical (not
`necessarily physical) functional partitioning with an emphasis on intrafunction dataflow and system level
`dynamic bandwidth allocation. A detailed block diagram is then presented and the function of each
`component is discussed in detail. Address maps are presented from the perspective of the onboard digital
`signal processor, disk controller, and PCI controller along with a view from the host PCI Bus. Available
`Interrupts and their allocation are discussed. Separate sections describe the internal architecture of the
`onboard field programmable gate array, programming the field programmable gate array, and the DSRA's
`reset and initialization methodology. Finally a software guide to the DSRA's command protocol is
`covered with a detailed specification of each DSRA command. Appendices list reference information
`including board component placement, a numerical listing of jumpers, external connectors for the
`UltraDMA disk interface and the PCI Bus, detailed schematics and a fully cross referenced parts list.
`
`The DSRA is the represents Realtime's first product in our comprehensive family of data storage
`controllers, network data storage, and data centric secure networking. Our technology represents the next
`logical step in the evolution of high perfoiniance data storage and completely secure high bandwidth data
`transmission. Employing industry standard interfaces and protocols that seamlessly integrate with
`existing media devices, our product offers a many-fold increase in data storage density, access speed, and
`security. This approach overcomes the traditional bottlenecks associated with local and network disk data
`accesses. In order to achieve this level of performance our proprietary data compression and encryption
`engine reads one byte of data stored on disk and decodes this information into multiple bytes of
`information for the computer. By implementing this process in a combination of dedicated hardware and
`an ultra high speed digital signal processor the translation takes place in "real-time". Thus, rather than the
`traditional delays normally associated with software data compression, our hardware approach creates a
`many-fold performance improvement. Our technology is designed to be Scalable through each successive
`computer generation; Adaptable to serve multiple functions concurrently, increasing performance and
`enhancing value; Insertable to seamlessly integrate into existing marketplaces — modifications to existing
`standards are not required. Our Value Proposition is Product Excellence through Innovation. Our
`technology creates the state-of-the-art; is easy to install and use, and is flawlessly reliable.
`
`Realtime 2010
`Page 6 of 112
`
`

`

`NOTATIONAL CONVENTIONS
`This manual utilizes the following conventions and nomenclature:
`Register Diagrams
`Register diagrams are presented as follows:
`
`External Interrupt Polarity Register
`
`31
`
`t4t,
`
`4
`
`3
`
`0
`1
`2
`XIP7 X I P 6 X I P 5 X I P 4
`Reserved
`RW, +0
`R, +0
`R, +0
`RW, +0
`RW, +0
`All register diagrams, unless otherwise noted, utilize the following notational conventions:
`Each rectangle represents a logically related group of bits called a bit field.
`Mnemonics for each field name is given within the rectangle.
`Numbers directly above the bit field represent starting and ending bit locations (inclusive).
`Properties are listed directly below each bit field.
`R — Readable by the DSP's CPU
`W Writeable by the DSP's CPU
`= Value undefined after DSP reset
`+0 = Value is 0 after DSP reset
`+1 = Value is 1 after DSP reset
`C = Clearable by the DSP's CPU
`
`3
`
`Realtime 2010
`Page 7 of 112
`
`

`

`Software Notation
`
`Program Listings are in c o u r i e r f o n t
`LDW . D 1 * A O , A l
`ADD . L 1 A 1 , A 2 , A 3
`
`All data is presented and utilized in little endian notation.
`
`In syntax descriptions, the command is in bold face, and parameters are in italics. Portions of a syntax
`that are in bold should be entered as shown; portions of a syntax that are in italics describe the type of
`information that should be entered. Here is an example of a command syntax:
`
`READ DISK DATA
`31
`
`16 1 5
`
`8
`
`7
`
`0
`
`Command
`Command Packet Number
`C o m ma n d Type
`Parameters (00h)
`00h
`0000h to FFFFh
`Starting Block Address (Least Significant Word)
`Starting Block Address (Most Significant Word)
`Number of Blocks (Least Significant Word)
`Number of Blocks (Most Significant Word)
`Destination Address (Least Significant Word)
`Destination Address Most Significant Word)
`Reserved
`[Checksum]
`
`00h
`
`04h
`08h
`OCh
`10h
`14h
`
`18h
`1Ch
`
`Square brackets ( [ and ] ) identify an optional parameter. If you use an optional parameter, you specify
`the information within the brackets; you do not enter the brackets themselves. When there is a choice
`amongst multiple items they are separated by a I , for example a I b is a selection of either a or b, but not
`both.
`
`Realtime 2010
`Page 8 of 112
`
`

`

`Hardware Notation
`
`DSRA busses and integrated circuit pins often are represented in groups. Device pin group notation
`consists of the pin name followed by brackets containing the range of pins included in the group. A colon
`separates the numbers in the range. For example, ED[3 1:0] represents the 32 bit DSP external data bus.
`
`Caution Statements
`
`A caution statement describes a situation that could potentially damage the DSRA, host computer, or
`software.
`
`c7kr
`
`•
`
`Warning Statements
`
`. A warning statement describes a situation that could potentially cause you injury or death.
`
`4,4r,
`
`7,77-
`
`Caution and Warning Statements are provided for your protection. Please read each caution and warning
`t- carefully.
`
`• :7
`
`Realtime 2010
`Page 9 of 112
`
`

`

`REALTIME DATA, LLC
`
`U1traDMA/66 Data Storage & Retrieval Accelerator
`
`Section
`
`T
`
`i
`
`t
`
`TABLE OF CONTENTS
`l
`e
`
`P
`
`a
`
`8
`
`1
`
`1
`
`1
`
`4
`
`e
`
`g
`
`0
`
`4
`
`4
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1.0 INTRODUCTION
`2.0 PERFORMANCE SPECIFICATION
`3.0 SYSTEM OVERVIEW
`4.0 DETAILED BLOCK DIAGRAM
`4.1 Master Oscillator
`4.2 Digital Signal Processor
`4.3 OTP EPROM
`4.4 SDRAM
`5.0 MEMORY MAPPING
`6.0 MEMORY BANDWIDTH ALLOCATION
`7.0 INTERRUPTS
`2
`7.1 Interrupt Multiplexer Register
`7.2 External Interrupt Polarity Register
`8.0 A T A AND ULTRA DMA/66 DISK INTERFACE
`8.1 Operational Registers
`2
`8.2 Sample ATA Command Sequence
`8,3 State Diagrams
`8.4 Ultra DMA66 Disk Interface
`8.4.1 Wr i t e Transaction
`8.4.2 Read Transaction
`8.5 Timing Diagrams
`8.5.1 Read Timing
`8.5.2 Wr i t e Timing
`9.0 XILINX ARCHITECTURE
`9.1 Block Diagram
`9.2 Register Map
`
`3
`3
`
`3
`3
`3
`
`2
`
`4
`
`1
`
`2
`
`2
`
`2
`
`2
`
`9
`
`5
`
`4
`
`4
`
`7
`
`7
`
`4
`
`6
`
`2
`
`5
`
`9
`
`4
`5
`
`6
`6
`9
`
`4
`
`2
`
`2
`
`Realtime 2010
`Page 10 of 112
`
`

`

`5
`5
`
`5
`
`5
`
`11,A
`
`10.0 XILINX PROGRAMMING
`11.0 DSRA INITIALIZATION & RESET
`11.1 Reset Sequence
`11.2 Initialization Sequence
`11.2.1 Internal Memory
`11.2.2 EDMA
`11.2.3 EMIF
`5
`11.2.4 Interrupts
`11.3 Instant Boot Device / Application Quick Launch
`12.0 COMMAND PROTOCOL
`5
`12.1 Command List
`12.1.1 Read Disk Data
`12.1.2 Write Disk Data
`12.1.3 Copy Disk Data
`12.1.4 Format Virtual Disk
`12.1.5 Disk Recovery
`12.1.6 Read Disk Status
`12.2 Command and Data Interface
`12.2.1 Data Write Transaction
`12.2.1 Data Read Transaction
`12.3 Command Protocol Errors
`12.4 Command Acquistion
`12.5 Command Execution
`13.0 EPROM PROGRAMMING
`
`4
`
`5
`5
`
`6
`6
`6
`
`6
`
`6
`
`7
`7
`
`6
`
`6
`6
`6
`7
`
`7
`
`Title
`
`Appendix
`A B o a r d Layout
`Jumper Listing
`UltraDMA Connector
`PCI Bus Connector
`Schematics
`F P a r t s List
`Boot Configuration Circuit
`
`5
`
`1
`
`2
`2
`
`5
`
`8
`
`5
`
`4
`
`1
`
`1
`1
`
`8
`
`6
`
`0
`1
`2
`3
`
`4
`5
`
`6
`8
`9
`0
`
`1
`2
`
`5
`
`Page
`A-1
`B-1
`C-1
`D-1
`E-1
`F-1
`G-1
`
`Realtime 2010
`Page 11 of 112
`
`

`

`1.0 INTRODUCTION
`
`The Challenge
`Modem Personal Computers have steadily increased in performance through advances in processor,
`memory and data communications bandwidth. In stark contrast, magnetic hard disk devices have not kept
`pace with this revolution. In fact, even the highest performance disk storage devices severely limit the
`capability of consumer, entertainment, office, and workstation personal computers (PCs) for all disk
`intensive operations. Hard disk storage devices house the computer's operating system, application
`programs, and data. Rapid access to this information, or bandwidth, is a critical factor in overall
`computer performance. In normal operation, the computer's operating system issues a request for data.
`This data might be a new program to execute or data for a program currently running. The disk controller
`*ri commands the disk to "seek" the requisite data. Three factors then limit disk performance:
`1. the time to position the read/write heads over the appropriate disk cylinder (seek time);
`2. the time for the disk to rotate under the read/write head to the beginning of data (rotational
`latency); and
`3. the time to read each byte of data from the disk (read/write bandwidth).
`Items one and two are typically incurred only once per disk access while read/write bandwidth limitations
`g are encountered for each byte of data requested. Currently the fastest available disk drives (10,200rpm)
`offer only a 18 Megabyte (MB/sec) per second data access rate. This is in stark contrast to PC's input /
`output (I/O) bus capability of 264 MB/sec. In short, the best available disks are 15 times too slow to
`match a PC's capabilities. A typical consumer hard disk drive performance utilizing U1traDMA/66 is
`often off by a factor of 100 or more.
`- Industry has generated several inadequate and costly solutions to address disk bandwidth limitations.
`Emergent high performance disk interface standards such as the Small Computer Systems Interface
`(SCSI-3) and Fibre Channel offer the ability to communicate at improved data transfer rates. These
`standards do not solve the hard disk's inherent physical media restriction of 17 MB/sec. Higher disk
`access data rates have only been achieved simultaneously reading or writing multiple disk drives. This is
`a costly and complex approach.
`
`The Solution
`Realtime's family of storage controllers and network data storage represents the next logical step in the
`evolution of high performance data storage. Employing industry standard interfaces and protocols that
`seamlessly integrate with existing media devices, our product offers a three-fold increase in data storage
`density and access speed. This approach overcomes the traditional bottlenecks associated with local and
`network disk data accesses.
`Our proprietary data compression engine reads one byte of data stored on disk and decodes this
`information into three bytes of information for the computer. By implementing this process in a
`combination of dedicated hardware and ultra high speed digital signal processors, the translation takes
`place in "real-time". Thus, rather than the traditional delays normally associated with software data
`compression, our hardware approach creates a three-fold performance increase.
`
`Realtime 2010
`Page 12 of 112
`
`

`

`Our first product, the Realtime Data Storage and Retrieval Accelerator (affectionately referred to as the
`DSRA) represents the state of the art in UltraDMA Disk Storage Adapters. Applying new discoveries in
`information theory, combined with artificial intelligence based application and data management
`algorithms, Realtime's technology dramatically accelerates computer performance and significantly
`increases hard disk data storage capacity. For personal computers running standard Microsoft Windows®
`based business application software:
`Disk storage capacity is typically increased by a factor of 3:1 (for example a 20 gigabyte hard
`drive effectively becomes a 60 gigabyte hard drive).
`Computer boot-up time (turn-on and operating system load) is decreased by a factor of two.
`Application software (for example Microsoft Office Programs) load twice as fast.
`User data storage and retrieval is increased (on average) by a factor of 3:1.
`
`•=1,
`
`Realtime 2010
`Page 13 of 112
`
`

`

`2.0 PERFORMANCE SPECIFICATION
`
`.i•••••••i!
`••••=i:
`
`Storage Device
`Interface
`
`PCI Bus
`Interface
`
`Command Set
`
`OnBoard
`Memory
`Data
`Compression
`
`Software
`Support
`Internal Interface
`Connectors
`External
`Interface
`Connectors
`Dimensions
`Power
`Mass
`Temperature
`
`Humidity
`
`MTBF
`
`U1traDMA/66
`Implemented in Dynamically Reprouammable Custom FPGA
`Full DMA to Local DSP & PCI Busses ($ gigabyte burst capability)
`PCI Bus Master/Slave Interface, 32 Bit Data, 64 Bit Address
`Zero Bus Wait States Disk Controller PCI Bus Master Data Transfers
`Zero Bus Wait State Multi Command Slave Mode Queue
`Implemented in Dynamically Reprogrammable Custom FPGA
`Full DMA Capability
`Fully Transparent PCI Master Data Storage Controller
`High Level Command Set Facilitates PO Channel Offload of Host Processor
`Full Self Diagnostics & SMART Diagnostic Support
`32 Megabytes
`
`Embedded 1.2 Billion Instruction per second, 32 Bit Digital Signal Processor
`Proprietary Information Processing & Artificial Intelligence Data Storage
`Management
`Windows 98 & Windows NT 5.0
`Utilities for Installation and Data Storage Management
`One 32 Bit PCI Bus Board Edge Connector
`One U1traDMA/66 40 Pin Header
`None
`
`6.875"(I), 4.187"(w), 0.500"(h)
`Less than 10.0 Watts (max)
`6.0 Ounces
` M a x Slew 15°C per hour
`0 to -1-50°C,
`Operating:
`NonOperating: --40 to +70°C M a x Slew 20°C per hour
`Operating
`1
`0
` to 85% M a x Slew 10% per hour
`NonOperating: 5 to 95% M a x Slew 10% per hour
`—500,000 hours g 40°C
`
`to
`
`Realtime 2010
`Page 14 of 112
`
`

`

`3.0 SYSTEM OVERVIEW
`
`Figure 2-1, UltraDMA Data Storage and Retrieval Accelerator (DSRA) Architecture, highlights the data
`internal flows and external interfaces for our storage controller.
`
`DATA
`COMPRESSION
`ENGINE
`
`32 MEGABYTES
`ONBOARD
`CACHE
`
`ULTRADMA / 66
`DISK
`INTERFACE
`
`PCI BUS INTERFACE
`
`REAL ATA
`
`4
`
`PC EXPANSION BUS
`
`3 3
`'••=3'
`
`ULTRADMA / 66
`DISK
`
`Compressed
`6.0 Megabytes/Sec
`
`Decompressed
`18.0 Megabytes/Sec
`
`The data flow architecture of the DSRA provides maximum system bandwidth by allowing simultaneous
`data transfers between:
`disk and onboard cache memory,
`DCE and onboard memory,
`PCI Bus and onboard memory.
`The DCE, disk interface, and PCI Bus controller have full DMA capability and are able to transfer data
`without interrupting or interfering with any other ongoing processes. An integral round robin arbitration
`bandwidth allocation controller allows the disk controller, DCE, and PCI Bus to access the onboard cache
`with a bandwidth proportional to the overall bandwidth of the respective interface or processing element.
`Arbitration happens transparently and does not introduce latency in memory accesses. Bandwidth
`division is performed with a high degree of granularity to minimize the size of requisite onboard buffers
`to synchronize data from the disk and PCI interfaces. Details of the PCI and Disk Interface are contained
`within the Xilinx FPGA Design Section contained within this document.
`Disk Read / Write Data Transfers
`
`Realtime 2010
`Page 15 of 112
`
`

`

`1
`
`When data is read from disk by the host computer data flows from the disk through the DSRA to the host
`computer. Data is normally stored in one of several proprietary compression formats on the disk. Data
`blocks are pre-specified in length and are typically handled in fractional or whole equivalents of tracks,
`e.g. 1/2 track, whole track, multiple tracks... Since tracks may contain variable numbers of sectors this is
`not always possible. In order to read disk data a DMA transfer is setup from the disk interface to the
`onboard cache memory. The disk interface has integral DMA control to allow transfers from disk to
`directly to the onboard 32 megabytes of cache without DCE intervention. It should be noted that the DCE
`acts as a system level controller and is used to set-up specific registers within both the disk and PCI
`Interfaces to facilitate DMA transfers to and from DSRA cache memory.
`To initiate a transfer from disk to onboard cache, the DMA Transfer is setup via specifying the
`appropriate command (read disk), the source address (disk logical block number), amount of data to be
`transferred (number of disk logical blocks), and destination address within the onboard cache memory.
`Finally the DISKINT# is cleared (if previously set and not cleared) and the command is initiated by
`writing to the appropriate address space.
`Once data has been read from disk and placed into onboard cache memory the DISKINT# is asserted
`notifying the DCE that requested data is now available in the DSRA's cache memory. Data is then read
`by the DCE's onboard DMA controller and placed into local memory for subsequent decompression. The
`decompressed data is then DMA transferred from the DCE's local memory back to the DSRA's 32
`megabyte cache memory. Finally, data is DMA transferred via the DSRA's PCI Bus controller from the
`32 megabyte cache to the host computer's PCI Bus. In this mode the DSRA acts as a PCI Bus Master. A
`DSRA PCI DMA transfer is setup via specifying the appropriate command (write to host computer), the
`source address within the DSRA's cache memory, the quantity of data words to be transferred (transfers
`are always in 4 byte increments and memory should always be viewed in only 4 byte clusters beginning
`with address NO), and the destination address on the host computer. When a PCI Bus read or write
`transaction has completed the appropriate PCIRDINT# and PCIWRINT# are asserted to the DCE. Either
`interrupts is cleared by it's corresponding interrupt service routines through a read or write to the
`appropriate DCE address.
`Similarly, when data is written to disk from the host computer, data flows from the host computer through
`the DSRA and onto disk. Data is normally received from the host computer in uncompressed (raw)
`folinat and must be compressed by the DCE to be stored in one of several proprietary compression
`formats on the disk. Data blocks from the host are pre-specified in length and are typically handled in
`blocks that are a fixed multiplier higher than fractional or whole equivalents of tracks, e.g. 1/2 track, whole
`track, multiple tracks... This multiplier is derived from the expected average compression ratio that is
`selected when the disk is formatted with the virtual file management system. I n order to read host
`computer data a PCI DMA transfer is setup from the PCI Host Bus to the onboard cache memory. The
`DSRA's PCI interface controller has integral DMA that allows large block transfers from the host
`computer directly to the onboard 32 megabytes of cache without DCE intervention. The DSRA's PCI
`Bus controller acts as a host computer bus master when executing this transfer. Once data has been read
`from the host and placed into onboard cache memory the data is read by the DCE's onboard DMA
`controller and placed into local memory for subsequent compression. The compressed data is then DMA
`transferred from the DCE's local memory back to the DSRA's 32 megabyte cache memory. Finally, data
`is DMA Transferred via the Disk Controller from the 32 megabyte cache to the disk.
`Commands
`
`2,
`
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`

`

`Upon host computer power-up or external user reset, the DSRA initializes onboard interfaces prior to
`release of the external PC expansion Bus from reset. The host computer's processor then requests initial
`data from the disk to facilitate the computer's boot-up sequence. Disk data is requested over the PCI
`Expansion Bus via a command packet issued from the host computer. Command packets are eight words
`long (words are 32 bit in this context). Commands are written from the host computer to the DSRA with
`the host computer as bus master and the DSRA as slave. The DSRA includes a single PCI Base Address
`Register (BARO) for decoding the address of the DSRA command queue.
`When a command is received and a PCICMDINT# interrupt is generated to the digital signal processor
`(DSP) within the data compression engine (DCE). The eight word command is read by the DCE and
`placed into the command queue that resides either within onboard DCE memory or within the DSRA's 32
`megabytes of onboard cache. Because the commands occupy a very small amount of memory the
`location of the command queue is at the discretion of software and the associated system level
`performance considerations. Commands may be moved from the PCI bus interface to the command
`queue by explicit DSP reads and writes or by utilizing programmed DMA from the DSP's Enhanced
`DMA Controller (EDMA). This second technique may better facilitate system throughput by allowing
`the EDMA to automatically load commands while the highly pipelined data compression and
`decompression processing transpires fully undisturbed.
`
`,
`
`k r . : 1
`
`13
`
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`Page 17 of 112
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`

`

`4.0 D E TA I L E D BLOCK DIAGRAM
`
`Figure 2-2 presents a board level overview of our UltraDMA Data Storage and Retrieval Accelerator
`(DSRA). As shown, the DSRA is designed with a minimum of components for low cost, minimum
`power consumption, a small printed circuit board footprint, and high reliability.
`4.1 M a s t e r Oscillator
`Both the DSP's and DSRA's master clock is generated from an onboard 35 MHz oscillator. The DSP
`incorporates a by four phase lock loop, yielding a DSP clock of 140MHz. The DSP internally divides this
`clock by a factor of two down to 70MHz for clocking the DSRA's SDRAM.
`4.2 D i g i t a l Signal Processor
`The primary processing element on the DSRA is a Texas Instruments (TI) TMS320C6211GFN-150
`Digital Signal Processor (DSP) housed in a Chip Scale 256 pin Ball Grid Array (BOA) package.
`Utilizing a 5 level metailzation 0.18um cmos technology, 3.3volt I/O, and a 1.8volt core, our DSP is
`al capable of up to 1.2 Billion Instructions per Second. Additional features of interest include a highly
`parallel eight processor single cycle instruction execution, onboard 4K byte LIP Program Cache, 4K L1D
`Data Cache, and 64K byte Unified L2 Program/Data Cache. A 32 bit External Memory Interface (EMT),
`also resident on the DSP, provides for a glueless interface to the two banks of SDRAM along with the
`non-volatile One Time (Erasable) Programmable Memory (OTP-EPROM). Two Multi-Channel Buffered
`Serial Ports (McBSPs) and two 32 bit General Purpose Timers are also included within the DSP. The
`DSRA disables the I/O Capability of these devices ands utilizes the 110 ports as general purpose I/O for
`both programming the FPGA with a strobed eight bit interface and signaling via a Light Emitting Diode
`(LED). Ancillary DSP features include a 16 bit Host Port Interface and full JTAG emulation capability
`for development support.
`— 4.3 O T P EPROM
`Nonvolatile storage is provide by a 128K byte M27W101-80K one time (erasable) programmable
`memory. This device is decoded at the DSP's Chip Enable CE I space (see Memory Map Section in this
`document for further details). The lower 80K bytes are utilized for program storage with the first lk bytes
`utilized for the DSP's boot loader. Upon DSP reset the first 1K of OTP EPROM is copied into Internal
`RAM by the DSP's Enhanced DMA Controller (EDMA). Although the boot process begins when the
`DSP is released from external reset, the transfer actually occurs while the CPU is internally held in reset.
`This methodology allows for selection of the boot prom width (in our case 8 bits). After completion of
`the 1K block transfer, the CPU is removed from reset and execution begins at address Ox0.
`The upper 48K bytes of the OTP EPROM is utilized for storage of FPGA Data. Since the DSRA is
`typically the primary boot storage device on the host computer, the interface to both the PCI Bus and the
`Disk must be stored on the DSRA and loaded prior to release of the PCI Bus from Reset. Revision 2.2 of
`the PCI Local Bus Specification is still quite lax in it's specification of a host computer's power on
`sequencing. The specification calls for a typical delay of 100msec from power-stable before release of
`PCI Reset. In practice this delay is currently 200msec although this varies amongst computer
`manufacturers. A detailed discussion of the power-on sequencing and boot operation of the DSRA is
`contained in the PCI Reset Section of this document.
`
`/
`
`Realtime 2010
`Page 18 of 112
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`

`

`--ECLK÷
`
`—CLK2—
`
`MASTER I t
`OSC
`&
`PLL
`MODULE
`
`—0SC+
`
`PLIA.
`
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`
`N M I #
`PCICMDINT#
`PCIMRDINT#
`PCIMWRINT#
`DISKINT#
`
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`HOLDA#
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`DIGITAL SIGNAL
`PROCESSOR
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`
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`TC59S6418BFT-10
`4Mx32
`EXTERNAL MEMORY
`SDRAM
`Qty 2
`
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`toshiba
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`EXTERNAL MEMORY
`SDRAM
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`SMODECONTROL
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`CLKMODE—
`
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`A R D Y
`
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`
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`
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`MODE
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`1/4
`
`Realtime Data Compression Systems Prc
`
`ir
`
`Realtime 2010
`Page 19 of 112
`
`

`

`cc
`- 01–
`00
`zz
`1.0K 82 L °
`W V0
`0
`
`82
`
`I/O Read (DIORC----*
`I/O Write (DIOW#)-----*
`
`— C h i p Select 0 (DCSO#)--*
`C h i pSelect1 (DCS1#)—*
`
`Device Address DAr2:0I
`
`DMA Acknowledge (DMACK#)–*
`
`Reset (DRESETIO—*
`
`4I---1/0 Ready (IORDY)
`
`4 - - Device Active (DASP#)
`
`NC
`
`.4–Interrupt Request (INTRQ)—
`
`-4—DM