TLC545C, TLC545I, TLC546C, TLC546I
`8-BIT ANALOG-TO-DIGITAL CONVERTERS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
`
`N PACKAGE
`(TOP VIEW)
`
`28
`27
`26
`25
`24
`23
`22
`21
`20
`19
`18
`17
`16
`15
`
`VCC
`SYSTEM CLOCK
`I/O CLOCK
`ADDRESS INPUT
`DATA OUT
`CS
`REF +
`REF –
`INPUT A18
`INPUT A17
`INPUT A16
`INPUT A15
`INPUT A14
`INPUT A13
`
`1 2 3 4
`
`
`
`5 6 7 8 9 1
`
`0
`11
`12
`13
`14
`
`INPUT A0
`INPUT A1
`INPUT A2
`INPUT A3
`INPUT A4
`INPUT A5
`INPUT A6
`INPUT A7
`INPUT A8
`INPUT A9
`INPUT A10
`INPUT A11
`INPUT A12
`GND
`
`FN PACKAGE
`(TOP VIEW)
`
`I/O CLOCK
`
`YSTEM CLOCK
`CC
`
`V S
`
`INPUT A0
`INPUT A1
`INPUT A2
`INPUT A3
`
`25
`24
`23
`22
`21
`20
`19
`
`ADDRESS INPUT
`DATA OUT
`CS
`REF +
`REF –
`INPUT A18
`INPUT A17
`
`4
`
`3 2 1
`
`28 27 26
`
`13 14
`
`15 16 17 18
`
`INPUT A16
`INPUT A15
`INPUT A14
`INPUT A13
`GND
`INPUT A12
`INPUT A11
`
`5 6 7 8 9 1
`
`0
`11
`12
`
`INPUT A4
`INPUT A5
`INPUT A6
`INPUT A7
`INPUT A8
`INPUT A9
`INPUT A10
`
`D 8-Bit Resolution A/D Converter
`D Microprocessor Peripheral or Stand-Alone
`Operation
`D On-Chip 20-Channel Analog Multiplexer
`D Built-in Self-Test Mode
`D Software-Controllable Sample and Hold
`D Total Unadjusted Error . . . ±0.5 LSB Max
`D Timing and Control Signals Compatible
`With 8-Bit TLC540 and 10-Bit TLC1540 A/D
`Converter Families
`D CMOS Technology
`
`PARAMETER
`
`Channel Acquisition Time
`Conversion Time (Max)
`Sampling Rate (Max)
`Power Dissipation (Max)
`
`TL545
`1.5 m s
`9 m s
`76 x 103
`15 mW
`
`TL546
`2.7 m s
`17 m s
`40 x 103
`15 mW
`
`
`
`description
`
`The TLC545 and TLC546 are CMOS
`analog-to-digital converters built around an 8-bit
`switched capacitor successive-approximation
`analog-to-digital converter. They are designed for
`serial interface to a microprocessor or peripheral
`via a 3-state output with up to four control inputs
`including independent SYSTEM CLOCK, I/O
`CLOCK, chip select (CS), and ADDRESS INPUT.
`A 4-MHz system clock for the TLC545 and a
`2.1-MHz system clock for the TLC546 with a
`design that includes simultaneous read/write
`operation allowing high-speed data transfers and
`sample rates of up to 76,923 samples per second
`for the TLC545, and 40,000 samples per second
`for the TLC546.
`
`In addition to the high-speed converter and
`versatile control logic, there is an on-chip
`20-channel analog multiplexer that can be used to
`sample any one of 19 inputs or an internal self-test
`voltage, and a sample-and-hold that can operate
`automatically or under microprocessor control.
`
`The converters incorporated in the TLC545 and TLC546 feature differential high-impedance reference inputs
`that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A totally
`switched capacitor design allows low-error (±0.5 LSB) conversion in 9 m s for the TLC545, and 17 m s for the
`TLC546, over the full operating temperature range.
`
`Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
`Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
`
`PRODUCTION DATA information is current as of publication date.
`Products conform to specifications per the terms of Texas Instruments
`standard warranty. Production processing does not necessarily include
`testing of all parameters.
`
`Copyright  1996, Texas Instruments Incorporated
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`1
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 1
`
`

`
`TLC545C, TLC545I, TLC546C, TLC546I
`8-BIT ANALOG-TO-DIGITAL CONVERTERS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
`
`
`
`TA
`
`0°C to 70°C
`
`– 40°C to 85°C
`
`AVAILABLE OPTIONS
`PACKAGE
`CHIP CARRIER
`PLASTIC DIP
`(FN)
`(N)
`
`TLC545CFN
`—
`
`TLC545IFN
`TLC546IFN
`
`TLC545CN
`—
`
`TLC545IN
`TLC546IN
`
`description (continued)
`The TLC545C and the TLC546C are characterized for operation from 0°C to 70°C. The TLC545I and the
`TLC546I are characterized for operation from –40°C to 85°C.
`
`functional block diagram
`
`REF +
`22
`
`REF –
`21
`
`8-Bit
`Analog-to-Digital
`Converter
`(Switched-capacitors)
`
`8
`
`Output
`Data
`Register
`
`8
`
`8-to-1 Data
`Selector and
`Driver
`
`24
`
`DATA
`OUT
`
`20-Channel
`Analog
`Multiplexer
`
`Sample
`and
`Hold
`
`5
`
`Input
`Address
`Register
`
`Self-Test
`Reference
`
`5
`
`Input
`Multiplexer
`
`2
`
`Control Logic
`and I/O
`Counters
`
`4
`
`1234567891
`
`0
`11
`12
`13
`15
`16
`17
`18
`19
`20
`
`A0
`A1
`A2
`A3
`A4
`A5
`A6
`A7
`A8
`A9
`A10
`A11
`A12
`A13
`A14
`A15
`A16
`A17
`A18
`
`INPUTS
`
`ADDRESS
`INPUT
`
`I/O
`CLOCK
`
`CS
`SYSTEM
`CLOCK
`
`25
`
`26
`
`23
`
`27
`
`2
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 2
`
`

`
`
`
`typical equivalent inputs
`
`TLC545C, TLC545I, TLC546C, TLC546I
`8-BIT ANALOG-TO-DIGITAL CONVERTERS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
`
`INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
`
`INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
`
`1 kW TYP
`
`INPUT
`A0 – A18
`
`Ci = 60 pF TYP
`(equivalent input
`capacitance)
`
`INPUT
`A0 – A18
`
`5 MW TYP
`
`operating sequence
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`1
`
`2
`
`43
`
`5
`
`6
`
`7
`
`8
`
`Access
`Cycle B
`(see Note C)
`
`Don’t
`
`Care
`
`tconv
`Sample Cycle B
`
`See Note A
`
`twH(CS)
`
`Access
`Cycle C
`
`Sample
`Cycle C
`
`MSB
`B4
`
`B3
`
`B2
`
`B1
`
`LSB
`B0
`
`Don’t Care
`
`MSB
`C4
`
`LSB
`C3 C2 C1 C0
`
`Don’t Care
`
`A7
`
`A6 A5 A4 A3 A2 A1 A0
`
`B7
`
`B6
`
`B5
`
`B4
`
`B3
`
`B2
`
`B1
`
`B0
`
`Hi-Z State
`
`A7
`
`Hi-Z
`State
`
`B7
`
`I / O
`CLOCK
`
`CS
`
`ADDRESS
`INPUT
`
`DATA
`OUT
`
`LSB
`Previous Conversion Data A
`
`LSB
`Conversion Data B
`
`MSB
`(see Note B)
`MSB
`MSB
`MSB
`NOTES: A. The conversion cycle, which requires 36 system clock periods, is initiated with the eighth I/O CLOCK↓ after CS↓ for the channel
`whose address exists in memory at that time.
`B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven bits
`(A6–A0) will be clocked out on the first seven I/O CLOCK falling edges.
`C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three system clock cycles (or less) after a chip
`select transition before responding to control input signals. Therefore, no attempt should be made to clock-in address data until the
`minimum chip-select setup time has elapsed.
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`3
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 3
`
`

`
`TLC545C, TLC545I, TLC546C, TLC546I
`8-BIT ANALOG-TO-DIGITAL CONVERTERS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
`absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
`
`
`
`Supply voltage, VCC (see Note 1)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
` 6.5 V
`Input voltage range, VI (any input)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`–0.3 V to VCC +0.3 V
`Output voltage range, VO
`–0.3 V to VCC +0.3 V
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`±10 mA
`Peak input current range (any input)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`±30 mA
`Peak total input current (all inputs)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`0°C to 70°C
`Operating free-air temperature range, TA: TLC545C, TLC546C
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`–40°C to 85°C
`TLC545I, TLC546I
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`–65°C to 150°C
`Storage temperature range, Tstg
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`260°C
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Case temperature for 10 seconds, TC: FN package
`260°C
`Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package
`. . . . . . . . . . . . . . . . . . . . .
`† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
`functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
`implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
`NOTE 1: All voltage values are with respect to network ground terminal.
`
`4
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 4
`
`

`
`
`
`TLC545C, TLC545I, TLC546C, TLC546I
`8-BIT ANALOG-TO-DIGITAL CONVERTERS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
`
`recommended operating conditions
`
`Supply voltage, VCC
`Positive reference voltage, Vref+ (see Note 2)
`Negative reference voltage, Vref– (see Note 3)
`Differential reference voltage, Vref+ – Vref– (see Note 3)
`Analog input voltage (see Note 3)
`High-level control input voltage, VIH
`Low-level control input voltage, VIL
`Setup time, address bits at data input before I/O CLOCK↑,
`tsu(A)
`Address hold time, th
`
`Setup time, CS low before clocking in first address bit, tsu(CS)
`(see Note 2)
`
`TLC545
`NOM
`MAX
`5
`5.5
`VCC VCC +0.1
`0
`VCC
`VCC VCC +0.2
`VCC
`
`0.8
`
`MIN
`4.75
`
`0
`
`– 0.1
`
`0
`
`0
`
`2
`
`200
`
`0
`
`3
`
`MIN
`4.75
`
`0
`
`– 0.1
`
`0
`
`0
`
`2
`
`400
`
`0
`
`3
`
`I/O CLOCK frequency, fclock(I/O)
`SYSTEM CLOCK frequency, fclock(SYS)
`
`0
`fclock(I/O)
`
`2.048
`0
`4 fclock(I/O)
`
`Pulse duration, CS high during conversion, twH(CS)
`
`Pulse duration, SYSTEM CLOCK high, twH(SYS)
`Pulse duration, SYSTEM CLOCK low, twL(SYS)
`Pulse duration, I/O CLOCK high, twH(I/O)
`Pulse duration, I/O CLOCK low, twL(I/O)
`fclock(SYS) ≤ 1048 kHz
`fclock(SYS) > 1048 kHz
`fclock(I/O) ≤ 525 kHz
`fclock(I/O) > 525 kHz
`TLC545C, TLC546C
`
`Clock transition time
`(see Note 4)
`
`
`
`SystemSystem
`
`
`
`I/OI/O
`
`TLC546
`NOM
`MAX
`5
`5.5
`VCC VCC +0.1
`0
`VCC
`VCC VCC +0.2
`VCC
`
`0.8
`
`
`
`UNITUNIT
`
`V
`
`V
`
`V
`
`V
`
`V
`
`V
`
`V
`
`ns
`
`ns
`
`System
`clock
`cycles
`
`1.1
`
`2.1
`
`MHz
`
`MHz
`
`System
`clock
`cycles
`
`ns
`
`ns
`
`ns
`
`ns
`
`
`
`nsns
`
`
`
`nsns
`
`30
`20
`100
`40
`70
`
`36
`
`110
`
`100
`
`200
`
`200
`
`0
`
`36
`
`210
`
`190
`
`404
`
`404
`
`0
`
`30
`20
`100
`40
`70
`
`
`
`Operating free air temperature TAOperating free-air temperature, TA
`
`°C
`85
`– 40
`85
`– 40
`TLC545I, TLC546I
`NOTES: 2. To minimize errors caused by noise at CS, the internal circuitry waits for three system clock cycles (or less) after a chip select falling
`edge or rising edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address
`data until the minimum chip select setup time has elapsed.
`3. Analog input voltages greater than that applied to REF+ convert as all “1”s (11111111), while input voltages less than that applied
`to REF– convert as all “0”s (00000000). As the differential reference voltage decreases below 4.75 V, the total unadjusted error tends
`to increase.
`4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
`of normal room temperature, the devices function with input clock transition time as slow as 2 m s for remote data acquisition
`applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`5
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 5
`
`

`
`TLC545C, TLC545I, TLC546C, TLC546I
`8-BIT ANALOG-TO-DIGITAL CONVERTERS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
`
`
`
`electrical characteristics over recommended operating temperature range,
`VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 2.048 MHz for TLC545 or fclock(I/O) = 1.1 MHz for TLC546
`(unless otherwise noted)
`
`VOH
`VOL
`
`
`
`IOZIOZ
`
`IIH
`IIL
`ICC
`
`PARAMETER
`High-level output voltage (DATA OUT)
`Low-level output voltage
`
`
`
`Off state (high impedance state) ouput currentOff-state (high-impedance state) ouput current
`
`High-level input current
`Low-level input current
`Operating supply current
`
`Selected channel leakage current
`Selected channel leakage current
`
`ICC + Iref
`
`Supply and reference current
`
`TEST CONDITIONS
`IOH = – 360 m A
`VCC = 4.75 V,
`VCC = 4.75 V,
`IOL = 3.2 mA
`VO = VCC,
`CS at VCC
`VO = 0,
`CS at VCC
`VI = VCC
`VI = 0
`CS at 0 V
`Selected channel at VCC,
`Unselected channel at 0 V
`Selected channel at 0 V,
`Unselected channel at VCC
`CS at 0 V
`Vref+ = VCC,
`
`Input capacitanceInput capacitance
`
`
`
`
`CiCi
`† All typical values are at TA = 25°C.
`
`Analog inputs
`Control inputs
`
`TYP†
`
`MAX
`
`MIN
`2.4
`
`0.4
`10
`– 10
`2.5
`– 2.5
`2.5
`
`1
`
`– 1
`
`3
`55
`15
`
`0.005
`– 0.005
`1.2
`
`0.4
`
`– 0.4
`
`1.3
`7
`5
`
`UNIT
`V
`V
`
`
`
`m Am A
`
`m A
`m A
`mA
`
`m A
`m A
`
`mA
`
`
`
`pFpF
`
`6
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 6
`
`

`
`
`
`TLC545C, TLC545I, TLC546C, TLC546I
`8-BIT ANALOG-TO-DIGITAL CONVERTERS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
`
`operating characteristics over recommended operating free-air temperature range,
`VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 2.048 MHz for TLC545 or 1.1 MHz for TLC546,
`fclock(SYS) = 4 MHz for TLC545 or 2.1 MHz for TLC546
`
`PARAMETER
`PARAMETER
`
`TEST CONDITIONS
`TEST CONDITIONS
`
`TLC545
`MIN TYP
`
`EL
`EZS
`EFS
`
`tconv
`
`Linearity error
`Zero-scale error
`Full-scale error
`Total unadjusted error
`
`Self-test output code
`
`Conversion time
`Total access and
`conversion time
`
`See Note 5
`See Note 6
`See Note 6
`See Note 7
`INPUT A19 address = 10011
`(see Note 8)
`See Operating Sequence
`
`See Operating Sequence
`
`tacq
`
`Channel acquisition time
`(sample cycle)
`
`See Operating Sequence
`
`01111101
`(125)
`
`MAX
`± 0.5
`± 0.5
`± 0.5
`± 0.5
`10000011
`(131)
`9
`
`13
`
`3
`
`TLC546
`MIN TYP
`
`01111101
`(125)
`
`MAX
`± 0.5
`± 0.5
`± 0.5
`± 0.5
`10000011
`(131)
`17
`
`25
`
`3
`
`UNIT
`UNIT
`
`LSB
`LSB
`LSB
`LSB
`
`m s
`
`m s
`
`I/O
`clock
`cycles
`
`tv
`
`td
`
`See ParameterSee Parameter
`
`Measurement Information
`
`Time output data remains
`valid after I/O CLOCK↓
`Delay time, I/O CLOCK to
`DATA OUT valid
`150
`Output enable time
`ten
`150
`Output disable time
`tdis
`300
`Data bus rise time
`tr(bus)
`300
`Data bus fall time
`tf(bus)
`NOTES: 5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
`6. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
`between 11111111 and the converted output for full-scale input voltage.
`7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
`8. Both the input address and the output codes are expressed in positive logic. The INPUT A19 analog input signal is internally
`generated and is used for test purposes.
`
`10
`
`10
`
`300
`
`ns
`
`ns
`
`ns
`ns
`ns
`ns
`
`400
`
`150
`150
`300
`300
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`7
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 7
`
`

`
`TLC545C, TLC545I, TLC546C, TLC546I
`8-BIT ANALOG-TO-DIGITAL CONVERTERS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
`
`PARAMETER MEASUREMENT INFORMATION
`
`1.4 V
`
`3 kW
`
`Output
`Under Test
`CL
`(see Note A)
`
`Test
`Point
`
`Output
`Under Test
`CL
`(see Note A)
`
`Test
`Point
`
`3 kW
`
`Output
`Under Test
`CL
`(see Note A)
`
`
`
`VCC
`
`3 kW
`
`Test
`Point
`
`LOAD CIRCUIT FOR
`td, tr, AND tf
`
`See Note B
`
`LOAD CIRCUIT FOR
`tPZH AND tPHZ
`
`See Note B
`
`LOAD CIRCUIT FOR
`tPZL AND tPLZ
`
`CS
`
`SYSTEM
`CLOCK
`
`50%
`
`Output Waveform 1
`(see Note C)
`
`See Note B
`
`Output Waveform 2
`(see Note C)
`
`tPZL
`
`tPZH
`
`tPLZ
`
`10%
`
`tPHZ
`
`90%
`
`50%
`
`50%
`
`VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES
`
`VCC
`
`0 V
`
`VCC
`
`0 V
`
`VOH
`
`0 V
`
`I/O CLOCK
`
`DATA OUT
`
`0.8 V
`
`td
`
`Output
`
`tr
`
`2.4 V
`
`0.4 V
`
`tf
`
`VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES
`
`2.4 V
`0.8 V
`
`VOLTAGE WAVEFORMS FOR DELAY TIME
` CL = 50 pF for TLC545 and 100 pF for TLC546
`NOTES: A.
`ten = tPZH or tPZL, tdis = tPHZ or tPLZ
`B.
`C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
`Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
`
`8
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 8
`
`

`
`
`
`TLC545C, TLC545I, TLC546C, TLC546I
`8-BIT ANALOG-TO-DIGITAL CONVERTERS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
`
`PARAMETER MEASUREMENT INFORMATION
`
`simplified analog input analysis
`
`Using the equivalent circuit in Figure 1, the time required to charge the analog input capacitance from 0 to VS
`within 1/2 LSB can be derived as follows:
`
`(1)
`
`(2)
`
`(3)
`
`(4)
`
`(5)
`
`The capacitance charging voltage is given by
`(
`)
`VC = VS 1–e –t c/RtCi
`
`where
`
`Rt = Rs + ri
`
`The final voltage to 1/2 LSB is given by
`VC (1/2 LSB) = VS – (VS/512)
`
`Equating equation 1 to equation 2 and solving for time tc gives
`VS –(VS/512) = VS 1–e(
`)
`–t c/RtCi
`
`and
`
`tc (1/2 LSB) = Rt × Ci × ln(512)
`Therefore, with the values given the time for the analog input signal to settle is
`) × 60 pF × ln(512)
`tc (1/2 LSB) = (Rs + 1 kW
`This time must be less than the converter sample time shown in the timing diagrams.
`
`Driving Source†
`
`TLC545/ 6
`
`VS
`
`Rs
`
`VI
`
`ri
`
`1 kW
`
` MAX
`
`VC
`
`Ci
`50 pF MAX
`
`VI = Input Voltage at INPUT A0 – A18
`VS = External Driving Source Voltage
`Rs = Source Resistance
`ri = Input Resistance
`Ci = Input Capacitance
`
`† Driving source requirements:
`• Noise and distortion for the source must be equivalent to the
`resolution of the converter.
`• Rs must be real at the input frequency.
`
`Figure 1. Equivalent Input Circuit Including the Driving Source
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`9
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 9
`
`

`
`TLC545C, TLC545I, TLC546C, TLC546I
`8-BIT ANALOG-TO-DIGITAL CONVERTERS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
`
`
`
`PRINCIPLES OF OPERATION
`
`The TLC545 and TLC546 are both complete data acquisition systems on single chips. Each includes such functions
`as system clock, sample and hold, 8-bit A/D converter, data and control registers, and control logic. For flexibility and
`access speed, there are four control inputs; CS, ADDRESS INPUT, I/O CLOCK, and SYSTEM CLOCK. These control
`inputs and a TTL-compatible 3-state output facilitate serial communications with a microprocessor or microcomputer.
`The TLC545 and TLC546 can complete conversions in a maximum of 9 and 17 m s respectively, while complete
`input-conversion-output cycles can be repeated at a maximum of 13 and 25 m s, respectively.
`The system clock and I/O clock are normally used independently and do not require any special speed or phase
`relationships between them. This independence simplifies the hardware and software control tasks for the device.
`Once a clock signal within the specification range is applied to the SYSTEM CLOCK input, the control hardware and
`software need only be concerned with addressing the desired analog channel, reading the previous conversion result,
`and starting the conversion by using the I/O CLOCK. SYSTEM CLOCK will drive the “conversion crunching” circuitry
`so that the control hardware and software need not be concerned with this task.
`
`When CS is high, DATA OUT is in a high-impedance condition, and ADDRESS INPUT and I/O CLOCK are disabled.
`This feature allows each of these terminals, with the exception of CS, to share a control logic point with their
`counterpart terminals on additional A/D devices when additional TLC545/TLC546 devices are used. Thus, the above
`feature serves to minimize the required control logic terminals when using multiple A/D devices.
`
`The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
`the conversion result. A normal control sequence is:
`
`1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges
`and then a falling edge of the SYSTEM CLOCK after a CS transition before the transition is recognized. The
`MSB of the previous conversion result automatically appears on DATA OUT.
`
`2.
`
` A new positive-logic multiplexer address is shifted in on the first five rising edges of I/O CLOCK. The MSB of
`the address is shifted in first. The negative edges of these five I/O clocks shift out the second, third, fourth,
`fifth, and sixth most significant bits of the previous conversion result. The on-chip sample and hold begins
`sampling the newly addressed analog input after the fifth falling edge. The sampling operation basically
`involves the charging of internal capacitors to the level of the analog input voltage.
`
`3. Two clock cycles are then applied to I/O CLOCK and the seventh and eighth conversion bits are shifted out on
`the negative edges of these clock cycles.
`
`4. The final eighth clock cycle is applied to I/O CLOCK. The falling edge of this clock cycle completes the analog
`sampling process and initiates the hold function. Conversion is then performed during the next 36 system
`clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low for at least 36
`system clock cycles to allow for the conversion function.
`
`CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple
`conversion, special care must be exercised to prevent noise glitches on the I/O CLOCK line. If glitches occur on the
`I/O CLOCK line, the I/O sequence between the microprocessor/controller and the device loses synchronization. Also,
`if CS is taken high, it must remain high until the end of conversion. Otherwise, a valid falling edge of CS causes a
`reset condition, which aborts the conversion in progress.
`
`A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
`4 before the 36 system clock cycles occur. Such action yields the conversion result of the previous conversion and
`not the ongoing conversion.
`
`10
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 10
`
`

`
`
`
`TLC545C, TLC545I, TLC546C, TLC546I
`8-BIT ANALOG-TO-DIGITAL CONVERTERS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
`
`PRINCIPLES OF OPERATION
`
`It is possible to connect SYSTEM CLOCK and I/O CLOCK together in special situations in which controlling circuitry
`points must be minimized. In this case, the following special points must be considered in addition to the requirements
`of the normal control sequence previously described.
`
`1. The first two clocks are required for this device to recognize CS is at a valid low level when the common clock
`signal is used as an I/O CLOCK. When CS is recognized by the device to be at a high level, the common clock
`signal is used for the conversion clock also.
`
`2. A low CS must be recognized before the I/O CLOCK can shift in an analog channel address. The device
`recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a
`negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address.
`Also, upon shifting in the address, CS must be raised after the eighth valid (10 total) I/O CLOCK. Otherwise,
`additional common clock cycles are recognized as I/O CLOCKS and shift in an erroneous address.
`
`For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.
`This device accommodates these applications. Although the on-chip sample and hold begins sampling upon the
`negative edge of the fourth valid I/O clock cycle, the hold function is not initiated until the negative edge of the eighth
`valid I/O clock cycle. Thus, the control circuitry can leave the I/O clock signal in its high state during the eighth valid
`I/O clock cycle, until the moment at which the analog signal must be converted. The TLC545/546 continues sampling
`the analog input until the eighth valid falling edge of the I/O clock. The control circuitry or software must then
`immediately lower the I/O clock signal to initiate the hold function at the desired point in time and to start conversion.
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`11
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 11
`
`

`
`TLC545C, TLC545I, TLC546C, TLC546I
`8-BIT ANALOG-TO-DIGITAL CONVERTERS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
`
`
`
`12
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 12
`
`

`
`Addendum-Page 1
`
`(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
`
`
`
`(4) Only one of markings shown within the brackets will appear on the physical device.
`
`
`
`in homogeneous material)
`Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
`the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
`Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
`lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
`Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
`TBD: The Pb-Free/Green conversion plan has not been defined.
`information and additional product content details.
`(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
`
`
`
`OBSOLETE: TI has discontinued the production of the device.
`PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
`NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
`LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
`ACTIVE: Product device recommended for new designs.
`(1) The marketing status values are defined as follows:
`
`
`
`TLC545IN
`
`Call TI
`Call TI
`Call TI
`Call TI
`Call TI
`Call TI
`
`Call TI
`Call TI
`Call TI
`Call TI
`Call TI
`Call TI
`
`TBD
`TBD
`TBD
`TBD
`TBD
`TBD
`
`TLC545IFN
`
`Level-1-260C-UNLIM
`
`CU NIPDAU
`
`& no Sb/Br)
`Green (RoHS
`
`TLC545CN
`
`TLC545CFN
`(4)
`
`Call TI
`Call TI
`
`Call TI
`Call TI
`
`TBD
`TBD
`
`Level-1-260C-UNLIM
`
`CU NIPDAU
`
`(3)
`
`& no Sb/Br)
`Green (RoHS
`
`(2)
`
`37
`
`37
`
`Samples
`
`Top-Side Markings
`
`Op Temp (°C)
`
`Lead/Ball FinishMSL Peak Temp
`
`Eco Plan
`
`PinsPackage Qty
`
`21-Mar-2013
`
`PACKAGE OPTION ADDENDUM
`
`28
`28
`28
`28
`28
`28
`
`28
`28
`28
`
`28
`
`N
`
`FN
`FN
`
`N
`
`N
`
`FN
`
`FN
`
`N
`
`N
`
`FN
`
`PDIP
`PLCC
`PLCC
`PDIP
`PDIP
`PLCC
`
`PLCC
`PDIP
`PDIP
`
`PLCC
`
`Drawing
`Package TypePackage
`
`
`
`OBSOLETE
`OBSOLETE
`OBSOLETE
`OBSOLETE
`OBSOLETE
`OBSOLETE
`
`NRND
`
`OBSOLETE
`OBSOLETE
`
`NRND
`
`(1)
`
`Status
`
`TLC546IN
`
`TLC546IFNR
`TLC546IFN
`TLC545ING4
`
`TLC545IN
`
`TLC545IFNR
`
`TLC545IFN
`
`TLC545CNG4
`
`TLC545CN
`
`TLC545CFN
`
`Orderable Device
`
`PACKAGING INFORMATION
`
`www.ti.com
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 13
`
`

`
`Addendum-Page 2
`
`In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
`
`
`
`TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
`continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
`provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
`Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
`
`
`
`21-Mar-2013
`
`www.ti.com
`
`PACKAGE OPTION ADDENDUM
`
`Samsung Electronics Co., Ltd. et al.
`Ex. 1007, p. 14
`
`

`
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`
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