`
`
`‘1? TEXAS
`
`INSTRUM ENTS
`I
`
`:
`
`I
`
`Linear Circuits
`
`Data Acquisition and Conversion
`
`
`‘
`
`Data Book
`
`Voiume 2
`
`
`
`Linear Products
`
`Samsung Electronics Co., Ltd. et al.
`Ex 1017, p. 1
`
`

`

`
`
`Linear Products Quick Reference Guide
`Contents
`
`Data Book
`
`1
`0 Linear Circuits Vol
`Amplifiers, Comparators,
`and Special Functions
`
`0 Linear C.rcuits Vol 2
`Data Acquisition
`and Conversion
`
`0 Linear Circuits Vol 3
`Voltage Regulators and
`Supervisors
`
`0 Telecommunications
`Circuits
`
`0 Optoelectronics and
`Image Sensors
`
`Interface Circuits
`
`Operational Amplifiers
`Voltage Comparators
`Video Amplifiers
`Hall—Effect Devices
`Timers and Current Mirrors
`Magnetic-Memory Interface
`Frequency-to—Voltage Converters
`Sonar Ranging Circuits/Modules
`Sound Generators
`
`A/D and D/A Converters
`DSP Analog Interface
`Analog Switches and Multiplexers
`Switched—Capacitor Filters
`
`Supervisor Functions
`Series—Pass Voltage Regulators
`Shunt Regulators
`Voltage References
`DC-to-DC Converters
`PWM Controllers
`
`Equipment Line Interfaces
`Subscriber Line Interfaces
`Modems and Receiver/Transmitters
`Ringers, Detectors, Tone Encoders
`PCM Interface
`Transient Suppressors
`
`Optocouplers
`CCD Image Sensors and Support
`Phototransistors
`lR—Emitting Diodes
`Hybrid Displays
`
`High-Voltage (Display) Drivers
`High—Power (Peripheral/Motor) Drivers
`Line Drivers, Receivers, Transceivers
`EIA RS-232, RS-422, RS—423, RS—485
`IBM 360/370, IEEE 802.3, CCITT
`Military Memory Interface
`
`0 Speech System Manuals
`
`TSP50C4X Family
`
`Document No.
`
`SLYDOOS
`1989
`
`SLYDOO4
`1989
`
`SLYD005
`1989
`
`SCTDOO1 A
`1988/89
`
`SOYDOOZ
`1987
`
`SLYD002
`1987
`
`SLP8025
`1988
`
`
`
`.....an.........gamma—inmumm-sz—w.1"...—--
`
`-lane-mrm
`
`
`
`
`_._.._...__.__..._'_—
`
`
`
`Samsung Electronics Co., Ltd. et al.
`Ex 1017, p. 2
`
`

`

`;
`
`i
`‘
`
`i‘
`'i
`
`Linear Circuits
`Data Book
`
`1989
`
`Volume 2
`Data Acquisition and Conversion
`
`{I}
`TEXAS
`INSTRUMENTS
`
`Samsung Electronics Co., Ltd. at al.
`EX 1017, p. 3
`
`
`
`Samsung Electronics Co., Ltd. et al.
`Ex 1017, p. 3
`
`

`

`
`
`
`
`. L‘nCMOSW‘ Technology
`N DUALAIN-LINE PACKAGE
`(TOP VIEW)
`. Microprocessor Peripheral or Stand-Alone
`
`TL8545M, TL0545I. TL05450. TL0546M. TL05461, “05450
`LinCMUSTM B-BIT ANALOG-TO-DIGITAL PERIPHERALS
`WITH SERIAL CONTROL AND 19 INPUTS
`D2850, DECEMBER 1985—REVISED SEPTEMBER 1988
`
`
`-
`2
`3
`ll):
`a
`
`in
`*"
`(B
`D
`
`
`'
`13:3: 2? I;
`:3. :SETEM CLOCK
`
`I/O CLOCK
`INPUT A2 I3
`
`INPUT A3 I4
`25' ADDREOSS INPUT
`
`Illjllilj‘I 2: I: Z. E—QTA UT
`
`22. REF+
`INPUT A6 I7
`
`INPUT A7
`8
`21
`REF—
`
`INPUT A8 .9
`INPUT A18
`19. INPUT A17
`INPUT A9 I10
`INPUT A10 III
`18. INPUT A16
`INPUT A11 |I2
`I7| INPUT A15
`INPUT A12 |I3
`16
`INPUT A14
`GND I14
`15' INPUT A13
`
`
`FN CHIP CARRIER PACKAGE
`(TOP VIEW)
`>5
`8
`d :4
`0
`m N r— o
`E g
`4 < <1
`‘1
`S S S '5 U 5 u
`E E E E g a g
`— — .— — — .-
`
`
`
`
`4
`3
`2
`1
`25' ADDRESS INPUT
`INPUT A4 I5
`INPUT A5 I6
`”I D_ATA OUT
`INPUT A6 '7
`93' CS
`
`22' RE“
`INPUT A7 '8
`
`21I REF T
`INPUT A8 I9
`INPUT A9 I”)
`ZOI INPUT A18
`WI INPUT A17
`INPUT A10
`
`
`
`
`
`
`
`_ _ _
`r— m g m e LO (.0
`2 2 (29 2 Z 2 2
`15 15
`I5 15 5 I5
`% %
`% % ‘2 %
`’ —
`— "’ _ —
`
`
`
`8-3“ Resolution A/D Converter
`
`O
`
`Operam“
`. on-Chip 20-Channel Analog Multiplexer
`. Built—In Self—Test Mode
`. Software—Controllable Sample and Hold
`. Total Unadjusted Error .
`.
`. $0.5 LSB Max
`0 Timing and Control Signals Compatible with
`8—Bit TL0540 and 10—Bit TLC154O AID
`Converter Families
`
`'
`
`.
`'
`..
`
`-
`
`_
`,
`
`.
`
`
`
`
`channel Acquisition Time
`
`
`convemlo” Time
`
`.
`Sampling Rate
`
`Power Dissipation
`.
`descriptlon
`.
`The TLC545 and TLC546 are LInCMOSw ND
`peripherals built around an 8-bit
`switched—
`capacitor
`successive—approximation A/D
`converter. They are designed for serial interface
`to a microprocessor or peripheral via a 3-state
`output with up to four control inputs [including
`independent System Clock,
`I/O Clock, Chip
`Select (E), and Address Input]. A 4-MH2
`system clock for the TLC545 and a 2.1-MH2
`system clock for the TLC546 with a design that
`includes
`simultaneous
`read/write operation
`allowing high-speed data transfers and sample
`rates of up to 76,923 samples per second for the
`TLC545, and 40,000 samples per second for the
`TLC546. In addition tothe high—speed converter
`and versatile control logic, there IS an on—Chip
`20-channel analog multIpIexer that can he used
`to sample any one of 19 inputs or an Internal
`“self—test” voltage, and a sample-and—hold that
`can
`operate
`automatically
`or
`under
`microprocessor control.
`
`
`
`The converters incorporated in the TLC545 and
`TLC546 feature differential high-impedance
`reference inputs that
`facilitate ratibmetric
`conversion, scaling, and analog circuitry isolation
`from logic and supply noises. A totally switched-
`capacitor design allows low—error (10.5 LSB)
`
`ntr0| -
`
`addi‘llgn
`
`used as
`'k S'Qnal
`antly th
`3n
`figf52i
`‘Ilftlng in
`d by the
`ik Signal
`309nize
`d
`lfIC poi
`d be ‘m
`Q'ns
`mm the
`Signal
`In
`mus: be
`I edge of
`ahd h l
`0d
`
`factory.
`
`.
`
`——‘
`
`‘
`
`_
`Samsung EIeCtronICS 00-, Ltd- at al-
`EX 1017, p. 4
`
`LinCMOS is a trademark of Texas Instruments Incorporated
`
`PRODUCTION DATA documents contain information
`_
`Copyright © 1985, Texas Instruments Incorporated
`current as of publicatinn date. Products conform to
`I
`
`:I::I‘.:::‘:::::.::I 13:13.5...“ Bearers":
`“Ecessarily inclu é testing of :III paramgters.
`n
`
`TEXAS *3
`INSTRUMENTS
`POST OFFICE BOX 555012 ' DALLAS, TEXAS 75265
`
`2-173
`
`
`
`Samsung Electronics Co., Ltd. et al.
`Ex 1017, p. 4
`
`

`

`
`
`TIES/IBM, TLCE45I, “£5450, TL6546M, TL0545I, TLCE4EC
`LiIIEMO'SoTM 8-,BIT ANALOG-TODIGITAI. PERIPHERALS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`WT,
`conversion in 9 [LS for the TLC545, and 17 us for the TLC546, over the full operating temperature range “’
`Detailed information on interfacing to most popular microprocessors is readily available from the factory
`
`The TLC545M and the TLC546M are characterized for operation from — 55°C to 125°C The TLC5453
`
`and the TLC546l are characterized for operation from —40°C to 85 °C. The TLC545C and the TLCS46C
`I
`
`are characterized for operation from 0°C to70°C.
`
`functional block diagram
`
`REF+
`
`REF—
`
`operat
`
`lIC
`CLOI
`
`ADDRE
`INPI
`
`DA'
`OI
`
`NOTES:
`
`absolt
`
`Ir
`
`O'D'PO
`
`NOTE 1
`
`
`
`DATA
`OUTPUT
`
`
`
`
`
`8-BIT
`
`ANALOG-TO-DIGITAL
`SAMPLE
`
`
`CONVE FITER
`AND
`
`
`
`HOLD
`(SWITCHEDcAPACITORSI
`
`
`20-CHANNEL
`
`
`ANALOG
`
`MULTIPLEXER
`OUTPUT
`810-1 DATA
`
`
`
`
`SELECTOR AND
`DATA
`
`INPUT
`REGISTER
`DRIVER
`
`
`
`ADDRESS
`
`REGISTER
`
`
`5
`
`_.
`ANALOG
`INPUTS
`
`U
`m
`a;
`(I)
`3"
`(1)
`I‘DH
`U)
`
`SELFvTEST
`REFERENCE
`
`ADDRESS
`INPUT
`
`I/O
`CLOCK
`
`'
`
`,
`
`INPUT
`. MULTIPLEXER
`
` CONTROL LOGIC
`COUNTERS
`
`V '-
`
`AND ”0
`
`,
`
`cs ~——-———————«)—————————
`
`SYSTEM ———~—————-~4>
`CLOCK
`
`
`
`
`TEXAS {j Samsung Electronics Co., Ltd. etal.
`INSTRUMENTS
`EX 1017 p 5
`POST OFFICE BOX 655012- DALLAS, TEXAS 75265
`
`
`
`
`
`2““
`
`Samsung Electronics Co., Ltd. et al.
`Ex 1017, p. 5
`
`

`

`-
`
`TLCSQSM, TL0545I, 1165456, TL054EM, TLCS46I, TL65466
`“MEMOSTM 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`
`operatINQ sequence
`
`III2|3I4|5I6|7|B
`
`,
`
`I‘I2I3I4I5I5I7I3
`I/O
`DON'T
`CARE
`CLOCKHW;
`I
`a—ACCEse—N k—SAMPLE—u
`FAccsss—fi k—SAMPLeokwxconv—w‘
`I
`CYCLEC
`I
`-
`CYCLEC I
`(g
`I
`CYCLEB
`I
`r
`CYCLEB
`I
`[See Note A)
`I
`LH‘——_——I;
`IwH(CS) >Lff—-———___.f
`(See NoteC)
`MSB
`LSB
`MSB
`LSB
`DON'T
`
`CARE
`DON'T CARE
`ADDRESS—a Efifififl
`if @@@@@h
`INPUT
`Hl-Z
`@@@@@@@Q STATE
`6
`B7
`4—Air“~ CONVERSION DATA B _.____,
`M88
`LSB MSB
`
`DATA @@@@@@@@9
`our—“f
`"
`A7
`‘— PREVIOUS CONVERSION DATA A -+
`M58
`LSB M38
`(See Note 8)
`
`Hl-ZSTATE
`
`
`
`
`
` DataSheets(\J‘
`
`NOTES: A. The conversion cycle, which requires 36 system clock periods. is initiated with the 8th (/0 clockl after CSI for the channel
`whose address exists in memory at that time.
`8‘ The most significant bit (MSB) will automatically be placed on the DATA OUT bus afterE is brought low. The remaining
`seven bits (A6~AO) will be clocked out on the first seven I/O clock falling edges.
`C. To minimize errors caused by noise at the CS input, thelinternal circuitry waits for three system clock cycles (or less) after
`a chip select transition before responding to control input signals. Therefore, no attempt should be made to clock-in address
`data until the minimum chip-select setup time has elapsed.
`
`absolute maximum ratings over operating free—air temperature range (unless otherwise noted)
`
`Supply voltage, VCC (see Note 1) ............................................. 6.5 V
`Input voltage range (any input) ................................. -—0.3 V to VCC +0.3 V
`Output voltage range ......................................... —0.3 V to Vcc +0.3 V
`Peak input current range (any input) ......................................... i10 mA
`Peak total input current (all inputs) .......................................... $30 mA
`Operating free-air temperature range: TLC545M, TLC546M ................. ~55°C to 125°C
`TLC545I, TLC546| .................... —40°C to 85°C
`TLC545C, TLC546C ..................... 0°C to'70 °C
`Storage temperature range ......................................... —65°C to 150°C
`Case temperature for 10 seconds: FN package ................................... 260°C
`Lead temperature 1,6 mrn (1/16 inch) from case for 10 seconds: N package ............ 260°C
`. NOTE 1: All voltage values are with respect to network ground terminal.
`
`
`
`
`{if
`TEXAS
`INSTRUMENTS
`POST OFFICE BOX 655012 ' DALLAS. TEXAS 75265
`
`Samsung Electronics Co., Ltd. et al.
`Ex 1017, p. 6
`
`2175
`
`Samsung Electronics Co., Ltd. et al.
`Ex 1017, p. 6
`
`

`

`
`
`
`
`TLCB45M. TLC545L TLCS45C, “0546M, TLC545I, TL9546C
`LinCMUSTM 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`
`
`TLC546
`NOM
`
`5
`
`O
`
`X
`MA
`.5
`
`5
`
`W 0 0 O 2
`
`4 75
`
`4
`
`recommended operating conditions
`
`Supply voltage, VCC
`
`
`
`TLC545
`mm m M
`5
`
`4 75
`
`AX
`.5
`
`5
`
`Low-level control input voltage, V“_ m
`Setup time, address bits at data input before [/0 CLKT, tsuiAl
`200
`Address hold time, th
`
`2
`
`Setup time, E low before clocking in first
`address bit, tsulCS) (see Note 3)
`
`Chip select high during conversion, th(CS)
`
`3
`
`3
`
`O
`
`
`
`
`
`
`
`
`
`
`Input/Output clock frequency, fCLK l/O)
` lCLKil/O)
`System clock frequency, fCLK(SYS)
`5,3,...
`th svs
`
` ssem crock .ow, twt svs
`Input/Output clock high, thll/O)
`Input/Output clock row. twLii/O)
`
`f
`s 1048 kH
`
`
`
`
`
`swanse130N
`
`
`
`
`
`
`Clock transition time
`
`(see Note 4)
`
`VD
`
`Operating free-air temperature, TA
`
`
`
`
`
`n
`
`.1
`.1
`
`1 2
`
`2.048
`4
`
`36
`
`0
`
`fCLKll/O)
`
`404
`404
`
`3 2 4
`
`30
`—_ [13
`fax SYsi > 1048 kHz __
`fCLKiI/O) S 525 kHz
`100
`O
`40
`fCLKiI/O) > 525 kHz ——
`
`
`
`WW.W.
`
`———I0
`
`TLC545l, TLC546l
`TLC545C, TLC546C
`
`
`—4O
`85
`—40
`0
`70
`0
`
`
`
`85
`70
`
`C
`
`NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all "1”5 (1 l 1 1 l l ‘l 1), while input voltages less than that
`applied to REF— convert as all "0"s (00000000). As the differential reference voltage decreases below 4.75 V, the total
`unadjusted error tends to increase.
`3. To minimize errors caused by noise at the Chip Select input, the internal circuitry waits for three system clock cycles (or leSSl
`after a chip select falling edge or rising edge is detected before responding to control input signals. Therefore, no attempt
`should be made to clock-in address data until the minimum chip select setup time has elapsed.
`4. This is the time required for the clock input signal to fall from VIH min to VlL max or to rise from V”_ max to VIH min. in
`the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 ps for remote data
`acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor'
`
`
`
`2476
`
`
`
`TEXAS %5 .Samsung Electronics Co., Ltd. et al
`lNSTRUMENTS
`Ex 1017, p. 7
`POST OFFICE BOX 6550l2 ' DALLAS, TEXAS 76265
`
`Samsung Electronics Co., Ltd. et al.
`Ex 1017, p. 7
`
`

`

`
`
`
`
`
`TLCS45M, 11.05451, TLCE458, “(2546M TL654EI, TLCS460
`LinDMDST’" 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`
`ehactr‘cal characteristics over recommended operating temperature range,
`VCC = Vref+ = 4.75 V to 5.5 V (unless otherwise notedl, fCLKII/O) = 2.048 MHz for TLC545
`or chKll/O) = 1.1 MHz for TLC546
`PARAMETER
`
`
`TEST CONDITIONS
`MIN
`TYP’r
`MAX
`
`UNIT
`
`
`
`
`
`
`VOH
`VOL
`
`
`
`
`| .
`
`
`
`IOH = —360 pA
`VCC = 4.75 V,
`High-level output voltage (pin 24)
`'OL = 3.2 mA
`VCC : 4.75 V,
`Low—level output voltage
`ES at VCC u_
`V0 2 Vcc,
`Off—state (high-impedance state)
`
`CS at VCC
`V0 2 0,
`output current
`'02
` High»level input current v = VCC
`
`'
`1H
`L
`Low-leve' mom current
`.
`Operating supply current
`lcC
`
`
`
`.
`
`0.005
`
`.5
`
`2
`
`~2-5
`2.5
`1
`
`--0-005
`1.2
`O 4
`'
`
`-o.4
`
`—1
`
`CS at O V
`Selected channel at VCC:
`Unselected channel at O V
`Selected channel at O V,
`
`u
`
`A
`
`pA
`
`
`
`
`
`
`
`
`
`
`
`
`
`;
`
`
`
`2
`‘
`(I)
`H
`a)
`Q)
`g
`e
`8
`
`Selected channel leakage current
`
`PARAMETER
`
`
`
`
`
`Unselected channel at VCC
`Vref+ = VCC:
`ICC + Iref Supply and reference current
`E at 0 V
`.
`n 0 ca acr ance
`I
`t
`.t
`Analog inputs__ F
`
`
`
`
`c.
`p
`" —_— p
`
`IAII typical values are at TA = 25°C.
`operating characteristics over recommended operating free-air temperature range,
`VCC = Vref+ = 4.75 V to 5.5 V, fCLKII/O) = 2.048 MHz for TLC545 or 1.1 MHz for
`
`TLC546, fCLK(SYS) = 4 MHz for TLC545 or 2.1 MHz for TL0546
`.
`TLCS45
`TEST CONDITIONS
`
`TYP
`
`
`
`
`
`
`MIN
`
`MAX
`
`
`
`
`
`TLC546
`TYP
`
`MIN
`
`MAX
`
`U
`
`
`
`8 If
`9
`
`-t
`
`t
`T
`es 0” p”
`
`t CO
`
`d
`
`8
`
`Input A19 address = 10011
`(See Note 8)
`
`01111101
`i125)
`
`10000011
`i131)
`
`01111101
`1125)
`
`10000011
`(131)
`
`
`
`
`
`
`I
`r ess)
`tempt
`
`In
`win.
`e data
`
`IBSSOT-
`
`Total access and
`See Operating Sequence
`'
`13
`25
`#5
`
`
`
`conversion time
`.
`
`Channel acquisition
`.
`
`
`
`tacq
`'
`See Operating Sequence
`time (sample cycle)
`
`
`Time output data
`
`tv
`remains valid after
`l/O clock].
`
`
`
`I
`Delay time, 1/0 clockl
`to data output valid
`See Parameter
`_
`
`
`
`
`Measurement
`
`.
`
`
`Information
`
`
`
`
`
`
`
`
`d
`
`_
`_
`Output disable time
`1mg
`.
`.
`tribus) Data bus rise time
`1films) Data bus fall time
`
`
`
`
`
`NOTES:
`
`5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
`6. Zero Error is the difference between 00000000 and the converted output for zero input voltage; full—scale error is the difference
`between 11111111 and the converted output for full—scale input voltage.
`7. Total unadjusted error is the sum of linearity, zero, and full-scale errors.
`8. Both the input address and the output codes are expressed in positive logic. The A19 analog input signal is internally generated
`and is used for test purposes.
`'
`
`T
`@i}
`EXAS
`.
`INSTRUMENTS
`POST OFFICE BOX 655012 0 DALLAS. TEXAS 75265 samsung EleCtronICS CO" Ltd' et al'
`EX 1017, p. 8
`
`2,177
`
`
`
`Samsung Electronics Co., Ltd. et al.
`Ex 1017, p. 8
`
`

`

`
`
`TLCS45M, TLCE45I, “0545C, TL8545M, TLCE46I, “(25486
`LinCMIJSTM B-BIT ANALOG-Tfl-DIGITAL PERIPHERALS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`
`PARAMETER MEASUREMENT INFORMATION
`
`VCC
`
`3m
`
`prInCIpl
`Th
`IUI
`
`cl(
`
`OUTPUT
`UNDER TEST
`CL
`‘
`(SEE NOTE A)‘ I
`__.
`(SEE NOTE B)
`
`P
`E
`T ST 0”“
`3kfl
`
`OUTPUT
`UNDER TEST
`CL
`(SEE NOTE A) ‘ _I_ ‘
`(SEE NOTE 8)
`
`TEST POINT ,
`
`1.4V
`
`3 m
`
`OUTPUT
`UNDER TEST
`
`TEST
`POINT
`
`CL
`2 (SEE NOTE A) ‘
`
`I
`
`‘
`
`SITh7:O<<8
`
`LOAD CIRCUIT FOR
`td, tr, AND tf
`
`LOAD CIRCUIT FOR
`tPZH AND tsz
`
`LOAD CIRCUIT FOR
`tP2L AND tPLz
`
`I
`
`I
`
`I
`
`I
`
`| I
`
`II
`
`I I
`
`SYSTEM
`
`CLOCK
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`. OUTPUT
`WAVEFORM1
`(SEE NOTE C)
`
`OUTPUT
`WAVE FORM 2
`(SEE NOTE 6)
`
`—DI tIi’LZ I‘—
`.——§I tPZL I‘—
`Al
`|
`I
`I
`|
`|
`I
`
`
`(SEE NOTE B)
`I
`I
`I
`______ o v
`
`—pI tPZHH'_
`“H ‘PHZ “—
`|
`I
`
`50%
`
`30"— — _ _ _ VOH
`
`0 v
`
`Vcc
`
`slaaqsmeg
`
`I
`
`‘
`
`OUTPUT
`
`DATA
`
`OUTPUT
`
`VOLTAGE WAVE FORM FOR DELAY TIME
`
`
`
`VOLTAGE WAVE FORM FOR
`RISE AND FALL TIMES
`
`mnnnl
`
`NOTES: A. CL = 50 pF for TLC545 and 100 pF for TLC546
`8-
`ten = tPZH 0r tPZLr tdis = tPHz 0r tPLZ
`C. Waveform 1 is for an Output with internal conditions such that the Output is low except when disabled by the Output control-
`Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the Output control‘
`
`
`,
`b Samsung Electronics CO., Ltd. et al.
`TEXAS
`Ex 1017, p. 9‘
`INSTRUMENTS
`POST OFFICE BOX 655012' DALLAS, TEXAS 75265
`
`2-178
`
`Samsung Electronics Co., Ltd. et al.
`Ex 1017, p. 9
`
`

`

`
`
`U)
`4.:
`a:
`d)
`.C
`U)
`CU+1
`CG
`0
`
`
`
`_ 2.4V
`— 0.4V
`
`-'
`
`TL6545M, TL8545l, “85456, TLB546M, TLCS46l, “£5450
`LinCMlJSTM 8-BlT ANALOG-TU-DIGITAL PERIPHERALS
`WITH SERIAL CONTROL AND 19 INPUTS
`
`
`pl,mciples of operation
`The TLC545 and TLC‘546 are both complete data acquisition systems on single chips. Each includes such
`functions as system clock, sample-and-hold, 8—bit A/D converter, data and control registers, and control
`logic. For flexibility and access speed, there are four control inputs; Chip Select (El, Address lnput, |/O
`clock, and System clock. These control
`inputs and a TTL—compatible 3—state output facilitate serial
`communications with a microprocessor or microcomputer. The TLC545 and TLC546 can complete
`conversions in a maximum of 9 and 17 [.15 respectively, while complete input-conversion-output cycles
`can be repeated at a maximum of 13 and 25 [1.8, respectively.
`
`The System and l/O clocks are normally used independently and do not require any special speed or phase
`relationships between them. This independence simplifies the hardware and software control tasks for
`the device. Once a clock signal within the specification range is applied to the System clock input, the
`control hardware and software need only be concerned with addressing the desired analog channel, reading
`the previous conversion result, and starting the conversion by using the HO clock. The System clock will
`drive the “conversion crunching” circuitry so that the control hardware and software need not be concerned
`with this task.
`
`When 53‘ is high, the Data Output pin is in a high—impedance condition, and the Address input and I/O
`Clock. pins are disabled. This feature allows each of these pins, with the exception of the (i, to share
`a control logic point with their counterpart pins on additional A/D devices when additional TLC545/TLC546
`devices are used. Thus, the above feature serves to minimize the required control logic pins when using
`multiple A/D devices.
`
`The control sequence has been designed to minimize the time and effort required to initiate conversion
`and obtain the conversion result. A normal control sequence is:
`
`‘1. CS is brought low. To minimize errors caused by noise at the E input, the internal circuitry waits
`for two rising edges and then a falling edge of the System clock after a C—S— transition before the
`transition is recognized. The MSB of the previous conversion result will automatically appear on
`the Data Out pin.
`2. A new positive-logic multiplexer address is shifted in on the first five rising edges of the [/0 clock.
`The MSB of the address is shifted in first. The negative edges of these five l/O clocks shift out
`the 2nd, 3rd, 4th, 5th, and 6th most significant bits of the previous conversion result. The on-
`chip sample‘and hold begins sampling the newly addressed analog input after the 5th falling edge.
`The sampling operation basically involves the charging of internal capacitors to the level of the
`analog input voltage.
`3. Two clock cycles are then applied to the I/O pin and the 7th and 8th conversion bits are shifted
`out on the negative edges of these clock cycles.
`4. The final 8th clock cycle is applied to the I/O clock pin. The falling edge of this clock cycle completes
`the analog sampling process and initiates the hold function. Conversion is then performed during
`the next 36 system clock cycles. After this final l/O clock cycle, RE must go high or the l/O clock
`must remain low for at least 36 system clock cycles to allow for the conversion function.
`
`C_S can be kept low during periods of multiple conversion. When keeping 65 low during periods of multiple
`conversion, special care must be exercised to prevent noise glitches on the [/0 Clock line. If glitches occur
`on the HO Clock line, the l/O sequence between the microprocessor/controller and the device will lose
`synchronization. Also,
`if E is taken high,
`it must remain high until the end of conversion. Otherwise,
`a valid falling edge of 65 will cause a reset condition, which will abort the conversion in progress.
`
`A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps
`1 through 4 before the 36 system clock cycles occur. Such action will yield the conversion result of the
`previous conversion and not the ongoing conversion.
`
`control,
`control.
`
`Samsung Electronics Co., Ltd. et al.
`Ex 1017, p. 10
`“um—“m
`
`lNSTRUMENTs
`POST OFFlCE BOX 655012 ' DALLAS, TEXAS 75265
`
`
`TEXAS ‘53
`
`2-179
`
`Samsung Electronics Co., Ltd. et al.
`Ex 1017, p. 10
`
`

`

`
`
`TL6545M, “8545i, “05456, “6546“”, TLC546I, TLC54GC
`LinflMOSTM 8-BlT ANALOG-TU-DIGITAL PERIPHERALS
`WlTH SERIAL CONTROL AND 19 INPUTS
`
`
`principles of operation (continued)
`
`It is possible to connect the system and HG clocks together in special situations in which controlling circuitry
`points must be minimized. In this case, the following special points must be considered in addition to the
`requirements of the normal control sequence previously described.
`
`1. When 6—8. is recognized by the device to be at a low level, the common clock signal is used
`as an l/O clock. When the ES— is recognized by the device to be at a high level, the common
`clock signal is used to drive the "conversion crunching” circuitry.
`2. The device will recognize a E transition only when the (3—5 input changes and subsequently
`the system clock pin receives two positive edges and then a negative edge. For this reason,
`after a E negative edge, the first two clock cycles will not shift in the address because a
`low E73 must be recognized before the HO clock can shift in an analog channel address. Also,
`upon shifting in the address, E must be raised after the 6th l/O clock, which has been
`recognized by the device, so that a E low level will be recognized upon the lowering of the
`8th l/O clock signal recognized by the device. Otherwise, additional common clock cycles will
`be recognized as l/O clocks and will shift in an erroneous address.
`
`For certain applications, such as strobing applications, it is necessary to start conversion at a specific point
`
`,
`
`_ in time. This device will accommodate these applications. Although the on—chip sample—and—hold begins
`sampling upon the negative edge of the 5th I/O clock cycle, the hold function is not initiated until the negative
`edge of the 8th l/O clock cycle. Thus, the control circuitry can leave the HO clock signal in its high state
`during the 8th l/O clock cycle, until the moment at which the analog signal must be converted. The
`TLC545/546 will continue sampling the analog input until the 8th falling edge of the HO clock. The control
`circuitry or software must then immediately lower the l/O clock signal to initiate the hold function at the
`desired point in time and to start conversion.
`
`Detailed information on interfacing to most popular microprocesors is readily available from the factory.
`
`steedsmegN
`
`..AhHmHPI—
`
`
`
`0.0000000.0
`
`
`
`2-180
`
`{if Samsung Electronics Co., Ltd. et al.
`TEXAS
`EX 1017, p. 11.5
`lNSTRUMENTS
`POST OFFICE BOX 655012 ' DALLAS. TEXAS 75265
`
`
`““th
`
`PRDBI
`curren
`specii
`Stand;
`"Buns:
`
`Samsung Electronics Co., Ltd. et al.
`Ex 1017, p. 11
`
`