.ci_-
`
`Address all telephone calls to: Mark A. Wolfe at (612) 340-5659.
`
`Address all correspondence to: Mark A. Wolfe at Dorsey & Whitney LLP. Pillsbury Center South,
`220 South Sixth Street, Minneapolis. Minnesota 55402.
`
`I hereby declare that all statements made herein of nty own knowledge ‘are true and
`that all statements made on infon-nation and belief are believed to be true; and further that these
`statements were made with the knowledge that willful false statements and the like so made are
`punishable by fine or imprisonment, or both, under Section 1001 of Title 18 of the United ‘States’,
`Code and that such willful false statements may jeopardize the validity of the application or any’
`patent issued thereon.
`.
`\
`
`
`Richard Weber
`Name of Sole or First Inventor
`
` /,2 M//{_
`
`.
`
`
`Inventor's Signature
`
`I33 la: gfljb 399$
`
`Date
`
`2972 North Woodcreek Lane
`
`Post Office Address
`
`Boise, Idaho 33704
`
`
`USA
`Citizenship
`
`2972 North Woodcreek Lane
`Boise, Idaho 33704
`Residence Address
`
` Core! Larsen
`
`Inventor's Signature
`
`
`no. Box ass
`Musing. Idaho 33639
`Post Office Address
`
`Name of Second Inventor
`
`8,
`
`.
`
`Date
`
`
`USA
`-
`Citizenship
`
`225 Canal Street
`
`Marsing. Idaho 83639
`Residence Address
`
`81
`
`81
`
`

`
`
`
`:5: ts
`ll-1%-fifi
`
`Docket: 6325
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Applicant:
`
`Richard Weber and Corey Larsen‘
`
`Serial No;
`
`09:'035.739
`
`_
`
`'
`
`'
`
`_
`
`HECEIVED
`Filing Date: March5, 1998
`Title:
`Method for Recovery of Useful Areas of Partially Defective Synchron
`$2
`93
`Memo[xCon'1pnnents
`.
`Cirg in Q;
`Inf rmalit) Disc]
`
`re talement
`
`Jr"
`i
`
`Assistant Commissioner for Patents
`Washington D.C. 20231
`
`Dear Sir:
`
`Pursuant to 37 CFR §1.56, the references listed on the attached Form PTO-1449 (1 sheet,
`
`;' «’
`
`submitted in duplicate] are being brought to the attention of the Examiner for consideration in
`
`connection with the examination of the above identified patent application. Copies of the
`
`identified references are enclosed.
`
`Applicant reserves the right to show, pursuant to 37 CFR §l .131 or otherwise, that any of
`
`the identified publications. and any referenced in the present application and its parent
`
`applications, is not prior art with respect to the present inventions.
`
`Iheteby cuufy that the document is being deposited
`with the United Suites Postal Service as first elm mail
`in an envelope addressed to: Assistant Comntiasioner
`
`
`
`82
`
`82
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`

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`
`
`that the Examiner consider each of the listed documents and initial and return to the undersigned
`
`a copy of the enclosed Form PTO-1449’.
`
`.
`..
`Respectfully submitted,
`
`WE:
`‘.
`F5
`‘OJ Q4’ 993
`C*i_.=___:;a ;7;n7-fl’3
`5
`
`‘
`
`Date:
`
`/9425; 73
`
`I
`
`By
`
`Niall A. MacLeod, Esq.
`Registration No. 41,963
`Dorsey & Whitney LLP
`Pillsbury Center South
`220 South Sixth Street
`Minneapolis, Minnesota 55402
`Telephone: (612) 343-2193
`Attorney for Applicant
`
`83
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`83
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` ______:_____________ __________ Sheet 1 ct 3
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`' ‘
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`-
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`ATFY DOCKET NO. 6325
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`
`
`INFORMATION DISCLOSURE
`ATEMENT BY APPLLGA
`39'°"*' ="'°°*9 " “W955
`
`
`
`
`
`J
`
`SEFIAAL NO. 09.739
`
`snow AFIT UNIT 2751
`
`APPLICANT Richard Weber and Gorey?
`
`
`
`FILING one Match 5. 1993
`LLS. PATENT DOCUMENTS
`
`ifixaruincr
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`initial if citation considered. whether or not citation is in conformance with MPEP 609: Draw line through ,
`EXAMINER:
`citation if not in conformance and not considered.
`include copy of this ton-n with next communication to applicant.
`
`
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`
`
`84
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`84
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`

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`Sheet 2 of 3
`_ SERIAL ND. 0‘!laI\‘.JG5.?39
`ADDCKE. B325
`APPLICANT Ftichand Weber and Goray Larsen
`
`_
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`‘
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`
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`- —_-._-.-.l
`GROUP AFIT UNIT 2751
`x
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`FfL|NG DATE March 5, 1998
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`-
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`NFOFIMATION DISCL
`STATEMENT BY APPL
`
`{use several sheets if naces
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`Dacurnant Description
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`cons: “-
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`Initiai if citation considered, whether
`—E§<AMINEFi:
`citation if not in conformance and not considered.
`
`or not citation is In conformance with MPEP S09; Draw line through
`Include copy of this form with next communication to applicant.
`
`85
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`85
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`""_ COMMERCE _ MTV DOCKET NO. 6325
`
`-
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`SERIAL N0. O9fO35,':"39
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`OSUFIE
`OF-WIATIDN D
`LLCJI
`ATEMENT BY
`(use several sheets if necees
`
`APF'LIC.I'tNT Flichard Weber and Corey Larsen
`
`‘I
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`Sheet 3 of 3
`
`FOREIGN PATENT DOCUMENTS
`' “TE 7- 77-"
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`It
`
`DTHEFI DOCUMENTS tnctudin Author TIIIE Date Pertinent Pass Etc.
`
`
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`—-
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`EXAMINER:
`citation if not in conformance and not considered.
`Include copy of tn‘
`
`forrnance with MPEP 609: Draw tine through ‘
`rrn with next communication to applicant.
`
`86
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`86
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`A'i'I'Y DOCKET NO. 6325
`
`Sheet 1 of 3
`seam. NO. 091035.739
`
`
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`_ ,
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`' .
`PTO-1-t-49 u.s DEPARTME
`
`.2-321 PATENT AND T
`iNFOFiMATi
`IIHSCLOSUFIE
`STATEME
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`{USE SBVBTEI SHBBISI
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`APPLICMIT Richard Weber and Dnrpy Larsen
`
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`._
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`
`I
`
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`
`_ FILING DATE March 5. 1993
`
`i____l______ __________
`U.S. PATENT DOCUMENTS .;:'.,
`““$?»‘33°' V ’
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`Initial it citation considered. whether or not citation is in
`INER:
`ion if not in conformance and not considered. Include copy of th‘
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`nformance with MPEP B09; Draw line through
`rm with next communication to applicant.
`
`87
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`87
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`ATTY DOCKEI’ N0. 5325
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`SERIAL N0. n9.'o35.‘.':59
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`I
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`Sheet 2 of 3
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`
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`GFIOUP ART UNIT 2'35?
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`1‘;
`
`APPLICANT Richard Weber and Coruy Lazsen
`
`
`
`s n-
`
`
`Form
`
`{Fla-.r.
`
`WFGRMATION DISOLOS
`'
`STATEMENT BY APPLIC
`
`(use several sheets if necessary}
`FILING DATE March 5. 1998
`
`
`_
`_
`U.5. PATENT DOCUMENTS
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`Document Description
`
` EXAMI El’-1:
`_T: —'enen‘T”-
`
`Initial it citation considered, whether or not citation Is in
`citatio it not in contormance and not considered. Include copy of th‘
`
`formanca with MPEP 609: Draw line through ‘
`rm with naxt communication to avplicant.
`
`88
`
`88
`
`

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`
`
`See! 3 of-3
`
`cnoup ART UNIT 2751
`
`_
`
`APPLICANT Filchard Weber and Gorey Lemon
`
`FILING DATE March 5. 1993
`
`IN FORMATION DISCLOSURE
`STATEMENT BY AF-‘PLWCANT
`{use several sheets If necessary}
`
`
`
`
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`Initial If citation
`EXAMINER:
`citation it not in conformance
`1.
`
`side-red. whether or not citation is in conformance with MPEP 609: Draw tine through
`not considered. Include copy at this form with next communication to applicant.
`
`89
`
`89
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`

`
`or
`' UNITED STATES DEPARTMENT OF COMMERCE"
`K‘ '
`Patent and Trademark Office
`' '
`X
`j Address-.
`COMMISSIONER OF FATENTS AND TRADEMARKS
`’flrn or
`Ws.s!1lngtnn.D.C.2O23i
`FlR5TNAMED*“VE”"°"
`
`1::-an) :35, 7239
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`IJIDRSEY 3: WHITNEY
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`PTLLSBURY CENTER SWTH ‘;~:;2I:1 E-CILITH SIXTH STREET " - '
`
`
`.-._.\—...a-
`2751
`HINNEAFDLIS MN 5540::
`DATE I|M‘LEIiI:
`
`lo/25/99
`
`Please find below and/oraltachad-an ‘Office-communloatlonloonoernlng this application or
`proceeding.
`
`Commissioner oi Patents and Tradomarksfih 5
`
`910-»: lfin. ms}
`
`1, ,1. cm,
`
`90
`
`90
`
`

`
`Office Action Summary
`
`Appiic " N0.
`06:
`
`0 3; 7]‘! Examiner
`
`p
`7.5‘
`(.1: //rs
`K9...‘
`--The MAILING-DATE of this communication appears on the cover sheet beneath the correspondence eddreeaw .
`
`Period for Iiieeponao
`A SHOHTENED STATUTORY PEFIIOD FOH RESPONSE IS SET TO EXPIREL MDNTH($) FROM THE
`MAIUNG DATE OF THIS CUMMUNICAUON.
`'
`-
`
`- Extensions cl time may be available under the pron-ieionsot 31' GFFl1.1‘.!B{a). in no event, however. may a response be timely filed other six (5) MONTHS
`item the mailing dale ofthia communication.
`- It the period tor response specified above is less Iiranii-iirty [30] days, eresponse within lhe statutory minimumoi thirty (30) days will oeconsioered lirne'ly.
`-it ND period lor response 'ns.spncitiee ab0V°i' such period shall, try de‘II.utt, expire SIX (6) M0l~i'|'t-I5 trorn the mailing date at this tmnrnunicalion .0/=’
`- Failure-In respond within the set orexiended period for response wil. bjnetetute. cause the application to become ABANDONED (35 u.s.c. § 1333}.
`
`Status
`l] Responsive to cornmunirrationtsi tiled on
`El This action is FINAL.
`
`\
`
`
`III Since this application is in condition tor allowance except for forrnaimatlers; prosecution as to the merits is closed in
`. accordance with the practice under Experie Ouayie. 1935 CD. 1 1; 453 0.6. 213.
`
`Disposition of Claims
`_
`E’ CIaIm(s) iefere pending in the application.
` isiere withdrawn from consideration.
`Of the above ciaim(s)
`
`DCmim(s) la.-‘are allowed.
`fic|mms) is-‘are rejected.
`UClalm{s) isiare objected to.
`U Clain1{s)
`are subject to restriction or election
`requirement.
`
`Application Papers
`B see the attached Notice of Drat1epereon's Patent Drawing Review. F'TO—94-8.
`E1 ‘the proposed drawing correction, tiledWe is Dappmved El disapproved.
`D ‘me erawingtat tiled on________,_,__ isiare objected to by the Examiner.
`Ci The specification is objected to by the Examiner.
`CI The oath or declaration is objected to by the Examiner.
`Friority under 35 u.5.c. § 119 ta)-(at
`El Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 11 9(a)-id).
`.. All
`C1 Some‘ ' E! None 01 the CERTIFIED copies of the priority documents have been
`' received.
`_ received in Application No. (Series Coclalserial Number)
`E. received in this national stage appflcallon from the International Bureau [PCT Rule t T.2(a)).
`‘Certified copies not received-
`Altaci1n1ent(s}
`fifiniomation Disclosure Staten-Ient{$). PTO-1 449,, Paper Nola).L Ellntieniiew Summary, PTO-413
`i3’Notice of Reterenr.-es Cited. PTO-892 .
`.
`E Notice ct lntorrnal Patent Application. PTO-152
`El Notice oi Dral“tsperaon'e Patent Drawing Review, F'TO-943
`Elmher
`
`‘-
`
`Ofllce Action Summary
`
`u. 5. Patent and race-nan-k oiiioe
`_
`_
`PTO-G25 tans-an
`'u.a.oeo:1ear4Ir-aaiiuflo
`
`Part of Paper No. S
`
`91
`
`91
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`

`
`K.1
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`- 2 ~
`Serial Numiier'§"o9ro35,739
`Art Unit: 2751
`
`Detailed Action
`
`1.
`
`2.
`
`Claims 1-8 are presented for examination.
`
`Information disclosed and listed on PTO 1449 was considered.
`
`_ Drawings
`
`-
`
`3.
`
`This application has been filed with informal drawings which are acceptable for
`
`examination purposes only. Formal drawings will be required when the application is allowed. J‘
`
`Claim Objections
`
`K
`
`4.
`
`Claims 1-8 are objected to because of the following inforrnaiities:
`Claims la d.
`recites:
`
`A)
`
`"to the microprocessor" (Lines 9 and 15 respectively} It is suggested that the
`
`word 'the‘ be changed to '21‘ since the ‘microprocessor’ as not been set forth it the
`claim.
`
`_
`
`Claims 24 and 6-8 are objected to as fully incorporating the defects of an objected base
`
`claim.
`
`Appropriate correction is required.
`
`Claim Rejections - 35 USC § 102
`
`5.
`
`The following is a quotation of the appropriate paragraphs of 35 USC § 102 that form
`
`the basis for the rejections under this section made in this Office action:
`
`A person shall be entitled to apatent unless --
`
`the invention was described in a patent granted on an application for patent by
`(e)
`another filed in the United States before the invention thereof by the applicant for
`patent. or on an international application by another who has fulfilled the requirements
`of paragraphs (1), (2), and (4) of section 371(c) of this title before the invention thereof
`by the applicant for patent.
`
`92
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`92
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`‘i
`la
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`'5’.
`r__..
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`Serial Number: 09I035,739
`Art Unit: 2751
`
`“"\
`
`5
`
`- 3 -
`
`6.
`
`Claims 1 and 2 are rejected under 35 USC 1020:) as being anticipated by Jacobson,
`
`U.S. Patent 5,920,513.
`
`A}
`
`As to claim 1, Jacobson discloses the invention as claimed. There is a method
`
`of accessing a memory module (Fig 4) comprising the acts of presenting a row address
`
`to the address inputs (see Col 3 Lines 2-12} of each of a plurality of partially defective
`
`SDRAM components {see Fig 4 & 5. Col 3 Lines 35-41, Col 4 Lines 25-42, and Col 5
`
`Lines 4-45) that have at least one unreliable data output {Col 3 Lines l2-27. Col 5
`
`Lines 4-7 & 33-45) and that also have a plurality of valid data outputs, wherein the
`
`valid data outputs are data outputs that provide reliable and accurate data (Col 3-Lines
`
`1247, Col 5 Lines 4-7 & 33-4-5). and presenting a column address to the address inputs
`of each SD_RAM component (Col 3 Lines 2-12), aggregating the valid data outputs of
`I
`each of the SDRAM components to provide a data path (see Fig 5 and C014 Lines 26- I
`6?‘), and communicating the data from the valid data outputs to a microprocessor (Col 4
`
`Lines ‘I-8; one of ordinary skill in the art would recognize that a computer would
`
`include some sort of processing device, ie. a microprocessor).
`
`As to claim 2, the act of presenting a row address does include the act of
`
`presenting a row address to the address inputs of partially defective SDRAM
`
`components (see Col 4 Line 67 to Col 5 Line 3), where for each of these SDRAM
`
`components, the plurality of valid data outputs are the same for each addressable
`
`memory location within that component so that the same portion of each addressable
`
`memory location within any given SDRAM component consistently provides valid and
`
`accurate data (see Col 3 Lines 13-27).
`
`Claim Rejections - 35 USC § 103
`
`The following is a quotation of 35 USC § 103 which forms the basis for all obviousness
`
`rejections set forth in this Office action:
`
`93
`
`93
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`

`
`- 4 -
`Serial Number: 091035339
`Art Unit: 2751
`
`A parent may not be obtained though the invention is not identically disclosed or
`described as set forth in section 102 of this title, if the differences between the subject
`matter sought to be patented and the prior art are such that the subject matter as a
`whole would have been obvious at the time the invention was made to 2‘: person having
`ordinary skill in the art to which said subject matter pertains. Patentability shall not be
`negatived by the manner in which the invention was made. ‘
`
`Subject matter developed by another person, which qualifies as prior an only
`under subsection (f) or (g) of section 102 of this title, shall not preclude patentability
`under this section where» the subject matter and the claimed invention were, at the time
`the invention was made, owned by the same person or subject to an obligation of
`assignment to the same person.
`Claims 3 and 4 are rejected under 35 USC § 103 as being unpatentable over Jacobson,
`US. Patent 5,920,513. in view of Dell et al., US. Patent 5,896,346.
`
`J .
`
`Ii‘
`
`A)
`
`As to claims 3 and 4, Jacobson discloses the invention substantially as claimed.
`
`However, Jacobson does not disclose that the SDRAM components are mounted on
`SIMMs or DIMMs.
`
`Dell et al. teaches that it was common for SDRAM_compor1ents to come
`mounted on
`or DIMMs (see Col 1 Lines 33-47:). SIMMS and DIMMS were
`common memory modules in the art at me time of the invention. They provide a
`
`convenient and standardized packaging of the SDRAM components which could be
`
`easily inserted into and removed from a computer system motherboard.
`
`_Aocordingly. it would have been obvious to one having ordinary skill in the art
`
`at the time of the invention to package the SDRAM components of Jacobson in a SIMM
`
`or DIMM module as these were common memory module designs in the industry.
`
`Claims 5 and 6 are rejected under 35 USC § 103 as being unpatentable over Jacobson,
`
`U.S. Patent 5,920,513, in view of Schaefer, U.S. Patent 5,636,173.
`
`A)
`
`As to claim 5, Jacobson discloses the invention substantially as claimed. There
`
`is a method of accessing memory cells in a memory module (Fig 4) having a plurality
`
`of SDRAM components (see Col 3 Lines 35-42), each of the SDRAM components
`
`having at plurality of address inputs (see Fig 5 and Col 4» Line 67 to C015 Line 3), the
`
`94
`
`94
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`

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`- 5 -
`I
`_
`Serial Number: o9ro35_739
`Art Unit; 2751
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`method comprising the acts of presenting a row address to the address inputs of each
`
`SDRAM component (see Col 3 Lines 2-12), presenting a column address to the address
`inputs of each SDRAM component (Col 3 Lines 2-12), wherein each of the SDRAM
`
`components is partially defective {see Fig 4 & . Col 3 Lines 35-41, Col 4' Lines 25-42,
`
`and Col 5 Lines 4-45) such that each SDRAM components has at least one unreliable
`
`data output (Col 3 Lines 12-27, Col 5 Lines 4—7 & 33-45) and also a plurality of valid”/'
`data outputs that provide reliable and accurate data (Col 3 Lines 12-27, Col 5 Lines 4i?
`
`& 33-45), aggregating the valid data outputs of each of the SDRAM components to
`
`provide a data path (see Fig 5 and C014 Lines 2667), and communicating the data
`from the valid data outputs from each of the SDRAM "components to a microprocessor
`
`(Col 4 Lines 7-8; one of ordinary skill in the art would recognize that a computer
`
`,
`
`would includesorne sort of processing device, i.e. a microprocessor). However,
`
`Jacobson does not disclose that each of the SDRAM components further comprises a
`
`plurality of banks of memory that are addressable by address inputs and that the method
`
`comprises selecting one of the plurality of banks within each SDRAM component by
`
`presenting at least one selection bit at the address inputs when the row address is
`
`presented to the address inputs.
`
`I
`
`- Schaefer teaches SDRAM components that comprise a plurality of banks of
`
`memory that are addressable by address inputs and that the selecting of one of the
`
`plurality of banks within the SDRAM component is performed by presenting at least
`
`one selection bit at the address inputs when the row address is presented to the address '
`
`inputs (see Col 1 Lines 2342-and Col 4- Lines 22-36). The advantage to using SDRAM
`
`with banks is that it allows interleaving between the two or more banks to hide the
`
`precharging time.
`
`Accordingly, it would have been obvious to one having ordinary Skill in the art
`
`at the time the invention was made to utilize SDRAM components that include a
`
`95
`
`95
`
`

`
`_~.I
`
`Serial Number: o9zo3s,739
`Art Unit: 2751
`
`- 6 —
`
`plurality of banks of memory that are addressable by address inputs and that the
`
`selecting of one of the plurality of banks within each SDRAM component is performed
`
`by presenting at least one selection bit at the address inputs when the row address is
`
`presented to the address inputs‘ as taught by Schaefer for the advantage that using
`
`. SDRAM components with multiple banks allows "the precharging time to be hidden thus
`
`increasing the speed of the memory.
`
`B)
`
`As to claim 6. the act of presenting a row address does include the act of
`
`presenting a row address to the address inputs of partially defective SDRAM
`
`components (see Col 4 Line 67 to Col 5 Line 3), where for each of these SDRAM
`
`components. the plurality of valid data outputs are the same for each a.dd.ressabl'e
`
`memory location within that component so that the same portion of each addressable
`memory location within any given SDRA-M component consistently provides valid and
`
`accurate data (see Col 3 Lines 13-27).
`
`10.
`
`Claims 7 and 8 are rejected under 35 USC§ 103 as ‘being unpatentable over Jacobson.
`US. Patent 5,920,513, and Schaefer. U.S. Patent 5,636,173, and in further view of Bell et.
`
`al., U.S, Patent 5,896,346.
`
`A)
`
`As to claims 1 and 3, Jacobson discloses the invention substantially as claimed.
`
`However, Jacobson does not disclose that the SDRAM components are mounted on
`SIMMS or DIMMS.
`
`Dell et al. teaches that it was common for SDRAM components to come -
`
`mounted on SIMMS. or DIMMS [sec Col 1 Lines 38-47). SIMMS and DIMMS were
`
`common memory modules in the art at the time of the invention. They provide a
`
`convenient and standardized packaging of the SDRAM components which could be
`easily inserted into and removed from a computer system motherboard.
`
`Accordingly, it would have been obvious to one having ordinary sltiii in the art
`
`96
`
`96
`
`

`
`Serial Number: 09/035,739
`Art Unit: 2751
`
`- 7 -
`
`at the time of the invention to package the SDRAM components of Iaoobson in a SIMM
`
`or DIMM module as these were common memory module designs in the industry;
`
`Conclusion
`
`11.
`
`The prior art made of record and not relied upon is considered pertinent to applicant's
`
`disclosure.
`
`-
`
`f’
`
`_ 12.
`
`A shortened statutory period for response to this action is set to expire 3 (three) month‘:
`
`and 0 (zero) days from the mail date of this letter. Failure to respond within the period for
`
`response will resultin ABANDONMENT of the application (see 35 USC 133, MPEP 710.02,
`
`710.02(b)).
`
`13.
`
`Any inquiry concerning this communication or earlier cornmunications from the
`
`Examiner should be directed to Kevin Ellis whose telephone number is (703) 305-9659. The
`
`Examiner can normally be reached on the weekdays from 5:3Darn to 3:00pm.
`
`If attempts to reach the Examiner by telephone are unsuccessful, the Examiner's
`
`supervisor, Eddie Chan, can be reached on (703) 305-9712.
`
`Any response to this action should be mailed to:
`
`Commissioner of ram: and Thdenurks
`I
`i
`Washington. DJ2. 2023 I
`' or mud ID:
`(703)305-9051. (for format communications intended for entry}
`Hand-delivered responses should his brought to Crystal. Park I1, 2121 Crystal Drive, Arlington, VA. Sixdi Floor (Receptionist).
`
`Any inquiry of a general nature or relating to the status of this application should be
`
`directed to the Group receptionist whose telephone number is (703) 305-3900.
`
`Kevin L. Ellis
`Patent Examiner
`October 22, 1999
`
`/4..rzf%
`
`97
`
`97
`
`

`
`To savanna, I:I"'_ "_'-':‘i- mo ao'r1-on eases. SNAP-APART mo.""‘°Aao cmaou _
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`u.s. oEPAérMs.I_HT or‘ COMMERCE
`Form! PTO-892
`'
`D.n1'EN1‘ AND TRADEMIIRK oI=FIcE
`|HEV_z-92}
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`ATTACHMENT '
`mus:
`TD
`NUMBER
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`5
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`-j-mmmsammm———EEl'E!EEWE-nuanmammnn-_-flE_E»..>V‘E-
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`PERTINENT
`
`owc;
`
`sash,
`
`EXAMINER
`
`Keviln a: g [[5
`' A copy of this reference is not being iumished with this office action.
`{See Manual of Patent Examining Procedure, section '!{}?.05 lair.)
`
`98
`
`

`
`Docket:_6325
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`é
`
`Applicant‘:
`
`Serial No.:
`
`Richard Weber and Corey Larsen
`'
`
`09!'035,739
`
`Filing Date: March 5. 1993
`
`JAN 5 - 2500
`
`G'.’°Uo- 2700
`
`Examiner: K. Ellis
`
`Title:
`
`'
`
`Method for Recovery ofUseful Areas of Partially
`Defective Synchronous Memory Components
`
`Group Art Unit: 2751
`-
`
`/1
`
`COMBINED: (1) INFORMATION DISCLOSURE STATEMENT
`(2) CERTIFICATION UNDER 37 C.F.R. §].9'.-'(c) and (2)
`
`K
`
`Assistant Commissioner for Patents
`' Washington D.C. 20231
`
`Dear Sir:
`
`(1) Information Disclosure Statement
`
`Pursuant to 37 C.F.R. §1.56, the references listed on the attached form PTO-1449 (1
`
`sheet, submitted in duplicate) are being brought to the attention of the Examiner for
`
`consideration in connection with the examination ofthe above identified patent application.
`
`_
`
`Copies of the identified references are enclosed. These references were cited in an Office Action
`
`mailed December 8, 1999, by Examiner P. Kcrmanyos in related application Serial No.
`
`o9;o3s,e29.
`
`_
`
`lherehy certify HIM the floculllentis being deposited
`with the United States Postal Service as first class mail
`in an envelope attdreseed to: Assistant Commissioner
`for Patents, Weshingecn, 11c. 2023i on
`.9.
`(D te ofDeposIt
`-
`
`I
`
`a./Lr
`
`a.
`
`
`
`99
`
`99
`
`

`
`IA.
`
` '91,}
`
`(2) Certification Unde
`
`The undersigned hereby certifies that no item of information contained in the above
`
`Information Disclosure Statement was cited in a communication from a foreign patent office in a
`
`counterpart foreign application or, to the _knowledge of the undersigned, was known to any
`
`individual designated in §1.56(c) more than three months prior to the filing of this statement.
`Pursuant to the Manual‘ofPatent Examining Procedure, Chapter 609, Applicant requests 7/'
`that the Examiner consider each ofthe listed documents and initial and return to the undersigned\.
`
`"a copy ofthe enclosed Form PTO—1449 (submitted in duplicate).
`
`Respectfully submitted,
`
`Date:
`
`/Z5217;
`
`By W '
`
`.;
`
`_,
`
`Niall A. MacLeod
`Registration No. 41,963
`Dorsey & Whitney LLP
`220 South Sixth Street
`Minneapolis, Minnesota 55402
`Telephone: 612/340-2755
`
`Attorney for Applicant
`
`100
`
`100
`
`

`
`,;.
`Fo PTO-144$ US DEPARTMENT OF COMEHCE
`[Ravi 2-32]
`PATENT AND TRADEMARK OFFICE
`INFoHMAT!ON DISCLOSURE
`STATEMENT BY APPLICANT
`{use several sheets II moassary}
`
`.fl'|T‘I"-DD O. 6325
`_
`
`'
`
`.’
`
`Sht1 of i
`BEFIIAL NO. 09i’035.?3-9
`'
`
`
`
`
`
`u.s. PATENT DOCUMENTS
`_______________
`IE ===
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`Ar:-3-...
`IBE-
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`Docu_n1anl Description
`
`
`1 INTEL, PC SDRAM IJNBUFFEFIED DIMM SPEC1FICAT|ClN. REVISION 1.0, Fahruary_15“aa. -1?’ pages
`I INTEL. PC SDFIAM SPECIFICATION. REVISION 1.63. October 1998
`
`ATE DNSIEED 3’/Io/00
`
`
`
`Initial if citation considered. whether or not citation is in conformance with MPEP 609; Draw line through
`EXAMINER:
`citation if not in conformance and not considered. Include oopy of this form with next communication to applicant.
`
`~
`
`101
`
`101
`
`

`
`
`
`
`
`.'
`RPPLICANT Fiilll'|a.TU W856!‘and O'--.-‘‘.-!;
`FILING DATE March 5, 1993
`
`.
`
`.,
`
`STATEMENT BY APFLICNW
`
`\ ‘P E «O
`__=_\I %
`_
`.
`. ....___.._._._._ _....___..._._..._ ._.._.....L__'_ . _.._.._.j
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`.__....____..._.___ ._.._..__._.._.... _
`Form PTO-‘I449 U.S DEPARTMENT OF CUMME
`E
`ATTY DOCKET NO. 6325
`'-'- ‘
`.
`(HOV. Z532]
`PATENT AND TRADEMARK 0
`E
`_"
`WNFDRMATIUN DISCLOSURE
` (use several sheets Ii nscessanii
`
`.
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`1
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`_ ‘
`.._____
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`u.s. PATENT DOCUMENTS
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`FOREIGMENTS
`.____
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`é.___A..._. __,.__ _ _ __ :
`______.___.
`F
`_
`_
`Examiner
`5uIJ-
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`____._____ ._ ___..__!_!Q!!lL_.___..._________§_%§j
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`cludin Author,Titie Data PeI'1inentPaes Etc.
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`iiiai if citation considered. whether or not citation is in conformance with MPEP 609; Draw time through
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`citation if no in conformance and not considered.
`inciude copy of this iorm wiih next communication to applicant.
`
`102
`
`102
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`

`
`.,9ir/2*“
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`
`-
`
`Docket: 5325
`
`.-:_£'yI_a_.}S‘l/""1131'I‘_I-IEUNITED-"STATES PATENTAmpTRADEMARKOFFICE
`
`Richard Weber and Corey Larsen
`
`Applicant:
`.
`09/035,739
`Serial No;
`Filing’ Date: March 5, 1998
`
`
`
`F5?
`2%?
`0'0
`c.-.
`L0 _'__.
`5.‘
`Exarnineg }(::_l§l1lsL'Fl
`3; 3 '-‘*3
`Group Art [git 2751
`Method for Recovery of Useful Areas of Partially
`Title:
`it-s
`Defectives
`chronous Memo Com nents
`
`
`l\'men'dment and Regtiest for Reconsideration
`
`“fyfiI
`
`
`3.
`
`
`
`Assistant Comrnissioner for Patents
`Washington D.C. 20231
`
`Dear Sir:
`
`The following amendments and remarks are submitted in response to the Office A-ction of
`
`October 26, 1999.
`
`L
`
`In the Claims
`
`Please amend the claims as follows:
`
`1. (Amended) A method of accessing a memory module comprising the acts of:
`
`Q>
`
`‘
`
`presentingarow address totheaddressinputs ofeachofapluralityofpartiallydefective
`
`SDRAM components that have at least one unreliable data output, and that also have a plurality
`
`.
`
`'\
`
`'
`
`I hetchy certify that the document is being deposits}
`with the Uniteaj_5tales Postal Service as firs! class mail
`in an envelope addressed to: Assistant Colpmissionu
`for Patents. Wttshttlgtnn. D.C 2023! on
`'
`'
`D00
`n:ofDepos'n)
`_
`C_
`E
`-
`(Nana:
`5
`Signature
`
`re ofSignature
`
`I
`
`_/ at
`
`103
`
`
`
`103
`
`

`
`of valid data outputs, wherein the valid data outputs are data outputs that provide reliable and
`
`accurate data; and
`
`presenting a column address to the address inputs of each SDRAM component;
`
`aggregating the valid data outputs of each of the SDRAM components to provide a data
`
`path; and
`
`xr
`-*I
`\
`
`communicating the data from the valid data outputs to g [the] microprocessor,
`
`
`
`5. A method of accessing memory cells in a memory module having a plurality of SDRAM
`
`components, each of the SDRAM components having a plurality of address inputs, and wherein
`
`each of the SDRAM components further comprises aplurality of banks of memory that are
`
`addressable by the address inputs, the method comprising the acts of:
`
`presenting a tow address to the address inputs of each SDRAM component;
`
`presenting a column address to the address inputs of each SDRAM component;
`
`selecting one of the plurality of banks within each SDRAM component by presenting at
`
`least one selection bit at the address inputs when the row address is presented to the address
`
`inputs. wherein each of the SDRAM components is partially defective such that each SDRAM
`
`components has at least one unreliable data output, and also a plurality of valid data outputs that
`
`provide reliable and accurate data;
`
`aggregating the valid data outputs" of each of the SDRAM components to provide a data
`
`path; and
`
`communicating the data -from die valid data outputs from each of the SDRAM
`
`components to g [the] microprocessor.
`
`
`Page 2 of 5
`
`104
`
`104
`
`

`
`II:
`
`Remarks
`
`A.
`
`Office Action Dated October 26, 1999
`
`In the Office Action dated October 26, 1999, the Examiner rejected all pending claims 1-
`
`8 in light of U.S. Patent Nos. 5,920,513 to Jacobson, 5.896346 to Dell. and 5,636,173 to
`
`Sehaefer. The primary reference cited by the Examiner (and the only one discussed further) is
`
`.
`
`the Jacobson reference. While the Jacobson reference and the present invention are directed to
`I
`solutions to the same problem —— how to avoid complete replacement of a memory device that is
`
`_,«r'
`
`I
`\
`
`only partially defective ~- they do so in patentably distinct manners.
`
`In Jacobson, repair sites 54 and 56 are provided on a particular memory chip module 32
`
`in anticipation that one or more of the memory device 33, etc. on the module 32 will be partially
`
`defective. g Figs. 3 and 4. In the event that a memory device 33. etc. is found to be defective,
`
`the data lines of the memory device 33. etc. that correspond to the defective portions of memory
`
`device 38, etc. are linked to the data lines of a memory device 66 {termed a “repair memory
`
`device“) located in the repair sites 54 and 56.
`
`In this manner. according to the Jacobson
`
`reference, “[r]ather than replacing device 38 entirely, repair device 66 only g_e1)lt;t;e<s those
`
`sections of device 38 that are defective." Jacobson, col. 5, lines 7-9.
`
`In the present invention, however, the problem is solved in a different manner. The
`present invention, unlike Jacobson. does not -require the addition of repair memory devices to
`
`E partially defective memory portions, rather the present invention aggregates mg
`
`SDRAM data outputs found to be reliable in order to form the desired bank of memory. E.
`
`Application, p. 6. lines 10-13 (“By using the twelve nondefective DQ outputs from SDRAM
`components 54. 55, S7. and 58 and by using the eight nondefective DQ outputs from SDRAM X\
`
`Page 3 of S
`
`105
`
`105
`
`

`
`\-
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`.1-5
`
`components 56 and 59. a 512K I 64 x 2 memory module can be constructed from the six
`partially defective SDRAM components").
`-
`
`These two ‘approaches are quite distinct. In Jacobson. the amount of memory planned for
`
`the module prior to the detection of defects is _main_tained, but it is maintained at a price —- space
`
`on the memory module must be reserved for one or more of the "memory repair devices." In
`
`contrast, in the present invention, several defective memory devices ofcapacity N are used to
`
`J
`
`.7
`
`\
`
`form an "aggregate" memory device of the same capacity N, out in the present invention; no
`
`additional components are required. Rather, the valid data outputs of the SDRAMS are
`
`aggregated to form the data outputs of an overall “non-defective" memory device of capacity N.
`
`The Applicant submits that this aspect of the present invention differentiates Jacobson and it is
`
`c