I lllll llllllll Ill lllll lllll lllll lllll lllll 111111111111111111111111111111111
`US007834605B2
`
`c12) United States Patent
`Balakrishnan et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,834,605 B2
`*Nov. 16, 2010
`
`(54) METHOD AND APPARATUS FOR
`MAINTAINING A CONSTANT LOAD
`CURRENT WITH LINE VOLTAGE IN A
`SWITCH MODE POWER SUPPLY
`
`(52) U.S. Cl. ....................................... 323/282; 323/273
`(58) Field of Classification Search ......... 323/282-288,
`323/235-239, 220-223, 272-275; 363/79,
`363/80,97, 131,63, 89
`See application file for complete search history.
`
`(75)
`
`Inventors: Balu Balakrishnan, Saratoga, CA (US);
`Alex B. Djenguerian, Saratoga, CA
`(US); Kent Wong, Fremont, CA (US);
`David Michael Hugh Matthews,
`Windsor (GB)
`
`(73) Assignee: Power Integrations, Inc., San Jose, CA
`(US)
`
`( *) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`3,694,772 A
`
`9/1972 Sordello
`
`(Continued)
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`
`0 744 818 Al
`
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`
`(Continued)
`
`OTHER PUBLICATIONS
`
`This patent is subject to a terminal dis(cid:173)
`claimer.
`
`(21) Appl. No.: 12/581,054
`
`(22) Filed:
`
`Oct.16, 2009
`
`(65)
`
`Prior Publication Data
`
`US 2010/0033147 Al
`
`Feb. 11, 2010
`
`Related U.S. Application Data
`
`(63)
`
`Continuation of application No. 11/784,560, filed on
`Apr. 6, 2007, now Pat. No. 7,646,184, which is a con(cid:173)
`tinuation of application No. 11/397,524, filed on Apr.
`3, 2006, now Pat. No. 7,215,105, which is a continua(cid:173)
`tion of application No. 10/892,300, filed on Jul. 15,
`2004, now Pat. No. 7,110,270, which is a continuation
`of application No. 10/253,307, filed on Sep. 23, 2002,
`now Pat. No. 6,781,357.
`
`(60)
`
`Provisional application No. 60/325,642, filed on Sep.
`27, 2001.
`
`(51)
`
`Int. Cl.
`GOSF 1140
`
`(2006.01)
`
`U.S. Appl. No. 90/009,393, filed Jan. 20, 2009, Power Integrations,
`Inc.
`
`(Continued)
`Primary Examiner-Rajnikant B Patel
`(74) Attorney, Agent, or Firm-Blakely Sokoloff Taylor &
`Zafman, LLP
`
`(57)
`
`ABSTRACT
`
`A power supply regulator including a variable current limit
`threshold that increases during an on time of a switch. In one
`aspect, a power supply regulator includes a comparator that
`has a first input coupled to sense a voltage representative of a
`current flowing through a switch during an on time of the
`switch. The comparator has a second input coupled to receive
`a variable current limit threshold that increases during the on
`time of the switch. A feedback circuit is coupled to receive a
`feedback signal representative of an output voltage at an
`output of a power supply. A control circuit is coupled to
`generate a control signal in response to an output of the
`comparator and in response to an output of the feedback
`circuit. The control signal is to be coupled to a control termi(cid:173)
`nal of the switch to control switching of the switch.
`
`12 Claims, 5 Drawing Sheets
`
`DRAIN
`12
`
`SOURCE
`
`ON SEMICONDUCTOR EXHIBIT 1001
`Page 1 of 11
`
`

`
`US 7,834,605 B2
`Page 2
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`
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`
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`
`JP
`
`FOREIGN PATENT DOCUMENTS
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`OTHER PUBLICATIONS
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`Translation), mailed Oct. 21, 2008.
`European Search Report, EP 02256760, Feb. 2, 2005.
`Infineon Technologies Preliminary Datasheet, "ICE2ASO 1; Off-Line
`SMPS Current Mode Controller," Datasheet, Version 2.1, Feb. 2001,
`Infineon Technologies AG, Miinchen, Germany.
`National Semiconductor: Linear and Switching Voltage Regulator
`Fundamentals, 'Online: XP002316042 Retrieved from the Internet:
`URL: http://web.archive.org/web/20010602192453/http://www.na(cid:173)
`tional .corn/ appinfo/powerfiles/f 4. pdf>.
`Linear Technology, LT1375/LT1376, "l.5A, 500kHz Step-Down
`Switching Regulators," 1995, pp. 1-28.
`Infineon Technologies AG, Edition Apr. 11, 200, "Off-Line Current
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`16822, Datasheet, Vl.O, Apr. 11, 2000, pp. 1-15.
`Infineon Technologies, "Off-Line Current Mode Controller with
`Coo!MOS™ on board," Coo!SET™-Fl TDA 16822, Datasheet,
`V2.0, Apr. 11, 2000, pp. 1-14.
`Tea 1566 GreenChip™; SMPS Module, Preliminary Specifications,
`Integrated Circuits, Philips Semiconductors, Apr. 20, 1999, pp. 1-24.
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`Edition, Published by Cambridge University Press, New York, 1989,
`Chapter 5, pp. 263-305.
`Analog Devices, "Secondary Side, Off-Line Battery Charger Con(cid:173)
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`pages).
`Unitrode Integrated Circuits, " Application Note U-lOOA: The
`UC3842/3/4/5 Series of Current-Mode PWM IC's," published in
`"Product and Application Handbook 1994-1995," Jun. 1993, at pp.
`9-64 through 9-75; (12 pages).
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`Maxim, "How to Design Battery Charger Applications that Require
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`(16 pages).
`Chester Simpson, "Battery Charging," National Semiconductor, No
`Available Publication Date. ( 17 pages).
`* cited by examiner
`
`ON SEMICONDUCTOR EXHIBIT 1001
`Page 2 of 11
`
`

`
`ON SEMICONDUCTOR EXHIBIT 1001
`Page 3 of 11
`
`

`
`U.S. Patent
`
`Nov. 16, 2010
`
`Sheet 2 of 5
`
`US 7 ,834,605 B2
`
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`ON SEMICONDUCTOR EXHIBIT 1001
`Page 4 of 11
`
`

`
`U.S. Patent
`
`Nov. 16, 2010
`
`Sheet 3 of 5
`
`US 7 ,834,605 B2
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`ON SEMICONDUCTOR EXHIBIT 1001
`Page 5 of 11
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`310
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`
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`320
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`ON SEMICONDUCTOR EXHIBIT 1001
`Page 6 of 11
`
`

`
`400
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`......... -- ... -----
`-~---#-----«::'"---~-------
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`
`\
`
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`CHARACTERISTICS DEPENDS ON EXACT
`CIRCUIT CONFIGURATION ANO
`COMPONENT CHARACTERISTICS
`
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`
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`COMPONENT CHARACTERISTICS ~ NOl
`NECESSARILY A STRAIGHT LINE AS SHOWN
`
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`
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`ON SEMICONDUCTOR EXHIBIT 1001
`Page 7 of 11
`
`

`
`US 7,834,605 B2
`
`1
`METHOD AND APPARATUS FOR
`MAINTAINING A CONSTANT LOAD
`CURRENT WITH LINE VOLTAGE IN A
`SWITCH MODE POWER SUPPLY
`
`RELATED APPLICATION
`
`This application is a continuation of U.S. application Ser.
`No. 11/784,560, filed Apr. 6, 2007, now pending, which is a
`continuation of U.S. application Ser. No. 11/397,524, filed
`Apr. 3, 2006, now U.S. Pat. No. 7,215,105 B2, which is a
`continuation of U.S. application Ser. No. 10/892,300, filed
`Jul. 15, 2004, now U.S. Pat. No. 7,110,270 B2, which is a
`continuation of U.S. application Ser. No. 10/253,307, filed
`Sep. 23, 2002, now U.S. Pat. No. 6,781,357 B2, which claims
`the benefit of and priority to U.S. provisional application Ser.
`No. 60/325,642, filed Sep. 27, 2001, entitled "Method And
`Apparatus For Maintaining A Constant Load Current With
`Line Voltage In A Switch Mode Power Supply."
`
`BACKGROUND OF THE INVENTION
`
`2
`supply has an output characteristic having an approximately
`constant output voltage below an output current threshold and
`an approximately constant output current below an output
`voltage threshold. A regulation circuit is coupled between the
`power supply input and the power supply output. The regu(cid:173)
`lation circuit includes a semiconductor switch and current
`sense circuitry to sense the current in the semiconductor
`switch. The current sense circuitry has a current limit thresh(cid:173)
`old. The regulation circuit current limit threshold is varied
`10 from a first level to a second level during the time when the
`semiconductor switch is on. In another aspect, the current
`limit threshold being reached coincides with the power sup(cid:173)
`ply output characteristic transitioning from providing an
`approximately constant output voltage to supplying an
`15 approximately constant output current. In yet another aspect,
`the semiconductor switch is a MOSFET. Additional features
`and benefits of the present invention will become apparent
`from the detailed description and figures set forth below.
`
`20
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention detailed illustrated by way of
`example and not limitation in the accompanying figures.
`FIG. 1 is a schematic of one embodiment of a switched
`mode power supply regulator in accordance with the teach(cid:173)
`ings of the present invention.
`FIG. 2 is a diagram illustrating one embodiment of saw(cid:173)
`tooth, duty cycle and intrinsic current limit waveforms in
`accordance with the teachings of the present invention.
`FIG. 3 shows one embodiment of a power supply that has
`an approximately constant voltage and constant current char(cid:173)
`acteristic in accordance with the teachings of the present
`invention.
`FIG. 4 shows one embodiment of a power supply that has
`an approximately constant voltage and constant current char(cid:173)
`acteristic in accordance with the teachings of the present
`invention.
`FIG. 5 is a diagram illustrating the typical relationship
`between the output current and output voltage of one embodi(cid:173)
`ment of a power supply in accordance with the teachings of
`the present invention.
`
`DETAILED DESCRIPTION
`
`Embodiments of methods and apparatuses for maintaining
`a power supply output current substantially constant indepen(cid:173)
`dent of input voltage at the point where the power supply
`output characteristic transitions from providing an approxi(cid:173)
`mately constant output voltage to supplying an approxi-
`50 mately constant output current are disclosed. In the following
`description, numerous specific details are set forth in order to
`provide a thorough understanding of the present invention. It
`will be apparent, however, to one having ordinary skill in the
`art that the specific detail need not be employed to practice the
`55 present invention. In other instances, well-known materials or
`methods have not been described in detail in order to avoid
`obscuring the present invention.
`Reference throughout this specification to "one embodi(cid:173)
`ment" or "an embodiment" means that a particular feature,
`60 structure or characteristic described in connection with the
`embodiment is included in at least one embodiment of the
`present invention. Thus, the appearances of the phrases "in
`one embodiment" or "in an embodiment" in various places
`throughout this specification are not necessarily all referring
`to the same embodiment. Furthermore, the particular fea(cid:173)
`tures, structures or characteristics may be combined in any
`suitable manner in one or more embodiments.
`
`1. Field of the Invention
`This invention relates generally to power supplies and,
`more specifically, the present invention relates to a switched 25
`mode power supply.
`2. Background Information
`All electronic devices use power to operate. A form of
`power supply that is highly efficient and at the same time
`provides acceptable output regulation to supply power to 30
`electronic devices or other loads is the switched-mode power
`supply. In many electronic device applications, especially the
`low power off-line adapter/charger market, during the normal
`operating load range of the power supply an approximately
`constant output voltage is required below an output current 35
`threshold. The current output is generally regulated below an
`output voltage in this region of approximately constant output
`voltage, hereafter referred to as the output voltage threshold.
`In known switched mode power supplies without second(cid:173)
`ary current sensing circuitry, minimizing the variation of the 40
`output current at the output voltage threshold is performed
`with complex control schemes. Typically, these schemes
`include the measurement of input voltage, output diode con(cid:173)
`duction time and peak primary current limit. Some or all of
`this measured information is then used to control the regulator 45
`in order to reduce the variation of the output current at the
`output voltage threshold.
`
`SUMMARY OF THE INVENTION
`
`A power supply that maintains an approximately constant
`load current with line voltage below the output voltage thresh(cid:173)
`old is disclosed. In one embodiment, a regulation circuit
`includes a semiconductor switch and current sense circuitry
`to sense the current in the semiconductor switch. The current
`sense circuitry has a current limit threshold. The regulation
`circuit current limit threshold is varied from a first level to a
`second level during the time when the semiconductor switch
`is on. In one embodiment, the regulation circuit is used in a
`power supply having an output characteristic having an
`approximately constant output voltage below an output cur(cid:173)
`rent threshold and an approximately constant output current
`below an output voltage threshold. In another embodiment, a
`power supply is described, which includes a power supply
`input and a power supply output and that maintains an 65
`approximately constant load current with line voltage below
`the output voltage threshold. In one embodiment, the power
`
`ON SEMICONDUCTOR EXHIBIT 1001
`Page 8 of 11
`
`

`
`US 7,834,605 B2
`
`3
`In one embodiment here, a switched mode power supply is
`described in which the output current below the output volt(cid:173)
`age threshold, is regulated to be approximately constant. This
`provides an approximate constant voltage/constant current
`output characteristic. The output current level at the output
`voltage threshold in known power supplies sensed at the
`output of the power supply to provide feedback to a regulator
`circuit coupled to the primary winding of the power supply. If
`however, the approximate constant current functionality is
`achieved without feedback from the secondary winding side 10
`of the power supply, the output current at the output voltage
`threshold is a function of a peak current limit of the primary
`regulator.
`Embodiments of the present invention reduce the variation
`of the output current at the output voltage threshold by reduc(cid:173)
`ing the peak current limit variation with changing input volt(cid:173)
`age. In general, the intrinsic peak current limit is set by
`internal circuitry in the regulator to be constant. In one
`embodiment, once the drain current reaches a current limit
`threshold, the switching cycle should, in theory, terminate
`immediately. However, a fixed delay is inherent from the time
`the threshold is reached until the power metal oxide semicon(cid:173)
`ductor field effect transistor (MOSFET) is finally disabled.
`During this delay, the drain current continues to ramp up at a
`rate equal to the direct current (DC) input voltage divided by
`the primary inductance of the transformer (drain current ramp
`rate). Therefore, the actual current limit is the sum of the
`intrinsic current limit threshold and a ramp-rate dependent
`component (the overshoot), which is the drain current ramp
`rate multiplied by the fixed delay. Thus, at higher DC input
`voltages, the actual current limit ramps to a higher level above
`the intrinsic current limit level than at low DC input voltages.
`This can result in variations in the output current delivered to
`the load at the output voltage threshold over a range of input
`line voltages.
`The actual current limit is the sum of the intrinsic current
`limit and the ramp-rate dependent component (the over(cid:173)
`shoot). The goal is to maintain a constant actual current limit
`over DC input voltage variations. Since the ramp-rate com(cid:173)
`ponent (the overshoot) increases with respect to the DC input
`voltage, the only way to maintain a relatively constant current
`limit would be to reduce the intrinsic current limit threshold
`when the DC input voltage rises.
`In discontinuous power supply designs, the point in time
`during the switching cycle in which the current limit is
`reached is dependent on the DC input voltage. In fact, the time
`it takes from the beginning of the cycle to the point where
`current limit is inversely proportional to the DC input voltage.
`Thus, the time elapsed from the beginning of the cycle can be 50
`used to gauge the DC input voltage.
`Therefore, in order to create an intrinsic current limit which
`decreases relative to the DC input voltage, the time elapsed
`can be used. It is simply necessary to increase the intrinsic
`current limit as a function of the time elapsed during the cycle. 55
`A first approximation for increasing the intrinsic current limit
`with time can be obtained by using the Equation 1 below:
`
`(Equation 1)
`
`where is ILIM-INTRINsic the intrinsic current limit, K 1 and K2
`are constants and telapsed is the time elapsed.
`In one embodiment, the time elapsed can be detected by the
`internal oscillator output waveform. In one embodiment, this
`waveform is a triangular one. It starts at its minimum at the
`beginning of the cycle. It gradually ramps until it reaches the
`point of maximum duty cycle.
`
`4
`In one embodiment, the ramp is substantially linear with
`time. In another embodiment, the ramp can also be nonlinear
`depending on the requirements of the power supply in which
`the regulator is used. The intrinsic current limit threshold is
`basically proportional to the voltage seen at the input of the
`current limit comparator. This bias voltage is the product of
`the resistor value and the current delivered to this resistor.
`One way to increase the intrinsic current limit linearly as a
`function of the elapsed time would then be to derive a linearly
`increasing (with elapsed time) current source and deliver this
`current to the resistor. This linearly increasing (with elapsed
`time) current source can thus be derived from the oscillator.
`FIG.1 shows a schematic of one embodiment of a switched
`mode power supply in accordance with the teachings of the
`15 present invention. All of the circuitry shown in this schematic
`is used to control the switching of the power MOSFET 2. The
`timing of the switching is controlled by oscillator 5. Oscilla(cid:173)
`tor 5 generates three signals: Clock 10, DMAX (Maximum
`duty cycle) 15, and Sawtooth 20. The rising edge of Clock
`20 signal 10 determines the beginning of the switching cycle. As
`shown in the illustrated embodiment, when Clock signal 10 is
`high, output latch 90 is set, which results in a control signal
`output from output latch 90 to enable power MOSFET 2 to
`begin conducting. The maximum conducting time is deter-
`25 mined by DMAX 15 signal being high. When DMAX 15
`signal goes low, latch 90 is reset, thus causing the control
`signal output from latch 90 to disable power MOSFET 2 from
`conducting.
`The intrinsic current limit is, to the first order proportional
`30 to the voltage on node 22. As stated earlier, the goal of the
`invention is to generate an intrinsic current limit proportional
`to the time elapsed in the switching cycle. The saw tooth
`waveform 20 can be used to perform this task. As the base
`voltage of NPN transistor 30 rises, the emitter voltage also
`35 rises at the same rate. Thus, the current through resistor 25 is
`linearly increasing with time elapsed during the switching
`cycle. After mirroring this current through current mirror 40,
`the linearly increasing (with elapsed time) current source 27
`is derived. The current limit threshold 22 is thus proportional
`40 to the product of the combination of linearly increasing cur(cid:173)
`rent source 27 and constant current source 50 with the resistor
`17. The voltage on node 37 is proportional to the power
`MOSFET drain voltage because of the voltage divider net(cid:173)
`work formed by resistors 55 and 60. The drain current is
`45 proportional to the drain voltage. As the drain current 7 ramps
`up during the switching cycle, the voltage on node 37 rises
`proportionately. After the voltage on node 37 exceeds the
`voltage on current limit threshold node 22, comparator 70
`disables the power MOSFET by ultimately resetting latch 90.
`PWM Comparator 32 modulates the duty cycle based on
`the feedback signal coming from the output of the power
`supply. The higher the feedback voltage, the higher the duty
`cycle will be.
`FIG. 2 shows an embodiment of three waveforms: saw(cid:173)
`tooth 20, duty cycle max 15, and intrinsic current limit 22.
`The sawtooth waveform 20 and the duty cycle max waveform
`15 are generated by the oscillator 5. The duty cycle max 15
`signal determines the maximum duration of a power MOS(cid:173)
`FET switching cycle, when it is high. The sawtooth waveform
`60 20 starts increasing at the low point when the duty cycle max
`waveform 15 goes high. This signals the beginning of the
`power MOSFET switching cycle. The high point of the saw(cid:173)
`tooth 20 is reached at the end of the cycle, at the same time the
`duty cycle max signal 15 goes low. The intrinsic current limit
`65 22 signal starts at the low point at the beginning of the cycle
`and then linearly increases with elapsed time throughout the
`cycle. At a time elapsed of zero, the intrinsic current limit is at
`
`ON SEMICONDUCTOR EXHIBIT 1001
`Page 9 of 11
`
`

`
`US 7,834,605 B2
`
`30
`
`5
`K 1 As time elapsed increases, the current limit increases by a
`factor of K2 *telapsed· As can be seen in FIG. 2 therefore, the
`intrinsic current limit (ILIM-INTRINsid is the sum of K 1 and
`K2 *telapsed·
`FIG. 3 shows one embodiment of a power supply that has
`an approximately constant voltage and constant current char(cid:173)
`acteristic in accordance with the teachings of the present
`invention. An energy transfer element 220 is coupled between
`DC output 200 and HV DC input 255. In one embodiment,
`energy transfer element is a transformer including an input 10
`winding 225 and an output winding 215. Regulation circuit
`250 is coupled between HV DC input 255 and energy transfer
`element 220 to regulate DC output 200. In the illustrated
`embodiment, feedback information responsive to DC output
`200 is provided to the regulator 250 at its control pin. The 15
`current at the control pin is proportional to the voltage across
`resistor 235, which in tum is related to the output voltage at
`DC output 200.
`In operation, the regulator circuit reduces the duty cycle of
`the power MOSFET when the voltage across resistor 235 20
`increases above a threshold. In this section, the output is in
`approximately constant voltage mode. The regulator circuit
`reduces the current limit of the power MOSFET when the
`voltage across resistor 235 decreases below a threshold. The
`current limit is reduced as a function of the voltage across 25
`resistor 235 to keep the output load current constant. Thus, the
`load current is proportional to the current limit of the power
`MOSFET in regulator 250. By keeping the current limit
`invariant to line voltage, the output load current would remain
`constant at all line voltages.
`FIG. 4 shows one embodiment of a power supply that has
`an approximately constant voltage and constant current char(cid:173)
`acteristic in accordance with the teachings of the present
`invention. The feedback information is provided to the regu(cid:173)
`lator 350 at its control pin. The current at the control pin is 35
`proportional to the voltage across resistor 335, which in turn
`is related to the output voltage. The regulator circuit reduces
`the duty cycle of the power MOSFET when the voltage across
`resistor 335 increases above a threshold. In this section, the
`output is in approximately constant voltage mode. The regu- 40
`lator circuit reduces the current limit of the power MOSFET
`when the voltage across resistor 335 decreases below a
`threshold. The current limit is reduced as a function of the
`voltage across resistor 335 to keep the output load current
`approximately constant. Thus, the load current is propor(cid:173)
`tional to the current limit of the power MOSFET in regulator
`350. By keeping the current limit substantially constant with
`line voltage, the output load current would remain substan(cid:173)
`tially constant at all line voltages.
`FIG. 5 is a diagram illustrating the typical relationship
`between the output current and output voltage of one embodi(cid:173)
`ment of a power supply in accordance with the teachings of
`the present invention. As can be seen in curve 400, the power
`supply utilizing the invention exhibits an approximately con(cid:173)
`stant output current and constant output voltage characteris(cid:173)
`tic. That is, as output current increases, the output voltage
`remains approximately constant until the output current
`reaches an output current threshold. As the output current
`approaches the output current threshold, the output voltage
`decreases as the output current remains approximately con(cid:173)
`stant over the drop in output voltage until a lower output
`voltage threshold is reached when the output current can
`reduce further as shown by the range of characteristics. It is
`appreciated that the constant output voltage and constant
`output current characteristics of the present invention are 65
`suitable for battery charger applications or the like.
`
`6
`In the foregoing detailed description, the method and appa(cid:173)
`ratus of the present invention has been described with refer(cid:173)
`ence to specific exemplary embodiments thereof. It will, how(cid:173)
`ever, be evident that various modifications and changes may
`be made thereto without departing from the broader spirit and
`scope of the present invention. The present specification and
`figures are accordingly to be regarded as illustrative rather
`than restrictive.
`What is claimed is:
`1. A power supply regulator, comprising:
`a comparator having a first input coupled to sense a voltage
`representative of a current flowing through a switch
`during an on time of the switch, the comparator having a
`second input coupled to receive a variable current limit
`threshold that increases during the on time of the switch;
`a feedback circuit coupled to receive a feedback signal
`representative of an output voltage at an output of a
`power supply; and
`a control circuit coupled to generate a control signal in
`response to an output of the comparator and in response
`to an output of the feedback circuit, the control signal to
`be coupled to a control terminal of the switch to control
`switching of the switch.
`2. The power supply regulator of claim 1 further compris(cid:173)
`ing an oscillator having a first output to generate a sawtooth
`waveform, wherein the variable current limit threshold is
`generated in response to the sawtooth waveform.
`3. The power supply regulator of claim 2 wherein the
`feedback circuit is coupled to receive the sawtooth waveform.
`4. The power supply regulator of claim 2 wherein the
`oscillator further has a second output to generate a maximum
`duty cycle signal, wherein the control circuit is coupled to
`generate the control signal further in response to the maxi(cid:173)
`mum duty cycle signal.
`5. The power supply regulator of claim 2 wherein the
`control circuit includes a latch to provide the control signal,
`wherein the latch includes a reset input coupled to the output
`of the comparator.
`6. The power supply regulator of claim 5 wherein the latch
`further includes a set input coupled to be responsive to a clock
`signal generated from a third output of the oscillator.
`7. The power supply regulator of claim 5 wherein the reset
`input of the latch is further coupled to be responsive to a
`maximum duty cycle signal from a second output of the
`45 oscillator.
`8. The power supply regulator of claim 5 wherein the
`feedback circuit comprises a feedback comparator coupled to
`receive the feedback signal and the sawtooth waveform,
`wherein the reset input of the latch is coupled to be responsive
`50 to an output of the feedback comparator.
`9. The power supply regulator of claim 1 wherein a duty
`cycle of the control signal is modulated in response to an
`output of the feedback circuit.
`10. The power supply ofregulator of claim 2 further com-
`55 prising a current minor coupled to the oscillator to receive the
`sawtooth waveform, wherein the variable current limit
`threshold is generated in response to the current mirror.
`11. The power supply regulator of claim 1 wherein the
`switching of the switch provides at the output of the power
`60 supply an output characteristic having an approximately con(cid:173)
`stant output current below an output voltage threshold.
`12. The power supply regulator of claim 11 wherein the
`approximately constant output current remains substantially
`constant at all line voltages.
`
`* * * * *
`
`ON SEMICONDUCTOR EXHIBIT 1001
`Page 10 of 11
`
`

`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`PATENT NO.
`APPLICATION NO.
`DATED
`INVENTOR(S)
`
`: 7,834,605 B2
`: 12/581054
`: November 16, 2010
`: Balakrishnan et al.
`
`Page 1of1
`
`It is certified that error appears in the above-identified patent and that said Letters Patent is hereby corrected as shown below:
`
`In Column 6, Line 55, delete "minor" and replace with -- mirror--.
`
`Signed and Sealed this
`Seventeenth Day of May, 2011
`
`~JJ:•·t-.~
`
`David J. Kappos
`Director of the United States Patent and Trademark Off