United States Patent
`
`[193
`
`[11] Patent Number:
`
`5,680,034
`
`Red]
`[45] Date of Patent: Oct. 21, 1997
`
`
`
`US005680034A
`
`[54] PWM CONTROLLER FOR RESONANT
`CONVERTERS
`
`[75]
`
`Inventor: Richard Red1,0nnens, Switzerland
`
`Primary Examiner—Peter S. Wong
`Assistant Examiner—Shawn Riley
`Attorney, Agent, or Finn—William E. Hein
`
`[57]
`
`ABSTRACT
`
`[73] Assignee: Toke, Inc, Japan
`
`[21] Appl. No.: 532,476
`
`[22] Filed:
`
`Sep. 22, 1995
`
`Int. Cl.6 .................................................... 11on 3/335
`[51]
`[52] U.S. Cl.
`................................. 323/21; 363/79; 363/97;
`323/235
`
`[58] Field of Search .................................. 363/16, 21, 79,
`363/80, 97, 131; 323/235
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,864,480
`5,387,822
`5,532,626
`
`9/1989 Melcher ...............
`363/21
`
`211995 Martin-Lopez eta]
`.. 323/280
`7/1996 Khayat ...................................... 327/53
`OFHER PUBLICATIONS
`
`Kwang—Hwa Liu and Fred C. Lee, “Zero—Voltage Switching
`Technique in DC/DC Converters,” IEEE, 1986, pp. 58—70.
`Richard Redl and Bela Molnar, “Class—E Resonant Regu-
`lated DC/DC Power Converters: Analysis of Operation, and
`Experimental Results at 1.5 MHZ,” IEEE PESC, 1983
`Record, pp. 50—60.
`N.O. Sokal and AD. Sokal, “Class E—A New Class of High
`Efficiency Tuned Single—Ended Switching Power Amplifi-
`ers,” [EEE Journal of Solid—State Circuits, pp. 168—176,
`Jun. 1975, vol. SC—lO, No. 3.
`
`A pulse width modulated controller controls a zero-voltage
`switching resonant power converter or inverter. The on time
`of the power switch (110) of the converter or inverter is
`varied by an error amplifier (280) such that the output
`voltage of the converter or inverter maintains proportionality
`to a reference voltage (290). The oif time is terminated by a
`switch-voltage detector (320) when the voltage across the
`power switch (110) drops below a threshold voltage (330)
`due to the natural resonance of the external resonating
`capacitor (120) and inductors (130 and 150). In the first two
`embodiments of the invention, a single timing capacitor
`(260) is employed both for determining the on time and the
`off time. In two other embodiments, two timing capacitors
`(262 and 264) are employed for separately determining the
`maximum allowed off time and the variable on time. A
`cycle-by-cycle current limit circuit comprising a current
`sensor (605), a comparator (610), and an R—S latch (620)
`may be added to the circuits representing each of the
`embodiments. By incorporating a soft start subcircuit (775)
`and an overlap detector (710, 715, 20, 725), protection
`against overdissipation of the power switch caused by loss
`of zero-voltage switching can also be implemented. The soft
`start subcircuit can also be triggered by a voltage detector
`(740, 745), which monitors the output voltage of the power
`converter or some other voltage within the system, such as
`the peak voltage across the power switch (110), to effec-
`tively implement overvoltage protection.
`
`9 Claims, 7 Drawing Sheets
`
`
`
`ON Semiconductor v. Power Integrations
`|PR2016-01600
`
`PI 2014
`
`1
`
`PI 2014
`ON Semiconductor v. Power Integrations
`IPR2016-01600
`
`

`

`US. Patent
`
`Oct. 21, 1997
`
`Sheet 1 of 7
`
`5,680,034
`
`
`
`FIGI
`
`(PRIOR ART)
`
`VOLTAGE ACROSS CAPACITOR 260
`
`/ ’
`
`/
`
`/
`
`/
`
`VOLTAGE AT OUTPUT 240
`
`T
`.1
`
`_,__._
`
`I‘TZ'I
`
`VOLTAGE ACROSS POWER SWITCH
`”0
`
`FIG 2A
`
`(PRIOR ART)
`
`FIGZB
`(PRIOR ART)
`
`FIGZC
`(PRIOR ART)
`
`VOLTAGE ACROSS POWER SWITCH IIO
`
`FIG.3A .
`
`(PRIOR ART)
`
`CURRENTIN POWER SWITCH no
`
`FIG. BB
`
`(PRDR ART)
`
`2
`
`

`

`US. Patent
`
`Oct. 21, 1997
`
`Sheet 2 Cf 7
`
`5,680,034
`
`VOLTAGE ACROSS POWER SWITCH IIO
`
`FI G. 4!)
`
`(PRIORART)
`
`CUR RENT IN POWER SWITCH IIO
`
`FIG. 4 B
`(PRIOR ART)
`
`280
`
`272
`
`250
`
`I90
`
`I30 I40
`
`+Vn . “'
`
`I
`
`K
`
`ZIO
`
`.
`
`I80
`
`I70
`
`310-—
`260 V2,v«
`+
`15290
`?
`
`FIG.5
`(PRIORART)
`
`+
`
`32035O—I
`3;
`SOHOT
`no-
`222
`240230
`.__
`
`v LTAGE ACROSS CAPACITOR 260
`
`FIG. 6A
`
`(PRIOR ART)
`
`VOLTAGE ATOUTPUT 240
`
`FI G. 68
`
`VOLTAGE ACROSS POVIER SWITCH IIO
`
`FIG. 6C
`(PRIOR ART)
`
`113*:
`
`I-rTM
`
`3
`
`

`

`US. Patent
`
`Oct. 21, 1997
`
`Sheet 3 of 7
`
`5,680,034
`
`
`
`F |G.7
`
`VOLTAGE ACROSS CAPACITOR 260
`
`W FIG. 8A
`
`VOLTAGE AT 0 OUTPUT OF R-S LATCH 470
`
`VOLTAGE ACROSS POW R SWITCH IIO
`
`FIG.8B
`
`FIG. 8C
`
`___ ZOO
`
`I60
`
`.
`
`4
`
`

`

`US. Patent
`
`Oct. 21, 1997
`
`Sheet 4 of 7
`
`5,680,034
`
`VOLTAGE ACROSS CAPACITOR 260
`
`W FIGJOA
`
`VOLTAGE AT Q OUTPUT OF {H LATCH 480
`
`F 10108
`
`VOLTAGE ACROSS POWER SWITCH 110
`
`FIG. 10C
`
`
`
`5
`
`

`

`US. Patent
`
`Oct. 21, 1997
`
`Sheet 5 of 7
`
`5,680,034
`
`VOLTAGE ACROSS CAPACITOR 264
`
`FIGIZ A
`
`VOLTAGE ACROSS CAPACITOR 262
`
`W FIG-'28
`
`VOLTAGE AT Q OUTPUT OF R-S LATCH 470
`
`VOLTAGE ACROSS POWER SWITCH HO
`
`FIGIZD
`
`V3
`
`400 522
`'IP ‘I'
`23338 '-
`
`540
`
`526
`
`445
`+ 9
`. (ET:
`430
`
`130
`‘9°-— ‘40
`I
`[50
`.
`
`‘
`I70
`
`180
`
`7
`
`290
`
`528 262 264
`
`7% £“ 330%—
`
`120
`
`-
`
`no _
`
`S 5
`460 485 470
`532
`
`$5435
`
`6
`
`

`

`US. Patent
`
`Oct. 21, 1997
`
`Sheet 6 of 7
`
`5,680,034
`
`VOLTAGE ACROSS CAPACITOR 264
`
`\
`
`>\
`
`/\
`
`/\
`
`FIGI4A
`
`VOLTAGE ACROSS CAPACITOR 262
`
`VOLTAGE ATQ OUTPUT OF R-S LATCH 470
`
`VOLTAGE ACROSS POWER SWITCH IIO
`
`FIG. |4C
`
`FIG.|4D
`
`
`
`
`410???
`4:2
`4:4 9 525
`u
`
`7
`
`

`

`US. Patent
`
`Oct. 21, 1997
`
`Sheet 7 of 7
`
`5,680,034
`
`VOLTAGE ACROSS CAPACITOR 260
`
`W FIG. ISA
`CURRENT IN POWER. WITCH HO
`
`FIGISB
`
`VOLTAGE AT OUTPUT OF GATE 630
`
`FIGIESC
`
`VOLTAGE ACROSS POWER SWITCH HO
`
`
`
`FIGIBD
`
`300
`
`[90— ISO I40
`_
`+VIn -
`
`150
`
`- I60
`
`ZIO
`°
`I80
`
`_
`
`170
`
`.
`
`?
`200
`
`
`
`
`
`0 TROLLER
`SUBCIRCUIT
`710
`
`- é
`
`I20
`
`740 70
`
`4-
`745-1
`
`u
`
`8
`
`

`

`5,680,034
`
`1
`PWM CONTROLLER FOR RESONANT
`CONVERTERS
`
`BACKGROUND AND SUMMARY OF THE
`INVENTION
`
`This invention relates to pulse width modulation control—
`lers used for controlling DC/DC power converters or
`DC/AC power inverters, operating in voltage resonance
`mode.
`
`Operating a DC/DC power converter or DC/AC power
`inverter, hereinafter collectively referred to as converters, in
`voltage resonance mode is a useful technique for eliminating
`the tum—on loss and reducing the turn—01f loss in the power
`switching transistor. In voltage resonance mode, a ringing
`voltage waveform is generated across the transistor during
`the time it is turned off. The ringing is achieved with the help
`of one or more resonating inductors and capacitors con-
`nected to the transistor. The ringing appears as a voltage
`swing, first up and then down, toward zero. The case when
`the voltage across the transistor is close to zero at the time
`it is turned on is known as zero voltage switching (ZVS). In
`ZVS converters, the turn—on loss is virtually absent. Also, the
`tum-01f loss is substantially reduced due to the presence of
`a resonating capacitor in parallel with the switch. ZVS is
`essential in high frequency converters for achieving high
`power conversion efficiency. In addition to increasing the
`efficiency, ZVS effectively reduces the electromagnetic
`interference, or EMI, generated by the converter. Many
`dilferent versions of ZVS DC/AC inverters and DC/DC
`converters have been described in the technical literature.
`Exemplary of the literature is Sokal et al., “Class E—a new
`class of high eficiency tuned single-ended switching power
`amplifiers,” IEEE Journal of Solid-State Circuits, June,
`1975, pp. 168—175; Redl et al., “Class E resonant regulated
`dc/dc power converters: analysis of operation, and emeri-
`mental results at 1.5 MHz ” PESC 1983 Record (IEEE
`Publication No. 86CH1877-0), pp. 50—60; and Lin et al.,
`“Zero-voltage switching technique in dc/dc converters,”
`PESC 1986 Record (IEE Publication No. 86CH2310-1), pp.
`58—70.
`
`Usually ZVS converters are controlled with a special type
`of pulse width modulation method, with variable on time
`and quasi—constant oilD time. The switch on time is varied
`such that the controlled parameter (normally the DC output
`voltage) stays constant in spite of changes in the input
`voltage or load current. In programmable power supplies,
`the controlled parameter follows a variable reference volt—
`age. The oif time of the switch is either constant or it varies
`slightly, depending on the actual control technique.
`FIG. 1 shows a flyback—type ZVS converter controlled
`with a prior art controller, such as the ML4815 integrated
`circuit manufactured by Micro linear Corporation. The
`ZVS flyback converter comprises a switching transistor 110,
`a resonant capacitor 120, a resonant inductor 130, a flyback
`transformer 140 having a primary winding 150 and a sec-
`ondary winding 160, an output rectifying diode 170, and an
`output filter capacitor 180. The converter is powered by a
`DC voltage source connected between a positive input
`terminal 190 and the negative input (ground) terminal 200.
`The load (not shown) is connected between the positive
`output terminal 210 and the negative output terminal 200. In
`this prior art circuit, the negative output terminal is the same
`as the negative input terminal.
`After the one-shot multivibrator 220 is triggered, it turns
`ofi the power switch 110 through an inverting buffer 230.
`The power switch is in the off or non—conducting state during
`
`10
`
`15
`
`2O
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`the whole duration T1 of the timed section of the operation
`of the one-shot multivibrator 220. The output 240 of that
`multivibrator is at a high level during the OE state. The
`transistor 250 is turned on by that high level, resulting in the
`voltage across the capacitor 260 being zero. When the
`timing of the one-shot multivibrator is completed, its output
`goes to low, leading to the tum-on of the power switch 110
`and the tln'n—ofi of transistor 250. The constant current
`
`source 270 now begins to charge capacitor 260, producing a
`linearly increasing voltage. The charging process is termi-
`nated when the voltage at the non-inverting input of com—
`parator 270 exceeds the voltage at the inverting input of the
`same comparator At that time, the output of the comparator
`goes high and triggers the one-shot. As a result, the output
`of the one-shot also goes high, the switch 110 is turned 01f,
`the transistor 250 is turned on, and another switching period
`cormnences.
`
`The threshold voltage of comparator 2'70 is set by an error
`amplifier 280. The output of that error amplifier is connected
`to the inverting input of comparator 270. The error amplifier
`receives two signals at
`its inverting and non-inverting
`inputs, a reference voltage 290, and the output voltage (the
`voltage at terminal 210) through a series impedance com-
`prising a resistor 300. To ensure stability of the system, a
`feedback impedance (capacitor 310) is connected between
`the output and the inverting input of the error amplifier 280.
`When the output voltage of the converter increases because
`the input voltage increased orthe load current decreased, for
`example, the voltage at the output of the error amplifier
`becomes smaller, leading to a reduction in the time required
`for the sawtooth voltage of capacitor 260 to reach that
`voltage. The end result is a decrease in the time the switch
`110 is turned on. The reduced on time of the switch leads to
`a reduction in the energy absorbed from the power source
`connected to the input terminals of the converter. Eventually,
`the system reaches an energy balance again, at the same
`output voltage.
`FIGS. 2A—C illustrate the characteristic waveforms of the
`prior art circuit of FIG. 1 in normal operation. FIG. 2A is a
`plot of the voltage across the capacitor 260. FIG. 2B is a plot
`of the voltage at the output 240 of the one—shot multivibrator.
`FIG. 2C is a plot of the voltage across the switch 110. As
`illustrated, the switch voltage swings back to zero and is
`clamped by the intrinsic body diode of the MOSFEI‘ device
`before the switch is turned on again by the one-shot multi-
`vibrator.
`The prior art circuit of FIG. 1 provides a variable on—time,
`constant off-time type of control. That type of control is
`suitable for the case when the time T2 of the ringing
`waveform, the time required to return to zero, is constant.
`Unfortunately, the time T2 is a function of many parameters,
`including the supply voltage, the load, and all of the com-
`ponent values and tolerances of the power circuit. In a
`practical case, time T2 may easily vary over a range of 2 to
`1. FIG. 3A illustrates the switch voltage waveform, and FIG.
`3B illustrates the switch current waveform when the otf time
`is too short and the switch is turned on early. FIG. 4A
`illustrates the switch voltage waveform, and FIG. 4B illus-
`trates the switch current waveform when the 011” time is too
`long and the switch is tinned on late. In both cases, there is
`substantial voltage across the switch at the turn—on instant,
`leading to a large current spike and excess dissipation in the
`switch. The rapid collapse of the switch voltage and the
`sharp current spike result in an increase in the EMI gener-
`ated by the converter, While the excess dissipation reduces
`the efliciency and causes reliability problems. All of those
`results are undesirable and should be avoided. The prema-
`
`9
`
`

`

`5,680,034
`
`3
`ture turn-on of the power switch in the case illustrated in
`FIGS. 3A—B can be easily avoided by setting the time T1 of
`the one-shot multivibrator to be longer than the longest
`expected time T2. In many applications it is, however, very
`difficult or even impossible to avoid the late turn-on of the
`power switch in the case illustrated in FIGS. 4A—B, espe
`cially if a large time T1 has been selected for the reason
`discussed above. Common, although not perfect, practice is
`to choose time T1 such that it yields ZVS under nominal
`conditions while ZVS is lost when time T2 is longer or
`substantially shorter than time T1. In many designs it is not
`possible. using the method illustrated in the prior art circuit
`of FIG. 1,
`to achieve ZVS over the desired range of
`operation.
`FIG. 5 illustrates the flyback ZVS converter controlled by
`a diiferent prior art controller, such as the UC1862 integrated
`circuit manufactured by Unitrode Integrated Circuits Cor-
`poration. This controller avoids the main drawback of the
`prior art controller of FIG. 1 and operates as follows. After
`it is triggered, the one-shot multivibrator 222 turns off the
`power switch 110 through the inverting bufi‘er 230. The
`power switch is turned on either after the time T2 of the
`one-shot multivibrator has expired or when the comparator
`320, sometimes known as a zero-voltage detecting or ZVD
`comparator, terminates the timing, whichever happens ear-
`lier. The inverting input of comparator 320 is connected to
`the drain of the power MOSFE'I‘ switch, and the non-
`inverting input is connected to a voltage source 330. The
`output of comparator 320 goes high and possibly terminates
`the timing when the voltage across the power switch
`becomes smaller than the voltage of the voltage source 330.
`e.g. smaller than 2 volts. Such a low voltage is considered
`sufficiently small that the increase in dissipation and EMI
`caused by the discharge of the resonant capacitor 120 is
`negligible. Although not illustrated in FIG. 5, the one-shot
`multivibrator 222 must have provisions for not responding
`to the output of comparator 320 immediately after being
`triggered, in order to avoid turning on the power switch
`immediately after it is turned off.
`The remainder of the prior art control circuit of FIG. 5
`includes a voltage controlled oscillator, or VCO, comprising
`a voltage controlled current source 272, a timing capacitor
`260 for the VCO, a hysteretic comparator 2‘72 with an upper
`threshold V2 and a lower threshold V1, and a discharge
`transistor 250. This circuit also includes an error amplifier
`280. a voltage reference source 290, an input resistance 300,
`and a feedback capacitor 310. When the output of the
`hysteretic comparator 272 is low, the transistor 250 is of,
`and the voltage controlled current source 22 charges the
`timing capacitor 260. Eventually,
`the capacitor voltage
`reaches the upper threshold V2, and the output of compara-
`tor 272 goes high. The low-to—high transition triggers the
`one-shot multivibrator 272 and also turns on transistor 250.
`That transistor starts to discharge capacitor 260. When the
`capacitor is discharged to the lower threshold V1, the output
`of the hysteretic comparator 272 goes low, transistor 250
`turns oil”, and the charging cycle of the capacitor begins
`again.
`The current of the voltage controlled current source 272
`is proportional to the output voltage of the error amplifier
`280. The non-inverting input of the error amplifier is con-
`nected to the output 210 of the converter, while the inverting
`input of the error amplifier is connected to the voltage
`reference source 290 through the resistor 300. A feedback
`capacitor 310 is connected between the output and the
`inverting input of the error amplifier to ensure system
`stability. When the output voltage of the converter increases
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`4s
`
`50
`
`55
`
`65
`
`4
`because the input voltage increased or the load current
`decreased, for example, the voltage at the output of the error
`amplifier becomes higher, leading to an increase in the
`current of the voltage controlled current source 272. The
`increase in that current leads to reduction in the period T4 of
`the VCO, and also a reduction in the on time of the power
`switch 110. The end result is a reduction in the energy
`absorbed from the power source connected to the input
`terminals of the converter. Eventually, the system reaches an
`energy balance again, while maintaining the same output
`voltage.
`FIGS. 6A—C illustrate the characteristic waveforms of the
`prior art circuit of FIG. 5. FIG. 6A is a waveform diagram
`of the voltage across the capacitor 260. FIG. 6B is a
`waveform diagram of the voltage at the output of the
`one—shot multivibrator 222. FIG. 6C is a waveform diagram
`of the voltage across the switch 110. It can be seen that as
`soon as the switch voltage swing back to zero, the switch is
`turned on again.
`By using the ZVD comparator, it is clearly possible to set
`the maximum timing value T2 of the one-shot multivibrator
`such that it accommodates the largest ringing time T1, while
`retaining near ZVS operation under most conditions.
`The prior art controller of FIG. 5 suifers two drawbacks.
`First, it requires two independent timing circuits, a VCO,
`and a one—shot multivibrator. Secondly, the minimum on
`time for the power switch is generated as the difference
`between the minimum period of the VCO and the ringing
`time T1 of the switch voltage waveform. Due to component
`tolerances and changes in the operating conditions, the
`minimum on time cannot be defined very accurately. This
`fact may lead to loss of regulation under light load and/or
`high input voltage conditions, or to loss of zero-voltage
`switching. Alternatively, highly accurate, and therefore more
`costly, timing and resonant components and/or individual
`adjustment of the timing parameters may be required.
`It is therefore an object of the present invention to provide
`a controller for resonant converters that ensures zero—voltage
`switching over a wide range of operating conditions and
`components tolerances.
`It is a further object of the present invention to provide a
`controller for resonant converters that does not require
`individual adjustment of the timing parameters.
`It is a further object of the present invention to provide a
`controller for resonant converters that is able to maintain
`regulation of the output voltage over a wide range of
`operating conditions and component tolerances.
`It is a further object of the present invention to provide a
`controller for resonant converters that includes additional
`protection against overload, against overdissipation of the
`power switch in case of loss of zero-voltage switching, and
`against overvoltage across the switching device or across the
`load.
`
`It is yet another object of the present invention to provide
`a controller for resonant converters that is suitable for
`realization with monolithic integrated circuit technology.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a schematic circuit diagram of a ZVS flyback
`converter and a prior art controller of the fixed off-time and
`variable on—time type.
`FIGS. 2A—C are waveform diagrams showing character-
`istic waveforms exhibited by the prior art circuit of FIG. 1
`during normal operation.
`FIGS. 3A—B are waveform diagrams showing waveforms
`of the switch voltage and current exhibited by the circuit of
`FIG. 1 when the off time is too short.
`
`10
`
`10
`
`

`

`5,680,034
`
`5
`FIGS. 4A—B are waveform diagrams showing waveforms
`of the switch voltage and current exhibited by the circuit of
`FIG. 1 when the oilc time is too long.
`FIG. 5 is a schematic circuit diagram of a ZVS flyback
`converter and a prior art controller of the adaptive off—time
`and variable frequency type.
`FIGS. 6A—C are waveform diagrams showing character—
`istic waveforms exhibited by the prior art circuit of FIG. 5.
`FIG. 7 is a schematic circuit diagram of a ZVS flyback
`converter and a controller therefor in accordance with a first
`embodiment of the present invention.
`FIGS. 8A—C are waveform diagrams showing character-
`istic waveforms exhibited by the circuit of FIG. 7.
`FIG. 9 is a schematic circuit diagram of a ZVS flyback
`converter and a controller therefor in accordance with a
`second embodiment of the present invention.
`FIGS. 10A—C are waveform diagrams showing charac-
`teristic waveforms exhibited by the circuit of FIG. 9.
`FIG. 11 is a schematic circuit diagram of a ZVS flyback
`converter and a controller therefor in accordance with a third
`embodiment of the present invention.
`FIGS. 12A—D are waveform diagrams showing charac-
`teristic waveforms exhibited by the circuit of FIG. 11.
`FIG. 13 is a schematic circuit diagram of a ZVS flyback
`converter and a controller therefor in accordance with a
`fourth embodiment of the present invention.
`FIGS. 14A—D are waveform diagrams showing charac-
`teristic waveforms exhibited by the circuit of FIG. 13.
`FIG. 15 is a schematic circuit diagram illustrating imple-
`mentation of an overload protection circuitry in the circuit of
`FIG. 7.
`
`FIGS. 16A—D are waveform diagrams showing charac-
`teristics waveforms exhibited by the circuit of FIG. 15.
`FIG. 17 is a schematic circuit diagram illustrating imple-
`mentation of overdissipation and overvoltage protection
`circuitry in the circuit of FIG. 7.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Referring now to FIG. 7, there is shown a schematic
`circuit diagram of a ZVS flyback converter and a controller
`therefor in accordance with a first embodiment of the present
`invention. A power switch 110 is controlled by an R—S latch
`470. When latch 470 is set, the power switch 110 is turned
`on. When the latch 470 is reset, the power switch 110 is
`turned off. Latch 470 is set by a comparator 460 and is reset
`by another comparator 465. The output of comparator 460
`goes high when the voltage of a timing capacitor 260
`exceeds a threshold of comparator 460. That threshold, 3
`volts, for example, is set by a voltage source 435. The output
`of comparator 465 goes high when the voltage of the timing
`capacitor 260 decreases below the threshold (e.g. 1 volt) of
`the comparator 465, set by a voltage source 40. During the
`time that the power switch 110 is turned off, the timing
`capacitor 260 is charged by a current established in the
`resistor 420 and is mirrored by a current mirror comprising
`a pair of PNP transistors 422, 424. The emitters of transistors
`422, 424 are connected to a bus 400 with a voltage V3 (e.g.
`4 volts) between the buse and ground When the output of a
`two-input AND gate 455 goes high, the voltage controlled
`current source 450 is enabled and the charging current
`increases by the addition of the current flowing in that
`current source. The additional current is normally signifi-
`cantly higher by at least a factor of three than the current
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`flowing in transistor 424. This leads to a rapid increase in the
`voltage of the timing capacitor 260 and a quick termination
`of the off time of the power switch 110. The output of the
`AND gate 455 goes high when two conditions are met
`simultaneously: (1) the voltage across capacitor 260 exceed
`the voltage (e.g. 1.5 volts) of voltage source 430; and (2) the
`voltage across switch 110 decreases below the voltage of
`voltage source 330. When the first condition is met, the
`output of a comparator 445 goes high. When the second
`condition is met, the output of a comparator 320 goes high.
`The first condition is required to avoid tum—on of the power
`switch 110 immediately after tum-off. The second condition
`is required to ensure zero-voltage switching by enabling the
`turn-on of the power switch 110 as soon as the voltage across
`it swings back to nearly zero.
`Timing capacitor 260 is discharged by the current flowing
`in an output transistor 414 of the current mirror system
`comprising transistors 402, 404, 412, and 414. The input
`current of the current mirror system is established by a
`resistor 406. Resistor 406 is connected between the output of
`an error amplifier 280 and an input of the current mirror
`system The reference voltage of the error amplifier is that of
`a voltage source 290. An input resistor 300 and a feedback
`capacitor 310 are required for ensuring stability of the
`complete feedback loop.
`‘
`The output of the error amplifier becomes lower when the
`output voltage of the converter becomes higher, leading to
`an increase in the current flowing in resistor 406. The
`increased current causes a reduction in the discharge time of
`capacitor 260, and also in the on time of switch 110. The end
`result is regulation of the output voltage of the converter.
`During the 011” time of switch 110, transistor 410 is held
`on through a resistor 408, diverting the input current of the
`current mirror that comprises transistors 412 and 414. Thus,
`no discharge cmrent is available for timing capacitor 260
`during the off time. Similarly, dining the on time of switch
`110, transistor 418 is held on through a resistor 416, divert—
`ing the input current of the current mirror that comprises
`transistors 42 and 424. Thus, no discharge current is
`available for timing capacitor 260 during the on time.
`Referring now to FIG. 8A-C, there are shown character-
`istic waveforms exhibited by the circuit of FIG. 7. FIG. 8A
`is a waveform diagram of the voltage across the timing
`capacitor 260. FIG. 8B is a waveform diagram of the voltage
`at a Q output of R-S latch 470. FIG. 8C is a waveform
`diagram of the voltage across the switch 110. As is evident
`from these waveform diagrams, all of the drawbacks of the
`prior art circuits discussed above are eliminated. In this
`circuit, ZVS is ensured by a zero-voltage detector that
`quickly terminates the off time of the power switch 110. A
`single firming circuit is used to perform the two functions of
`setting the maximum off time and setting the variable on
`time. There is practically no interaction between the on-time
`setting and the off-time setting sections of the controller.
`Referring now to FIG. 9, there is shown a schematic
`circuit diagram of a ZVS flyback converter and a controller
`therefor in accordance with a second embodiment of the
`present invention. The difference between this circuit and
`the circuit of FIG. 7 is that in the circuit of FIG. 9 the of
`timing is not terminated rapidly upon detecting the zero—
`voltage condition of the switch 110. A turn-on signal is
`generated for the power switch when the following condi-
`tions are met: the output of comparator 445 is high, indi-
`cating that the timing signal passed the lower threshold set
`by voltage source 430 AND the output of the ZVD com-
`parator 320 is high, indicating that the voltage across the
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`power switch is low OR the output of comparator 460 is
`high, indicating that the maximum allowed 011‘ time has
`expired. The required logic functions are accomplished by a
`two-inputAND gate 455 and a two—input OR gate 485. The
`turn—on signal sets the R—S latch 480. If the output of the
`AND gate 455 sets the latch 480. the timing waveform of the
`voltage across capacitor 460 continues to increase at the
`same rate, all the way to the threshold of comparator 460.
`When that threshold is reached, another R—S latch 475 is set.
`The inverted (Q bar) output of R—S latch 475 disables the
`charging current mirror comprising transistors 422, 424 and
`enables the discharging current mirror comprising transis-
`tors 412, 414.
`Referring now to FIGS. 10A—C, there are shown wave-
`form diagrams illustrating characteristic waveforms exhib-
`ited by the circuit of FIG. 9. FIG. 10A is a waveform
`diagram of the voltage across the capacitor 260. FIG. 10B is
`a waveform diagram of the voltage at the Q output of the R—S
`latch 480. FIG. 10C is a waveform diagram of the voltage
`across the switch 110.
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`The practical advantage of the embodiment of FIG. 9 over
`that shown in FIG. 7 is that only negligible overshoot
`develops in the timing voltage across capacitor 260 when it
`reaches the upper threshold set by voltage source 435. The
`overshoot is not desirable because it leads to an increase in
`the subsequent on time and (2) requires an increased voltage
`V3 on bus 400. In low voltage applications even a small
`overshoot on the order of 0.5 volts should be avoided.
`
`The disadvantage of the embodiment of FIG. 9 over that
`of FIG. 7 is an increase in the value of the minimum
`achievable on time. In the circuit of FIG. 7, the minimum
`achievable on time is equal to the product of the timing
`capacitance and the diiference between the upper and lower
`threshold divided by the maximum discharge current. In the
`circuit of FIG. 9. an additional term appears. That additional
`term is the difference between the maximum off time and the
`actual otf time of the power switch. The maximum off time
`is equal
`to the timing capacitance times the ditference
`between the upper and lower threshold divided by the set
`charge current. It should be noted that although the increase
`in the minimum achievable on time reduces the control
`range of the converter, in many designs a reduced control
`range is acceptable.
`The controllers of FIGS. 7 and 9 are in many respects
`better than the prior art controllers discuss in detail herein—
`above and are quite suitable for a number of designs. Both
`circuits have, however. minor deficiencies which might
`prevent their usage in some demanding applications. The
`third preferred embodiment of the present invention, shown
`in FIG. 11. eliminates those minor deficiencies and is
`considered the best circuit for overall use.
`
`Referring now to FIG. 11, the off time setting and the on
`time setting are completely separated. The maximum 01f
`time is generated by way of several circuit components and
`parameters. These include the current at the output of the
`current mirror formed by transistors 522 and 526, a capacitor
`264. a reference source 435, and a comparator 460. The
`input current of the current mirror is set by a resistor 520.
`The power switch 110 is turned on when either the maxi-
`mum off time is reached or the AND combination of the
`output of the EVD comparator 320 and comparator 445 goes
`high. The OR function is accomplished by a gate 485 and the
`AND function is accomplished by a gate 455.
`The on time is generated by way of several circuit
`components and parameters. These include the current at the
`output of the current mirror formed by transistors 522 and
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`52.4, a capacitor 262, the output voltage of an error amplifier
`280, and a comparator 467. When the output of comparator
`467 goes high, indicating that the voltage across capacitor
`262 has reached the threshold voltage set by the output of
`error amplifier 280, an R-S latch 470 is reset and its output
`goes low and turns off the power switch 110.
`During the off time, a transistor 528 is turned on through
`a resistor 532, thereby maintaining the voltage across an
`on—time—setting capacitor 262 near zero. During the on time,
`a transistor 30 is turned on through a resistor 34, thereby
`maintaining the voltage across an oif-time—setting capacitor
`264 near zero.
`Regulation of the output voltage of the converter is
`achieved by an error amplifier 280 and associated compo-
`nents comprising an input resistor 300. a feedback capacitor
`310, and a reference voltage source 290. For example, when
`the output voltage of the converter is too high, the output
`voltage of the error amplifier 280 decreases, leading to a
`reduction of the on time and eventual stabilization of the
`output voltage of the converter.
`Referring now to FIGS. 12A-D, there are shown wave-
`form diagrams illustrating characteristic waveforms exhib-
`ited by the circuit of FIG. 11. FIG. 12A is a waveform
`diagram of the voltage across capacitor 264. FIG. 12B is a
`waveform diagram of the voltage across capacitor 262. FIG.
`12C is a waveform diagram of the voltage at the Q output of
`the R—S latch 470. FIG. 12D is a waveform diagram of the
`voltage across the switch 110.
`Referring now to FIG. 13, there is s