United States Patent [19]
`Bench et a1.
`
`[11]
`[45]
`
`4,156,867
`_ May 29, 1979
`
`[54] DATA COMMUNICATION SYSTEM WITH
`RANDOM AND BURST ERROR
`PROTECTION AND CORRECTION
`[75] Inventors: Stephen M. Bench, Lake Zurich;
`William R. Dirkes, Mundelein;
`Manohar A. Joglekar, Elk Grove
`Village; James C. Secora, Hoffman
`Estates; Michael A. Stepien,
`Schaumburg, all of I11.
`[73] Assignee: Motorola, Inc., Schaumburg, Ill.
`[21] Appl. No.: 830,531
`'
`[22] Filed:
`Sep. 6, 1977
`[51] Int. C1.2 ............................................ .. G06F 11/12
`[52] US. Cl. .............
`............. .. 340/1461 AL
`[58] Field of Search ................ .. 340/ 146.1, 146.1 AL,
`340/1461 D, 146.1 AG, 146.1 C; 325/163, 41
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`6/1962 Kahn ........................ .. 340/ 146.1 AL
`3,037,697
`2/ 1966 Marko
`340/ 146.1 AL
`3,234,364
`l/ 1969
`Heller
`340/ 146.1 AL
`3,423,729
`2/1971 McBride ................. .. 340/ 146.1 D
`3,560,924
`8/1973
`Nickolas et a1.
`.... .. 340/ 146.1 D
`3,753,228
`3,930,121 12/1975 Mathiesen .......................... .. 325/163
`
`OTHER PUBLICATIONS
`Brodd and Donnan, Cyclic Redundancy Check for
`
`Variable Bit Code Widths, IBM Technical Disclosure
`Bulletin, vol. 17, No. 6, Nov. 1974, pp. 1708-1709.
`
`Primary Examiner--Charles E. Atkinson I
`Attorney, Agent, or Firm—-Rolland R. Hackbart; James
`W. Gillman
`
`ABsTRAcr
`[s7]
`A data communication system for use in the control and
`monitoring of mobile stations, for example, in a bus
`monitoring system, from a central station over a com
`munication channel carrying both data and voice infor
`mation. Information is encoded into digital messages
`having a start code followed by one or more data
`blocks. The start code identifies the beginning of the
`data block that follows and enables synchronization of
`clock circuitry to the received data frequency. The data
`blocks have N digital words with M binary bits where
`one word is a parity word and N-l words are data
`words. Each of the data words has a data portion and
`parity portion coded for correction of at least one error.
`Reliability is enhanced by a data detector which dis
`criminates between data and noise or voice to provide
`an indication of the presence of data. In transmitting the
`digital messages, the bits of the N words in each data
`block are interleaved to provide protection against
`error bursts.
`
`8 Claims, 12 Drawing Figures
`
`(22 1
`FIXED STATION
`45
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`
`Microsoft Ex. 1018
`Page 1 of 12
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`

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`U.S. Patent May 29, 1979
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`Sheet '1 of 5
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`4,156,867
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`N. .IIE
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`Microsoft Ex. 1018
`Page 2 of 12
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`

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`U.S. Patent May 29, 1979
`
`Sheet 2 015
`
`4,156,867
`
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`Microsoft Ex. 1018
`Page 3 of 12
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`

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`U.S. Patent May 29, 1979
`
`Sheet 3 of5
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`4,156,867
`
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`Microsoft Ex. 1018
`Page 4 of 12
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`

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`U.S. Patent May 29, 1979
`
`Sheet 4 of5
`
`4,156,867
`
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`
`Microsoft Ex. 1018
`Page 5 of 12
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`

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`US. Patent May 29, 1979
`
`Sheet 5 of 5
`
`4,156,867
`
`300
`
`1 START 1
`
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`
`Microsoft Ex. 1018
`Page 6 of 12
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`

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`1
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`' 4,156,867
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`25
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`40
`
`DATA COMMUNICATION. SYSTEM ,WITH
`RANDOM AND BURST ERROR PROTECTION
`'
`AND CORRECTION
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates to a data communication sys
`tem, and, more particularly, to an improved method and
`apparatus for a data communication system utilizing a
`coded digital signalling. system. .
`.
`2. Description of the Prior Art
`In order to expand the capacityof a communication
`system, one may add more communication channels to
`the system or increase the amount of information car
`ried on each of the existing communication channels.
`Since the number of communication channels is limited
`for most systems, it has been more practical to increase
`the amount of information carried on each communica
`tion channel by various methods, for example, multi
`plexing and digital techniques. The communication
`systems using these concentrating techniques must be
`reliable to insure that the information is not lost. The
`reliability of communication systems using digital mes
`sages may be enhanced by using such techniques as
`error correcting codes and multiple transmissions of the
`digital messages. However, prior art communication
`systems, such as radio communication systems, are still
`prone to burst errors and have yet to realize optimal
`usage of error correcting and detecting techniques in a '
`bandwith limited system. This is especially the case
`with radio communication systems where interference
`and fading must be accommodated.
`For the foregoing and other shortcomings and prob
`lems, there has been a long felt need for an improved
`data communication system.
`I,_
`SUMMARY OF THE INVENTIO
`Accordingly, it is a general object of the present
`invention to provide an improved data communication
`
`system.
`
`-
`
`_
`
`It a further object of the present invention to provide
`a more reliable data communication system.
`It is still a further object of the present invention to
`provide an improved data communication system that
`provides random and burst error protection and correc
`
`45
`
`tion.
`
`‘
`
`,
`
`It is yet a further object of the present invention to
`provide an improved data communication system ‘that
`can recognize the presence of noise or voice to provide
`additonal protection against the reception of invalid
`digital messages.
`In accordance with the present invention, the afore
`mentioned problems and shortcomings of the prior art
`are overcome and the stated and other objects are at
`tained by an improved digital data communication sys
`tem that includes a central station and a plurality of
`mobile stations. The system may further include one or
`more ?xed stations for providing relevant information,
`60
`such as geographical location information, to the mobile
`stations. Communication channels of the system may
`carry voice between the operator of the mobile station
`and the dispatcher at the central station without affect
`ing the reliability of the digital message transmissions.
`In accordance with a feature of the present invention,
`digital messages are transmitted after a start code of a
`predetermined nature. The digital message is formated
`into at least one data block having N digital words, each
`
`65
`
`.word having M binary bits, where M and N are integer
`' numbers. The start code has a predetermined number of
`binary bits, for example thirty-‘two, organized in a
`highly correlatable pattern for de?ning the beginning of
`the ?rst data block of the digital message. The N digital
`words of a data block include at least one parity word
`and N-- 1 data words..Each of the data words has a data
`portion and a parity portion coded for correction of at
`least one bit which is in error in the data portion. For
`example, the parity portion can -.be coded according to a
`Hamming code. The parity word has M binary bits
`which are each derived according to a predetermined
`format from the group of corresponding bits taken from
`the N-l data words. The parity word may be chosen
`so that it does not include long strings of logical zero or
`logical one bits. This is bene?cial in limiting the low
`frequency content of the digital message and providing
`bit transitions to enable synchronization to the data
`frequency.
`Additional features, objects, and advantages of the
`data communication system in accordance with the
`present invention will be more clearly apprehended
`from the following detailed description together with
`the accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 illustrates a data communication system in
`accordance with the present invention.
`FIG. 2 illustrates a typical transmission of data hav
`ing a start code followed by three data blocks.
`FIG. 3 illustrates a 7 X 7 digital data block which has
`24 data bits, numbered D1 through D24; 18 parity bits,
`numbered P1 through P18; and 7 vertical parity bits,
`numbered VPl through VP7.
`FIGS. 4A and 4B illustrate partial waveforms of a
`digital message where a frequency-shift keying (FSK)
`waveform is shown in FIG. 4A and the corresponding
`data waveform is shown in FIG. 4B.
`FIG. 5 illustrates a block diagram of a modem for the
`data communication system of the .present invention.
`FIG. 6 illustrates a graph of the error voltage result
`ing from data and noise inputs to the phase locked loop
`for the modem of FIG. 5.
`FIG. 7 illustrates an embodiment of the data-operat
`ed-squelch circuitry for the modem of FIG. 5.
`FIG. 8 illustrates an embodiment of the data clock
`circuitry for the modem of FIG. 5.
`FIG. 9 illustrates logical state assignments which may
`be utilized for the parity portion of the digital messages.
`FIG. 10 illustrates a ?ow chart of a subprogram of
`the stored program in the modem of FIG. 5 for receiv
`ing digital messages.
`FIG. 11 illustrates a ?ow chart of a subprogram of
`the stored program in the modem of FIG. 5 for transi
`mitting digital messages.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`Referring to FIG. 1, a data communication system
`embodying the present invention is illustrated where
`information is communicated by digital messages be
`tween a central station 20, a mobile station 21 and a
`?xed station 22 over radio channels. The exemplary
`embodiment is a computer-controlled vehicle monitor
`ing system which is described in U.S. Pat. No.
`3,644,883, entitled “Automatic Vehicle Monitoring,
`Identi?cation, Location, Alarm and Voice Communica
`tion System,” by W. M. Borman et al. In this system, the
`
`Microsoft Ex. 1018
`Page 7 of 12
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`

`
`4
`The improved data communication system of the
`present invention utilizes a signalling system which
`enhances the reliability of the aforementioned vehicle
`monitoring system and other prior art systems. Refer
`5 ring to FIG. 2, the digital message is preceded by a start
`code 90 after which one or more data blocks 91, 92 and
`93 are transmitted. The start code is preferably a corre
`latable pattern of binary bits that de?nes the beginning
`of the ?rst data block 91 and enables synchronization to
`the data frequency. Start codes 90 having these charac
`teristics are described in a copending application, Ser.
`No. 830,951, entitled “Method and Apparatus for the
`Synchronization of Data Bit Streams,” by John En,
`?led on Sept. 6, 1977 and assigned to same assignee as
`5 the present application. The start code selected from the
`above referenced application for use in the data commu
`nication system of the present invention is the 32 bit
`code with the following bit sequence:
`
`0000101010101 l0l00l0l00l 100] ml l.
`
`The particular data rate utilized in the data communica
`tion system of the present invention may be any practi
`cal frequency selected to meet the system requirements
`and speci?cations.
`The data blocks 91, 92 and 93 are organized into a 7
`X 7 block of binary bits, although any practical number
`of words and binary bits can be utilized to practice the
`present invention. In FIG. 3, the 7 X 7 data block 80
`contains 24 data bits, numbered D1 through D24; 18
`parity bits numbered P1 through P18; and 7 parity bits
`hereinafter designated vertical parity bits, numbered
`VPl through VP7.
`A digital word is a horizontal group of bits, for exam
`ple, D1 through D4 and P1 through P3 being the ?rst
`digital word. Thus, each word consists of a four-bit data
`portion and a three-bit parity portion. The parity por
`tion is encoded according to a Hamming code for cor
`recting one error in the corresponding data portion of
`the digital word. The particular parity bits associated
`with the data portions of the digital words are listed in
`FIG. 9, where each digital word is at least a Hamming
`distance of three from the other digital words.
`The parity bits of the digital words are selected to
`satisfy the matrix equation HT = 0, where H is a rectan
`gular 3 X 7 matrix and T is a l X 7 column matrix made
`up of a digital word from the data block, for example
`the ?rst digital word of the data block 80 in FIG. 3
`would be D1, D2, D3, D4, P1, P2, P3. For the H matrix
`shown below, the following equations result for the ?rst
`digital word where the + sign indicates modulo 2 addi
`tion.
`
`(II
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`LII
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`4,156,867
`3
`central station 20 is a command and control station that.
`is operated by a dispatcher, the mobile station 21 is a bus
`and the ?xed station 22 is a signpost having a predeter
`mined location code. The bus stores the signpost loca
`tion code when it passes in close proximity to the partic
`ular signpost, and relays that information to the com
`mand and control station for providing the dispatcher
`with the approximate location of the bus along its route
`of travel. The bus also communicates alarm, status and
`additional information to the command and control 1
`station over the communication channel. Voice com
`munications may also take place between the driver of
`the bus and the dispatcher. Information is communi
`cated between the bus and the command and control
`station by digital messages, as will be explained herein
`after. Details of the vehicle location system are also
`described in the Motorola, Inc. instruction manual enti
`tled, “METROCOM Transit Data System and Loca
`tion System,” published by Motorola Service Publica
`tions, 1976, Schaumburg, Illinois.
`The above referenced vehicle monitoring system
`communicates digital messages between the central
`station 20, the mobile station 21, and the ?xed station 22
`which are coded according to audio frequency-shift
`keying (AFSK) at a frequency of 500 bits per second
`(500 baud). The information in the digital message is
`repeated twice and the repetitions are compared at the
`receiving station for error detection purposes. How
`ever, no error correction or burst error protection is
`provided.
`In FIG. 1, the central station 20 is made up of a radio
`tranceiver 30, a modem 31, a voice unit 34, and a com
`puter, or microcomputer 32 and its associated peripher
`als, data storage unit 33, printer 35, display 36 and key
`board 37. A dispatcher enters information by way of the
`keyboard 37. The entered information is converted to a
`digital message by the computer 32, coded by the
`modem 31 and transmitted over a radio channel 47 to
`the mobile station 21 by the transceiver 30. Both trans
`mitted and received digital messages are visually dis
`played to the dispatcher in the display 36, which may be
`any of a number of displays including alphabetic, graph
`ical, or digital displays.
`The mobile station 21 includes a modem 40, a trans
`ceiver 42, a location receiver 41 and a control head 43.
`An operator of the mobile station 21 can talk to the
`dispatcher by means of the control head 43. Digital
`messages are coded by the modem 40 and transmitted
`over the radio channel 47 by the transceiver 42 both
`automatically and in response to operator directives
`entered into the control head 43. The location receiver
`41 receives a predetermined location code from a ?xed
`station 21 over radio channel 48, which is coded by the
`modem 40 for transmission to the central station 20.
`The ?xed station 22 includes a radio transmitter 45
`and a location-code encoder 46. Fixed stations 22 are
`located along the route of the mobile station 21 and are
`each uniquely assigned a predetermined location code
`for identifying the particular ?xed station 22. The ?xed
`station 22 continuously transmits its predetermined lo
`cation code on a location radio channel 48 which is
`different from the data radio channel 47. When a mobile
`station 21 comes in close proximity to the ?xed station
`22, it receives the predetermined location code from the
`particular ?xed station 22 and relays it to the central
`station 20 automatically. Thus, the position of the mo
`bile station 21 along its route of travel can be deter
`mined by the central station 20.
`
`0
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`D Pl
`
`If HT ;& 0, then a single bit error is assumed to be
`present and an error correction algorithm may be per
`formed to correct the erroneous bit.
`The matrix organization of the data words is readily
`adapted to processing by a computer or microcom
`
`Microsoft Ex. 1018
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`' 4.156.867
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`5
`puter. In the data communication system of the present
`invention, the receiving and transmitting of the digital
`messages is performed by a microcomputer having a
`stored program,_ as .will be explained hereinafter. '
`The bits of the. vertical _ parity word, which Eare
`VP1-VP7 (see FIG. 3), are Y’ eachv derived fromthe
`group of six bits'inits respective column, forexample,
`VP1 is derived from D1, ‘D5, D9,- D13, D17tand D21.
`The vertical parity bits are derived according to a pre
`determined format such that none of the.~columns of bits
`contain all zeros or all ones. For instance, the vertical
`parity bit can be selected to bea logical one’; when all
`other bits in its respective column are logical zeros, and
`for all other conditions the vertical parity bit is a logical
`zero. By selecting the ‘vertical parity bits in this manner,
`the low frequency content of the transmitted data block
`is reduced, which allows a corresponding reduction in
`the bandwith of themodem which decreases low fre
`quency noise interference. In addition, the ‘vertical par
`ity bits enable the detection of a double error in at least
`one of the digital words. The vertical parity bits ob
`tained in the aforementioned manner forms a parity
`word for the system.
`>
`~
`The digital message,‘ transmitted‘ over the communi
`cation channel 'as shown in FIG. 2, is interleaved during
`transmission to provide burst error protection. Inter
`leaving of the digital message is accomplished by trans
`mitting the columns of binary bits (see FIG. 3) sequen
`tially, instead of transmitting one entire digital word
`after another. Forexample, the data block 80 of FIG. 3
`would be transmitted in the following’ sequence; D1,
`D5, D9, D13, D17, D21, VP1, D2,.D6, etc. Interleaving
`the bits of the digital message results in a maximum fade
`margin of 7 consecutive erroneous bits. If 7 consecutive
`bits are in error, then each data word has at most one bit
`in error which is correctable by use of ’ the Hamming
`
`20
`
`25
`
`6
`with the frequency of operation of the microcomputer
`in the modem.
`I
`_
`Referring to FIG. 5, a block diagram illustrates more
`clearly an embodiment of aimodem for the data commu
`nication system of the present invention. The MSK
`input data is ?rst connected to the input ?lter shown 50.
`The purpose of this ?lter is to provide some pre-?ltering
`action to limit the input bandwith to only that occupied
`by the MSK input data and to reject noise falling out
`side this band. For example, it may be comprised of four
`poles of high frequency at 1800 Hz and two poles of low
`frequency roll off, ‘whereby providing an input ?lter
`which is generally a bandpass ?lter occupying the band
`v800 Hz to 1700 Hz. The output of the input ?lter 50 is
`then ampli?ed and limited by the limiter 51. The pur
`pose of the limiter 51 is to provide a square wave signal
`to the phase comparator 52 of the phase locked loop 70.
`Therefore, the MSK input data is translated into zero
`crossing information by the limiter 51, which is then
`processed by the phase locked loop 70.
`The phase locked loop 70 includes a phase compara
`tor 52, a loop ?lter 53, a voltage controlled oscillator
`(VCO) 54 and a divider 55. The phase comparator 52
`compares the incoming phase of the limited MSK input
`data to that of the VCO 54 through the divider 55. It
`then provides an output voltage to the. loop ?lter 53
`indicating that the frequency of the VCO 54 is either
`too high or too low for correcting the frequency of the
`voltage control oscillator.
`The loop ?lter 53 is tailored to reject noise which
`may be introduced by either the phase locked loop 70
`itself or the MSK input data through a noisy signal. The
`bandwidth of the loop ?lter 53 is therefore controlled to
`be only that necessary for the data, which is approxi
`mately 500 Hz for MSK input data at 1000 baud. The
`loop ?lter 53 not only limits the bandwidth in the phase
`locked loop 70, but also maintains the stability of the
`phase locked loop 70. The error voltage 73 from the
`loop ?lter 53 is then fed into the VCO 54. The output of
`the VCO 54 is approximately sixteen, times the fre
`quency of the MSK input data and is fed into a divider
`55 for dividing the VCO by sixteen. Operating the VCO
`54 at sixteen times the frequency of the MSK input data
`provides better protection against noise and allows
`improved operation of the phase locked loop 70.
`The error voltage 73 from the loop ?lter 53 contains
`the recovered data together with high frequency com
`ponents. The error voltage 73 is coupled to the data
`operated-squelch circuitry 71 and the data ?lter 60. The
`data ?lter 60 is a low pass ?lter for removing the input
`data from the error voltage 73, where the data is con
`tained substantially within the frequency band from 0
`Hz to 500 Hz. The data ?lter 60 is optimized to closely
`match the characteristics of input data carried on the
`error voltage 73.
`r
`p
`The data limiter 61 then provides mark and space (see
`FIGS. 4A and 4B) information by a conventional bit
`slicing process. If the input data is more generally of
`mark frequency, the output of the data limiter 61 is a
`logical one. If the input data is generally more of a space
`frequecy, the output of the data limiter 61 is a logical
`zero. The output of the data limiter 61 is the recovered
`input data which is ‘coupled to the data clock circuitry
`. 72 and the microcomputer 64. The data clock circuitry
`72 utilizes the transitions of the recovered input data
`65
`from the data limiter 61.»for synchronizing to the input
`data frequency.’ Thedata sync pulse 62 ‘provides a sync
`pulse for each transition of the recovered ‘input data.
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`code.
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`The digital messages are transmitted over the com
`munication channel by means of coherent audio fre
`quency-shift keying. Coherent operation is character
`ized by transmission of audio tones which are rationally
`related to each other, 'with transmission of each bit
`initiated at a constant and‘ de?ned phase relationship.
`Further, the digital messages are transmitted by means
`of minimum shift keying (MSK). Minimum shift keying
`operation is characterized by the audio " tone for the
`logical one state being equal to the data frequency and
`the audio tone. representing the’logical zero state being
`equal to 15 times the data frequency. Each data bit starts
`and ends on a zero crossing of the respective tones. In
`the preferred embodiment, the tones selected are 1000
`Hz for a markand v1500 Hz vfor a space. A mark corre
`sponds to a data bit having a logical one state and a
`space correspondsto a data bit having a logical zero
`state. Referring to FIGS. 4a and 4b,.a portion of a digi
`tal message is shown where FIG, 4a is va waveform of
`the MSK data and FIG. 4b is, a waveform the demod
`
`ulated data.
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`By using MSK with, tonesof 1000 Hz and ‘1500 Hz,
`the spectral energy is contained substantially within the
`band of frequencies from 800 Hz to 1700 Hz. Such a
`bandwith is compatible with ,data communications, sys
`‘ terns operating'over radio'communicaticn channels or
`telephone wire lines. In:,the. preferred, embodiment, the
`frequency of the data which is-referred to as, 1000 baud,
`in actuality,~is 1075.28 baud ‘which was selected as close
`as possible to 1000 baud while still, being compatible
`
`Microsoft Ex. 1018
`Page 9 of 12
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`7
`The sync pulses are applied to the data clock 63 for
`phase synchronizing the data clock 63 to the data fre
`quency. In the absence of sync pulses, the data clock 63
`free runs at the data frequency, 1000 baud in the exem
`plary embodiment. The output of the data clock 63 is
`approximately a 1000 Hz square wave with ?fty percent
`duty cycle and is applied to the microcomputer 64. An
`ememplary embodiment of the blocks 62 and 63 of the
`data clock circuitry 72 is illustrated in detail in FIG. 8.
`The data-operated-squelch (DOS) circuitry 71 in
`cludes a squelch ?lter 57, a detector and integrator 58
`and a Schmitt trigger 59. The output of the Schmitt
`trigger is a logical zero when data has been detected and
`is applied to the microcomputer 64. The data-operated
`squelch circuitry 71, accurately discriminates data from
`noise, voice, or music. An exemplary embodiment of
`the blocks 57, 58 and 59 of the DOS circuitry 71 is
`illustrated in detail in FIG. 7.
`A computer system, which controls the generation of
`the modem, includes a microcomputer 64, a crystal
`20
`oscillator 65, a keyboard 66, a display 67, and a location
`data interface 68. The computer system can utilize any
`of a number of commercially available microcomputers
`or computers, for example, the Motorola MC6801 or
`the combination of the MC6802 and MC6846. The crys
`tal oscillator 65 provides the operating frequency for
`the microcomputer 64. The microcomputer 64 receives
`operator information from the keyboard 66 and location
`data from the location data interface 68 and provides
`information to an operator in the display 67. The key
`board 66, display 67 and location data interface 68 (see
`aforementioned US. Pat. No. 3,644,883) are intercon
`nected with the microcomputer 64 via address and data
`bus lines in a conventional manner. Furthermore, all
`interface connections to the microcomputer 64 can be
`readily accomplished by one skilled in the art by con
`ventional techniques. For example, where the mi
`crocomputer 64 is the MC6801, one may refer to the
`published speci?cation for the MC6801 to determine
`speci?c interconnections to the MC6801 ports. When
`40
`using an MC6801, the keyboard 66, display 67 and loca
`tion data interface 68 may be connected to parallel
`address and data ports, while the encode ?lter 56, DOS
`circuitry 71, data limiter 61 and clock circuitry 72 may
`be connected to single-line input/output ports.
`45
`For receiving digital messages, the microcomputer 64
`assembles and de-interleaves the recovered input data
`from the data limiter 61 as de?ned by the recovered
`data frequency from the data clock 63. If an indication
`that data is present is not received from the data-operat
`ed-squelch circuitry 71, the received digital message
`will be ignored. Also, if the recovered input data has
`more than one error in at least one word, the received
`digital message is invalid.
`For transmission of information the microcomputer
`64 arranges the information into a digital message hav
`ing a start code followed by requisite data blocks and
`applies the digital message in MSK format to the en
`code ?lter 56. The encode ?lter 56 takes the digital
`waveform from the microcomputer 64 and provides the
`sinusoidal MSK output data for transmission on the
`communication channel.
`FIGS. 10 and 11 illustrate flow charts of sub-pro
`grams of the modem stored program for receiving and
`transmitting digital messages, respectively. The flow
`charts of FIGS. 10 and 11 represent the logical sequen
`ces of operations that must be performed in order to
`receive and transmit digital messages, respectively. The
`
`8
`?ow charts of FIGS. 10 and 11 are explicit descriptions
`of the microcomputer algorithms necessary to achieve
`the desired function. By referring to the ?ow charts of
`FIGS. 10 and 11, one of ordinary skill in the program
`ming art may code the appropriate combination of in
`structions for a particular microcomputer to satisfy the
`operations called for in each block of the respective
`flow charts. The coding of the flow charts of FIGS. 10
`and 11 may be accomplished in any suitable manner
`using the instructions of the particular microcomputer,
`for example, such as the instructions of the MC6801.
`The operations and processes speci?ed in each block of
`the flow charts of FIGS. 10 and 11 are further supple
`mented in the foregoing description. In FIG. 10, the
`?ow chart of the subprogram for receiving a digital
`message begins at START terminal 300. Preceding to
`box 301, the start code is received serially bit by bit and
`stored in the memory of the microcomputer. Next,
`when the entire start code has been received, the start
`code is checked and correlated with the predetermined
`start code stored in the memory of the microcomputer,
`as shown in box 302. In the preferred embodiment, the
`start code can have as many as six bits out of 32 bits
`which are in error and still recognize the received start
`code. Preceding to decision box 303, if the start code is
`correctly received, the YES branch 305 is taken to
`decision box 306, otherwise the NO branch 304 is taken
`to return along path 319 to box 301.
`The reception of the start code has provided suffi
`cient time for the data-operated-squelch circuitry to
`detect the presence of valid data. In decision box 306, if
`the data-operated-squelch circuitry has been activated,
`the YES branch 308 is taken to box 309, otherwise the
`N0 branch 307 is taken to return along path 319 to box
`301.
`Next, the data blocks following the start code are
`received and stored into the memory of the microcom
`puter, as shown in box 309. Depending on the con?gu
`ration of the data communication system, one or more
`data blocks are received before proceeding to the deci
`sion box 310. Next, at decision box 310, if the data
`operated-squelch circuitry is still activated, the YES
`path 312 is taken to box 313, otherwise a NO path 311 is
`taken to return along path 319 to box 301.
`According to box 313, the received data blocks are
`corrected using the parity portion of each data word to
`correct the respective data portion. Finally, a vertical
`parity word is generated for each corrected data block,
`as shown in box 314. Then in decision box 315, the
`generated vertical parity word is compared with the
`received vertical parity word and if they are identical,
`YES branch 317 is taken to terminal 318, otherwise the
`NO branch 316 is taken to return along path 319 to box
`301. A valid digital message has been received when
`reaching the CONTINUE terminal 318 which is the
`end of this subprogram.
`In FIG. 11, a flow chart of a subprogram for transmit
`ting a digital message begins at the start terminal 400
`and proceeds to box 401. First, the start code which is
`stored in a predetermined location in the microcom
`puter memory is transmitted serially bit by bit with an
`MSK bit pattern. Next in box 402, the selected data
`block is transmitted serially bit by bit an MSK format
`also. Proceeding to decision box 403, if the last data
`block has been transmitted, YES branch 405 is taken to
`RETURN te