Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`Submitted Electronically via the Patent Review Processing System
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC,
`Patent Owner.
`____________________
`
`Case IPR2016-01567
`Patent No. 5,894,441
`____________________
`
`PETITION FOR INTER PARTES REVIEW
`
`

`
`
`
`I. 
`
`TABLE OF CONTENTS
`MANDATORY NOTICES (37 C.F.R. § 42.8) ................................................. 1 
`A. 
`Real Party-In-Interest ............................................................................ 1 
`B. 
`Related Matters ...................................................................................... 1 
`C. 
`Counsel and Service Information .......................................................... 2 
`PAYMENT OF FEES (37 C.F.R. § 42.103)...................................................... 3 
`II. 
`III.  REQUIREMENTS FOR IPR (37 C.F.R. § 42.104) .......................................... 3 
`A.  Grounds for Standing ............................................................................ 3 
`B. 
`Identification of Challenge and Relief Requested ................................ 3 
`C. 
`Level of Ordinary Skill in the Art ......................................................... 4 
`D. 
`Claim Construction ............................................................................... 4 
`IV.  TECHNOLOGY BACKGROUND ................................................................... 5 
`V. 
`THE ’441 PATENT ............................................................................................ 7 
`VI.  PROSECUTION HISTORY OF THE ’441 PATENT ................................... 11 
`VII.  THE CHALLENGED CLAIMS ...................................................................... 12 
`VIII.  THE PRIOR ART ............................................................................................. 12 
`A.  U.S. Patent No. 5,265,055 (“Horiguchi”) ........................................... 12 
`B. 
`U.S. Patent No. 5,126,973 (“Gallia”) .................................................. 18 
`IX.  HOW THE CHALLENGED CLAIMS ARE UNPATENTABLE
`(37 C.F.R. § 42.104 (B)(4)-(5)) ........................................................................ 26 
`A.  Ground 1: Claims 6-12, 14 and 15 Are Anticipated under
`35 U.S.C. §102(b) by Horiguchi ......................................................... 26 
`1. 
`Horiguchi anticipates independent claim 6 ............................... 26 
`2. 
`Horiguchi anticipates dependent claim 7 .................................. 36 
`3. 
`Horiguchi anticipates dependent claim 8 .................................. 39 
`4. 
`Horiguchi anticipates dependent claim 9 .................................. 40 
`5. 
`Horiguchi anticipates dependent claim 10 ................................ 42 
`6. 
`Horiguchi anticipates dependent claim 11 ................................ 45 
`7. 
`Horiguchi anticipates dependent claim 12 ................................ 46 
`i
`
`

`
`B. 
`
`C. 
`
`2. 
`
`3. 
`
`
`
`X. 
`
`Horiguchi anticipates dependent claim 14 ................................ 49 
`8. 
`Horiguchi anticipates dependent claim 15 ................................ 50 
`9. 
`Ground 2: Claims 6, 7, 9, 11, 12, 14, and 15 Are
`Anticipated under 35 U.S.C. §102(b) by Gallia .................................. 51 
`1. 
`Gallia anticipates independent claim 6 ..................................... 51 
`2. 
`Gallia anticipates dependent claim 7 ........................................ 62 
`3. 
`Gallia anticipates dependent claim 9 ........................................ 64 
`4. 
`Gallia anticipates dependent claim 11 ...................................... 66 
`5. 
`Gallia anticipates dependent claim 12 ...................................... 67 
`6. 
`Gallia anticipates dependent claim 14 ...................................... 70 
`7. 
`Gallia anticipates dependent claim 15 ...................................... 71 
`Ground 3: Claims 8 and 10 Are Obvious under 35 U.S.C.
`§ 103(a) in View of Gallia and Horiguchi .......................................... 73 
`1. 
`Gallia and Horiguchi disclose every limitation of
`dependent claim 8 ..................................................................... 73 
`Gallia and Horiguchi disclose every limitation of
`dependent claim 10 ................................................................... 73 
`A person of ordinary skill in the art would have
`been motivated to combine the teachings of Gallia
`and Horiguchi, rendering claims 8 and 10 obvious .................. 75 
`THE PROPOSED GROUNDS OF UNPATENTABILITY ARE
`NOT REDUNDANT ........................................................................................ 78 
`XI.  CONCLUSION ................................................................................................. 80 
`
`
`
`
`
`
`ii
`
`

`
`
`
`TABLE OF EXHIBITS
`
`Exhibit #
`
`Exhibit Description
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`Declaration of Dr. Pinaki Mazumder
`
`Curriculum Vitae of Dr. Pinaki Mazumder
`
`U.S. Patent No. 5,894,441
`
`File History for U.S. Patent No. 5,894,441
`
`U.S. Patent No. 5,265,055 to Horiguchi
`
`U.S. Patent No. 5,126,973 to Gallia
`
`Inter Partes Review No. IPR2016-00094, Petition for Inter Partes
`Review filed October 27, 2015 (without exhibits)
`
`U.S. Patent No. 5,270,975 to McAdams
`
`Japanese Patent Appl. No. H06-052696 to Minami
`
`Inter Partes Review No. IPR2016-00094, Patent Owner’s
`Preliminary Response filed January 27, 2016
`
`Inter Partes Review No. IPR2016-00094, Decision Denying
`Institution filed April 12, 2016
`
`1012
`
`U.S. Patent No. 5,956,285 to Watanabe
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`Masashi Horiguchi et al., A Flexible Redundancy Technique for High-
`Density DRAMs, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 26,
`No. 1, Jan. 1991, at 12-17
`
`U.S. Patent No. 5,267,214 to Fujishima
`
`U.S. Patent No. 5,349,556 to Lee
`
`U.S. Patent No. 5,355,339 to Oh
`
`U.S. Patent No. 5,359,560 to Suh
`
`iii
`
`

`
`1018
`
`1019
`
`U.S. Patent No. 5,798,974 to Yamagata
`
`U.S. Patent No. 5,808,948 to Kim
`
`1020
`
`Masashi Horiguchi, Redundancy Techniques for High-Density
`DRAMs, INNOVATIVE SYSTEMS IN SILICON CONFERENCE, Oct. 1997, at
`22-29
`1021 Masashi Horiguchi et al., NANOSCALE MEMORY REPAIR (Springer
`2011)
`
`1022
`
`Robert T. Smith et al., Laser Programmable Redundancy and Yield
`Improvement in a 64 K DRAM, IEEE JOURNAL OF SOLID-STATE
`CIRCUITS, VOL. SC-16, NO. 5, Oct. 1981, at 506-14
`
`
`
`
`
`iv
`
`

`
`
`
`Apple Inc. (“Apple” or “Petitioner”) petitions under 35 U.S.C. §§ 311-319,
`
`and 37 C.F.R. §§ 42.1-42.80 and 42.100-42.123, for Inter Partes Review (“IPR”)
`
`of claims 6-12, 14 and 15 (“the Challenged Claims”) of U.S. Patent No. 5,894,441
`
`(“the ’441 patent”) (Ex. 1003), filed on March 31, 1998. The ’441 patent issued on
`
`April 13, 1999, to Shigeyuki Nakazawa, and is assigned to Limestone Memory
`
`Systems LLC (“Limestone” or “Patent Owner”), according to USPTO records.
`
`There is a reasonable likelihood that Petitioner will prevail with respect to at least
`
`one Challenged Claim.
`
`I. MANDATORY NOTICES (37 C.F.R. § 42.8)
`A. Real Party-In-Interest
`Petitioner Apple is the real party-in-interest. No other party exercised or
`
`could have exercised control over this petition; no other parties funded or directed
`
`this petition. (Office Patent Practice Trial Guide, 77 Fed. Reg. 48750-60.)
`
`B. Related Matters
`Limestone has asserted the ’441 patent against Apple in Limestone Memory
`
`System LLC v. Apple Inc., 8:15-cv-01274-DOC-KES (C.D. Cal.), filed on August
`
`10, 2015. Apple was served with the complaint alleging infringement of the ’441
`
`patent on August 12, 2015.
`
`In addition, the following judicial matters may affect, or be affected by, a
`
`decision in this IPR: Limestone Memory System LLC v. Micron Technology, Inc.,
`
`8:15-cv-00278-DOC-RNB (C.D. Cal.); Limestone Memory System LLC v. Dell
`
`1
`
`

`
`
`
`Inc., 8:15-cv-00648-DOC-RNB (C.D. Cal.); Limestone Memory System LLC v.
`
`Lenovo (US) Inc., 8:15-cv-00650-DOC-RNB (C.D. Cal.); Limestone Memory
`
`System LLC v. Hewlett-Packard Co., 8:15-cv-00652-DOC-RNB (C.D. Cal.);
`
`Limestone Memory System LLC v. Acer America Corporation, 8:15-cv-00653-
`
`DOC-RNB (C.D. Cal.); Limestone Memory System LLC v. Kingston Technology
`
`Co., Inc., 8:15-cv-00654-DOC-RNB (C.D. Cal.); and Limestone Memory System
`
`LLC v. OCZ Storage Solutions, Inc., 8:15-cv-00658-DOC-RNB (C.D. Cal.).
`
`Limestone is asserting the ’441 patent in each litigation.
`
`The following administrative matters may affect, or be affected by, a
`
`decision in this IPR: IPR2016-01561 (filed by Apple simultaneously with this
`
`petition).
`
`C. Counsel and Service Information
`
`Lead Counsel
`John R. Hutchins (Reg. No. 43,686)
`jhutchins@kenyon.com
`Kenyon & Kenyon LLP
`1500 K Street NW
`Washington, DC 20005
`T: 202.220.4200
`F: 202.220.4201
`
`Back-Up Counsel
`Rose Cordero Prey (rcordero@kenyon.com)
`Kenyon & Kenyon LLP
`One Broadway
`New York, NY 10004
`T: 212.425.7200; F: 212.425.5288
`
`Michael Zachary (mzachary@kenyon.com)
`1801 Page Mill Road, Suite 210
`Palo Alto, CA 94304
`T: 650.384.4700; F: 650.384.4701
`
`
`
`Petitioner consents to email service. Back-Up Counsel will seek
`
`authorization to submit motions to appear pro hac vice.
`
`2
`
`

`
`
`
`II.
`
`PAYMENT OF FEES (37 C.F.R. § 42.103)
`
`The USPTO is authorized to charge the filing fee, and any other required
`
`fees, to Deposit Account 11-0600 (Kenyon & Kenyon LLP).
`
`III. REQUIREMENTS FOR IPR (37 C.F.R. § 42.104)
`A. Grounds for Standing
`Petitioner certifies that the ’441 patent is available for IPR and that
`
`Petitioner is not barred or estopped from requesting IPR challenging the patent
`
`claims on the grounds identified in this petition.
`
`Identification of Challenge and Relief Requested
`
`B.
`Petitioner requests cancellation of all Challenged Claims (claims 6-12, 14
`
`and 15 of the ’441 patent), based on the following references and the Declaration
`
`of Dr. Pinaki Mazumder (“Mazumder Declaration”) (Ex. 1001):
`
` U.S. Patent No. 5,265,055 (“Horiguchi”) (Ex. 1005), issued on
`
`November 23, 1993, and qualifying as prior art under 35 U.S.C. §
`
`102(b); and
`
` U.S. Patent No. 5,126,973 (“Gallia”) (Ex. 1006), issued on June 30,
`
`1992, and qualifying as prior art under 35 U.S.C. §102(b).
`
`The specific statutory grounds of unpatentability are as follows:
`
`3
`
`

`
`
`
`Ground
`1
`
`’441 Patent Claims
`6-12, 14, 15
`
`6, 7, 9, 11, 12, 14, 15
`
`2
`
`3
`
`
`
`Basis for Challenge
`Anticipated under 35 U.S.C. §102(b) by
`Horiguchi
`
`Anticipated under 35 U.S.C. §102(b) by
`Gallia
`
`8, 10
`
`Obvious under 35 U.S.C. §103(a) in view of
`Gallia and Horiguchi
`
`Each of these grounds is explained below and supported by the Mazumder
`
`Declaration and other exhibits.
`
`C. Level of Ordinary Skill in the Art
`As set forth in the Mazumder Declaration (Ex. 1001), a person of ordinary
`
`skill in the art with respect to the technology described in the ’441 patent as of
`
`March 1998 would have had a Master’s degree in electrical engineering or
`
`computer engineering (or an equivalent subject) and three to four years of post-
`
`graduate experience working with dynamic random access memory systems, or a
`
`doctoral degree in electrical engineering or computer engineering (or an equivalent
`
`subject) and one or two years of post-graduate experience working with dynamic
`
`random access memory systems, or an equivalent amount of work experience. Ex.
`
`1001, ¶¶ 28-30.
`
`D. Claim Construction
`The claim terms in an unexpired patent should be given their “broadest
`
`reasonable construction in light of the specification.” 37 C.F.R. § 42.100(b). The
`
`4
`
`

`
`
`
`claim terms are to be given their plain meaning unless inconsistent with the
`
`specification. See In re Zletz, 893 F.2d 319, 321 (Fed. Cir. 1989). The ’441 patent
`
`does not include special definitions for any claim term, and the original
`
`prosecution history of the ’441 patent does not include any claim construction
`
`arguments. The claim terms of the ’441 patent should be construed to have their
`
`plain and ordinary meaning in view of the specification.
`
`IV. TECHNOLOGY BACKGROUND
`The ’441 patent is generally directed to the field of semiconductor memory
`
`devices, in particular random access memories (“RAM”). RAM devices are
`
`comprised of memory cells laid out in rectangular arrays of rows and columns. Ex.
`
`1001, ¶ 33. A chain of memory cells, called words, are arranged in each row and
`
`are addressable by a word line. Id. ¶¶ 33-34. Columns of memory cells spanning
`
`multiple rows are addressable by a column select line. Id. ¶¶ 34-35. The contents
`
`of each memory cell are propagated via bit lines, each cell typically connected to
`
`two bit lines denoting polarity. Id. ¶¶ 35, 41, Fig. 4. Each memory cell, thus, is
`
`located at the intersection of a word line and a bit line, allowing a central
`
`processing unit (such as a microprocessor) to access data for READ and WRITE
`
`operations at any memory location by providing a unique address which identifies
`
`a particular row and column in the memory array. Id. ¶¶ 34-35. The memory
`
`5
`
`

`
`
`
`device includes row and column decoders that decode different combinations of
`
`signals representing an address input into the memory circuit. Id.
`
`Semiconductor memory devices are prone to defects during manufacturing.
`
`Id. ¶¶ 47, 50. To increase yield of operable devices despite having defective
`
`memory cells, RAM manufacturers generally include redundancy circuits that
`
`allow disabling defective cells and replacing them with spare (“redundant”) cells.
`
`Id. ¶¶ 49, 51. Memory circuits provide for redundancy by including on the same
`
`circuit several duplicate rows and/or columns of memory cells, with their
`
`associated word lines and bit lines, to replace any row or column having defective
`
`memory cells. Id. ¶ 51. Separate row and/or column decoders are provided for the
`
`redundant rows or columns that are programmable using programming elements
`
`such as fusible links. Id. ¶¶ 58-59, 69-70. Once the integrated circuit is tested and
`
`the locations of the defective memory cells are determined, the programmable
`
`redundancy decoders are programmed to decode those addresses that correspond to
`
`the rows or columns with defective cells. Id. ¶¶ 52, 59, 70. The defective rows or
`
`columns, and their associated decoders, are subsequently disabled. Id. ¶¶ 54 and
`
`70-71. This way every time a defective row or column is addressed, a redundant
`
`equivalent is selected instead. Id.
`
`To replace the maximum number of defective word lines or bit lines, it is
`
`desirable to include as many redundant cells as practicable. Id. ¶ 47. However,
`
`6
`
`

`
`
`
`these redundant cells and the corresponding redundancy circuitry take up space
`
`within a chip, a limiting factor for a highly integrated and compact memory circuit
`
`chip. Id. ¶ 62.
`
`V. THE ’441 PATENT
`The ’441 patent purports to improve the relief efficiency of defective cells in
`
`a semiconductor memory device by optimizing the space utilized for spare memory
`
`cells while maximizing the number of cells replaced. The ’441 patent recognizes
`
`that a variety of techniques existed in the prior art for replacing defective memory
`
`cells, including techniques based on a row flexible redundancy method. Ex. 1003,
`
`1:46-56. The ’441 patent describes, as the “object of application” of the purported
`
`invention, a semiconductor memory device with “divided” bit lines, i.e., the bit
`
`lines are divided into plural parts that are all activated by a single column address.
`
`Id. 3:23-25; see Figs. 1, 2, 6, 7; Ex. 1001, ¶ 73.
`
`7
`
`

`
`
`
`
`
`
`
`The prior art memory device depicted above in the ’441 patent, Fig. 1,
`
`comprises a normal cell array and a redundant cell array region. Ex. 1003, Fig. 1.
`
`Within the normal cell array, memory cells MC are located, e.g., at the intersection
`
`of word lines 118/120 and bit lines 122. Id. at 3:19-21. The device includes a row
`
`address decoder 106 and column address decoder 108, which activate the word
`
`lines 118/120 and column selection line 122, respectively. Id. at 3:6-17. The
`
`device also includes a row redundancy decoder 112 and a column redundancy
`
`decoder 116, which activate a redundant word line 128 or a redundant column
`
`selection line 130, respectively. Id. at 3:35-60. The redundancy decoders 112 and
`
`116 both include a plurality of fuse elements, which can be programmed to replace
`
`a particular defective word line or bit line. Id. at 3:49-52; Ex. 1001, ¶¶ 74-75.
`
`8
`
`

`
`
`
`In describing this prior art, the ’441 patent explains that when row
`
`redundancy decoder 112 detects a row address corresponding to a defective word
`
`line (according to whether its fuses are blown out), it inhibits the normal row
`
`decoder 106 in order to deactivate the defective word line, and activates a
`
`redundant word line driver 110 to activate redundant word line 128. Ex. 1003,
`
`3:40-46. Similarly, when the column redundancy decoder 116 detects a column
`
`address corresponding to a defective bit line, it inhibits the normal column decoder
`
`108 and activates the redundant column selection driver 114 to activate redundant
`
`column selection line 130. Id. at 3:52-60. ; Ex. 1001, ¶¶ 77-79.
`
`The ’441 patent asserts that in the prior art approach, if one bit line is
`
`defective, then all of the bit lines along a single column are replaced, thereby
`
`reducing the efficiency of the redundancy circuit. Ex. 1003, 3:61-4:5. The ’441
`
`patent purports to increase the relief efficiency of redundant bit lines by enabling a
`
`single redundant column selection line to partially replace components from
`
`different defective columns so that fewer redundant lines are needed, thus reducing
`
`cost and space needed for redundancy circuitry. Id. at 1:37-42, 2:8-13, 2:24-29;
`
`Ex. 1001, ¶ 80.
`
`The ’441 patent describes using a column redundancy decoder that receives
`
`not only a column address but also part of the row address. Ex. 1003, Fig. 2, 6, 7;
`
`Ex. 1001, ¶¶ 88-89.
`
`9
`
`

`
`
`
`
`
`
`
`As shown above in the ’441 patent, Fig. 2, the column redundancy decoder
`
`216 receives the most significant bit of the row address XA0, together with its
`
`complement XA1, thereby dividing the memory array into two sub-arrays. Ex.
`
`1003, 4:20-30. The column redundancy decoder 216 inhibits the normal column
`
`decoder 208 and activates a redundant column selection line 230 corresponding to
`
`redundant bit lines only if XA0 is “1” (and XA1 is “0”), i.e., the row addressed is
`
`within the sub-array of rows with a defective bit line. Id. at 6:20-25. Conversely,
`
`if the row addressed is not within the sub-array of rows associated with a defective
`
`bit line, XA0 is “0” (and XA1 is “1”), the column redundancy decoder is not
`
`enabled, thereby allowing the column decoder 208 to activate the normal column
`
`selection line. Id. at 6:28-39. According to the ’441 patent, relief efficiency is
`
`10
`
`

`
`
`
`improved because only the portion of the column select line with the defective bit
`
`line is replaced, rather than the entire column selection line. Id. at 7:25-35; Ex.
`
`1001, ¶¶ 89-94.
`
`VI. PROSECUTION HISTORY OF THE ’441 PATENT
`The application for the ’441 patent was filed on March 31, 1998, with claims
`
`1-15. Ex. 1004, pp. 35-39. The Examiner allowed all fifteen claims in the first
`
`action dated November 23, 1998. Id. pp. 89-90. The Examiner stated:
`
`[independent claim 6 recites] a semiconductor memory
`device having a first circuit generating a detection signal
`when the column address of a defective column selection
`line is supplied and a second circuit activating said
`redundant column selection line in response to said
`detection signal and at least a part of said row address.
`
`Id. 90. The Examiner further stated that “[t]he PRIOR ART fails to disclose or
`
`suggest such a column redundant circuit responsive to the row address . . . .” Id.
`
`The ’441 patent issued on April 13, 1999.
`
`On October 27, 2015, Micron Technology, Inc. filed a petition challenging
`
`certain claims of the ’441 patent. Ex. 1007. Micron argued that such claims were
`
`unpatentable over U.S. Patent No. 5,270,975 (“McAdams”) and Japanese Patent
`
`Appl. No. H06-052696 (“Minami”). Id. p. 12. That inter partes review was not
`
`instituted. Ex. 1011, p. 2. Patent Owner has disclaimed claims 1-3 and 5 of
`
`the ’441 patent. Ex. 1010, pp. 7, 15, 44-48.
`
`11
`
`

`
`
`
`VII. THE CHALLENGED CLAIMS
`The Challenged Claims of the ’441 patent are all directed to semiconductor
`
`memory devices with the redundancy circuitry described above. Claim 6 is an
`
`independent claim, and claims 7-12, 14 and 15 depend, either directly or indirectly,
`
`from claim 6. Ex. 1003, 13:56-14:52, 14:62-65.
`
`VIII. THE PRIOR ART
`A. U.S. Patent No. 5,265,055 (“Horiguchi”)
`U.S. Patent No. 5,265,055 (“Horiguchi”) (Ex. 1005), entitled
`
`“Semiconductor Memory Having Redundancy Circuit,” was filed on December 27,
`
`1991, and issued on November 23, 1993. Horiguchi qualifies as prior art under 35
`
`U.S.C. § 102(b).
`
`Horiguchi describes a redundancy circuit used in a semiconductor memory
`
`device that consists of a plurality of sub-arrays or “mats”. Ex. 1005, 21:52-66.
`
`Key to the redundancy circuit is an address comparison circuit that selectively
`
`compares address bits with a stored value. Id. at 18:55-19:7. When only the most
`
`significant bits of the row address are compared, the relief efficiency of spare bits
`
`is enhanced and yield is improved. Id. at 19:49-64; Ex. 1001, ¶ 113.
`
`Horiguchi describes several embodiments. Embodiment 8 describes a
`
`memory array divided into four sub-arrays, in a direction parallel to the bit lines,
`
`with the same divided bit line architecture as in the ’441 patent. Ex. 1005, 21:52-
`
`58, Fig. 26; Ex. 1001, ¶¶ 114, 117.
`
`12
`
`

`
`
`
`
`
`
`
`As shown in Horiguchi Fig. 26 above, each sub-array (130-133) includes a
`
`region where regular memory cells are arranged (140-143), and a region where
`
`spare memory cells are arranged (150-153). Ex. 1005, 21:58-61, Fig. 26. Each of
`
`the regions for regular memory cells contains multiple word lines and bit lines
`
`labeled W[i,n] and B[j,n], respectively, where “n” represents the sub-array (e.g.,
`
`n=0, 1, 2, 3), “i” represents the word line number (e.g., i=0, 1, . . .), and “j”
`
`represents the bit line number (e.g., j=0, 1, . . .). Id. at 21:61-65. Horiguchi
`
`explains that each sub-array contains NW/4 word lines (where NW denotes the total
`
`number of word lines in the memory array), NB bit lines and NW ×NB /4 memory
`
`cells. Memory cells used for normal operation are located at the intersections of
`
`the word lines (e.g., W[i,0]) and bit lines (e.g., B[j,0]). Id. at 21:61-65, Fig. 26.
`
`13
`
`

`
`
`
`Redundant memory cells in the spare regions (150-153) are located at the
`
`intersections of the word lines (e.g., W[i,0]) and spare bit lines (e.g., SB[0,0] and
`
`SB[1,0]). Id. at 21:65-22:3, Fig. 26. Horiguchi explains that in a memory array
`
`with L spare bit lines, each sub-array contains NW×L /4 spare memory cells. Each
`
`sub-array also includes dedicated sense amplifiers and input/output circuitry. Id. at
`
`22:3-6. In addition, the four sub-arrays share a single column address decoder
`
`(40), to activate a column selection line YS[j]. Id. at 22:6-10, Fig. 26; Ex. 1001, ¶
`
`118.
`
`Horiguchi further describes a redundancy control circuit 500 that activates a
`
`redundant column selection line to select spare bit lines when a defective memory
`
`cell is accessed. Ex. 1005, 2:66-3:4, 19:65-20:12. Like the column redundancy
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`decoder of the ’441 patent, Horiguchi’s redundancy control circuit 500 compares
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`not only the column address but also row address signals in its address comparing
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`circuit (AC). Id. at 18:35-39. When the column address and the row address both
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`match a stored address identifying a defective memory cell, the defective memory
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`cell can be replaced by a spare or redundant memory cell, bit by bit. For this
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`purpose, redundancy control circuit 500 includes a plurality of address comparing
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`circuits (AC[0], AC[1], AC[2], AC[3]). Id. at 19:66-68, Figs. 21, 26; Ex. 1001, ¶
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`119.
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`14
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`

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`Horiguchi describes each address comparing circuit AC[k] of the
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`redundancy control circuit 500 from Embodiment 8 in Fig. 30 above. Ex. 1005,
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`23:9-13. Each address comparing circuit includes a bit comparing circuit 810 to
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`compare one bit of a received address with a value stored in fuses 861-863. Id. at
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`23:17-21, Fig. 30. When the address bit being compared, Ax[i] (or Ay[j]), matches
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`the stored value, the output of the comparison, Cx[i] (or Cy[j]), is logic-High. Id. at
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`23:43-45. If all of the bit comparing circuits 810 output a logic-High signal Cx[i]
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`(or Cy[j]), indicating that all of the address bits match the bits of a stored address
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`(i.e., a defective memory cell), the output YR of the address comparing circuit is
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`logic-High. Id. at 23:62-65, Fig. 30. Ex. 1001, ¶¶ 122-23.
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`15
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`

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`
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`As shown in Fig. 26 of Horiguchi, the YR outputs (YR[0], YR[1], YR[2],
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`YR[3]) are applied to OR gates 502 and 503, which output YL[0] and YL[1]. Ex.
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`1005, 19:65-20:8, Fig. 26. When a matching comparison enables redundancy,
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`redundant column selection lines SYS[0] and SYS[1] are activated using signals
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`YL[0] and YL[1] to select a spare bit line. Id. at 20:8-10, 22:10-12, Fig. 26. In
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`addition, when the outputs YR[0] to YR[3] of the address comparing circuits are
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`activated, the NOR gate 504 disables the normal column address decoder (40). Id.
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`at 20:10-12, Fig. 26; Ex. 1001, ¶ 124.
`
`Horiguchi discloses the operation details of its redundancy circuit of
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`Embodiment 8 in Fig. 27 (below) and provides examples of various ways regular
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`memory cells may be replaced by spare memory cells. As explained below, a bit-
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`by-bit replacement can be used, or larger groups of cells may be replaced
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`simultaneously. Ex. 1005, 18:53-19:7; 22:27-42; Ex. 1001, ¶ 125.
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`16
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`

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`
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`As shown in Fig. 27, under the “Compared/Not Compared” columns, a “○”
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`symbol indicates that an input address signal is compared with a stored value, (that
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`is, a logical value “0” or “1” is stored in a bit comparing circuit) and an “X”
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`symbol indicates that the address signal is not compared with any data (i.e., a
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`“don’t care” value is stored). Ex. 1005, 18:55-65, 22:27-29. Read vertically, when
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`all of row address signals and column address signals are compared with stored
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`data, as shown in the first column of the table, a regular memory cell can be
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`replaced by a spare memory cell, bit by bit. Id. at 18:65-19:1, 22:27-29. When
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`only the least significant bit of the input row address is not compared (Ax[0]=X), as
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`shown in the second column, a pair of regular memory cells (two bits) are
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`simultaneously replaced by spare memory cells. Id. at 19:4-7, 22:27-29. When the
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`17
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`

`
`
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`memory array is divided into four sub-arrays, address signals for specifying one of
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`the sub-arrays (that is, address signals indicative of two leftmost bits of a row
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`address), are compared with a stored address, as shown in the third column. In this
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`case, a defective bit line in the specified sub-array is replaced by a spare bit line.
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`Id. at 22:29-37. If the column decoder is defective, no row address bits need be
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`compared, as shown in the fourth column. In this case, the corresponding bit lines
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`in all sub-arrays are simultaneously replaced by spare bit lines. Id. at 22:37-42;
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`Ex. 1001, ¶ 126.
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`B. U.S. Patent No. 5,126,973 (“Gallia”)
`U.S. Patent No. 5,126,973 (“Gallia”) (Ex. 1006), entitled “Redundancy
`
`Scheme for Eliminating Defects in a Memory Device,” was filed on February 14,
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`1990, and issued on June 30, 1992. Gallia qualifies as prior art under 35 U.S.C. §
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`102(b).
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`Gallia describes a semiconductor memory device partitioned into four arrays
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`or “data blocks”, each of which comprises a sub-array or “sub-block” of memory
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`cells arranged in addressable rows and columns along row lines and column lines.
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`Ex. 1006, Abstract, 4:25-35, Fig. 1 (below); Ex. 1001, ¶ 128.
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`18
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`
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`As shown above in Gallia Fig. 2, each memory array (data block 12) is
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`partitioned into sixteen sub-arrays (sub-blocks 14), each having its own bank of
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`sense amplifiers SA. Ex. 1006, 4:52-53, Figs. 1, 2. Fig. 3 of Gallia (below) shows
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`a single row of cells in a sub-array. Id. at 4:11-12, 4:59-60. Note that in Fig. 2 of
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`Gallia, the rows run horizontally, and in Fig. 3 of Gallia, the rows run vertically
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`such that Fig. 3 shows a small portion of a sub-array (sub-block 14 in Fig. 2),
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`rotated 90 degrees. Ex. 1001, ¶¶ 129, 131.
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`20
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`Each sub-array contains 256 word lines R and 256 column select lines YS.
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`Ex. 1006. 5:10-11, Figs. 2, 3. A word line is selectively activated by a row
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`decoder based on the row address. Id. at 5:12-16. Similarly, column select lines
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`YS are selectively activated by column decoder 20 for each array. Id. at 5:17-20,
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`Figs. 2, 3. Each array also contains a number of redundant columns RC, which are
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`21
`
`

`
`
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`controlled by a redundant column select line YRS. Id. at 6:8-11, Figs. 2, 3; Ex.
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`1001, ¶ 130.
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`The portion of a column C within each sub-array is formed as a pair of sub-
`
`columns SC. Ex. 1006, 4:59-60. The partial view shown in Fig. 3 illustrates two
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`adjacent pairs of sub-columns SC. A first pair comprises sub-columns SC1 and
`
`SC2; the second pair comprises sub-columns SC3 and SC4. Id. at 4:60-62. Each
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`of the pairs of sub-columns is associated with one of two adjacent columns C1 and
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`C2 in the sub-array. Id. at 4:62-64. Further, each sub-column SC comprises two
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`bit line segments BL and BL(cid:3364)(cid:3364)(cid:3364)(cid:3364) each connected to memory cells, such as memory cell
`
`308, and connected to the same sense amplifier SA. Id. at 4:66-5:1, Fig. 3; Ex.
`
`1001, ¶ 133.
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`Each memory array (data block 12) includes, in addition to memory cells
`
`arranged along 1,024 columns C, a number of redundant columns RC. Ex. 1006,
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`6:5-8, Fig. 3. As with the normal memory cells, the redundant columns RC are
`
`formed as pairs of redundant sub-columns RSC, and a redundant column select line
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`YRS is connected to access data from each sub-column pair. Id. at 6:18-22, Fig. 3.
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`All sub-arrays in a memory array include the same number of redundant column
`
`selects because they are stacked along the column select lines. Id. at 6:22-23; Ex.
`
`1001, ¶ 134.
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`22
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`

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`
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`Gallia discloses that because the four sub-columns SC associated with each
`
`column select line YS in a sub-array are also arranged in pairs, portions of each pair
`
`of redundant columns can be wired to replace one or more portions of a pair of
`
`sub-columns in a column C. Ex. 1006, 6:24-28. In order to substitute defective
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`memory cells with functioning cells, memory cells in each redundant column are
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`arranged along the 4,096 rows of a memory array with each cell connected to a
`
`different row line so that all cells in a redundant column can be accessed with the
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`row address decoder stages 16 and 18. Id. at 6:28-34, Fig. 2; Ex. 1001, ¶ 135.
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`Like the ’441 patent, Gallia further discloses incorporating a level of row
`
`decoding to enable a single redundant column to be segmented to replace defects in
`
`a plurality of column sections. Ex. 1006, 6:60-64. Notably, Gallia discloses that
`
`when two or more defective sections in different columns can be identified with
`
`sufficient row decoding information, a single redundant column can be segmented
`
`to replace all column sections containing the defects in the array. Id. at 6:60-7:22,
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`Ex. 1001, ¶ 136.
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`23
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`Gallia discloses a fusible comparator decoder 40 in Fig. 4 (above), which
`
`receives n-x regular column address signals (CAn-x-1:CA0) and y row address
`
`signals (RAm-y:RAm), where n represents the total number of columns, x
`
`corresponds to the number of redundant columns and y defines the level of
`
`segmentation. Ex. 1006, 7:43-53. The decoder includes a fuse F for programming
`
`it with the r