Redundancy Techniques for High-Density DRAMs
`
`Masashi Horiguchi
`Semiconductor and Integrated Circuits Div., Hitachi Ltd.
`Kokubunji, Tokyo 185, Japan
`
`Abstract
`
`describes the redundancy techniques for high-density DRAMS to solve the
`problems arisen with the increase in memory capacity: (1) the increase in
`division reduces the replacement flexibility between defective l i e s and spare
`defects causing DC-characteristics faults, especially excessive standby current
`faults cannot be repaired with the conventional redundancy techniques. First, two approaches
`to solve the first problem are discussed: enhancing the replacement flexibility within the limits
`of intra-subarray replacement, and the introduction of inter-subarray replacement. Next, the
`recent proposals to solve the second problem are reported. The DC-characteristics faults are
`repaired through the modification of bitlie precharge circuit or the subarray-replacement
`redundancy
`P... g
`1. Introduction
`Redundancy techniques have been widely
`used as effective methods of enhancing the
`on yield and reducing cost-per-bit of
`since 64 - 256-kbit generations [ 11 -
`[5]. The currently used technique replaces
`defective memory
`elements
`(usually
`wordlines andor bitlines (datalines)) by on-
`chip spare elements as shown in Fig. 1.
`However, with the increase in memory
`capacity, the following two problems have
`arisen.
`One is the increase in memory-may
`division shown in Fig. 2. The number of
`
`Programmed: WO Wi W2 W3
`X: Row Decoder
`Y Column Decoder
`SA. Sense Amplifiers
`AC: Address Comparator
`Fig. 1 Conventional redundancy technique
`applied to a DRAM.
`16384 1 lSSCC'86.97
`
`wordline architecture [SI, [9]. The bounda-
`ries between subarrays work as barriers to
`the defective-element replacement, and
`reduces the replacement flexibility, resulting
`in yield degradation.
`The other problem is the defects causmg
`DC-characteristics faults, especially exces-
`sive standby current (IsB) faults.
`An
`example of an ISB fault is shown in Fig. 3
`[lo]. A short circuit between a wordline
`(electrically connected to the ground in the
`y state) and a bitlme (connected to the
`precharge voltage, V D D R ) creates an
`
`
`
`
`
`4696 -
`-
`c
`4 1024-
`?
`-
`256-
`5
`-
`.
`z
`64 -
`
`
`
`16
`
`16M 64M 256M 10
`4M
`Memory Capacity (bits)
`Fig. 2 Trend of memory-array division.
`
`22
`
`0-7803-4275-997 $8.00 01997 BEE
`
`Apple – Ex. 1020
`Apple Inc., Petitioner
`1
`
`

`
`Session 2: Advances in Configuration for Fault Tolerance
`
`23
`
`Chip
`
`VLID
`
`-
`
`DC Current Path
`Fig. 3 ZSB fault model.
`
`illegal Dc current path from VDDi2 to
`ground. Replacing the wordlie (bitline) by a
`spare wordline (spare bitline) inhibits the
`defective line from being accessed, but the
`current path still remains. Thus, the fault is
`not repaired by the conventional redundancy
`technique.
`the redundancy
`This paper describes
`techniques to solve these problems. First, the
`flexibility enhancement within the limits of
`intra-subarray replacement is discussed in
`Section 2.
`Second,
`the
`inter-subarray
`replacement techniques are described
`in
`Section 3. The recent proposals to repair the
`DC-characteristics faults are reported
`in
`Section 4.
`2. Intra-subarrag replacement
`redundancy
`Fig. 1 shows the well-
`known redundancy technique
`[3], [5] applied to a DRAM
`without
`memory-array
`division. Redundant bitlines
`are
`omitted
`here
`for
`simplicity. The memory has
`(here, L = 4) spare
`L
`wordlines SWO - SW3 and as
`many address comparators
`ACO - AC3. Defective word
`addresses are programmed
`(usually by fuses)
`in
`the
`address
`comparators
`and
`compared with
`the
`input
`address. Thus, at most L
`defective normal wordlines
`In this
`can be repaired.
`example, defective normal
`- W3 are
`wordlies WO
`replaced by spare wordlines
`SWO - SW3, respectively, as
`shown by the arrows in the
`figure.
`consider
`let us
`Now
`dividing the memory array
`into subarrays.
`Two ap-
`proaches within the limits of
`intra-subarray
`replacement
`are shown in Fig. 4(a) and
`(b). Here the memory array
`MA in Fig. 1 is divided into
`four subarrays, MAO - MA3,
`only one of which is selected.
`In
`the simultaneous re-
`placement (Fig. 4(a)),
`the
`
`Programmed: WO Wi Wz W3
`
`(a) simultaneous replacement
`
`(b) individual replacement
`Fig. 4 Conventional intra-subarray replacement redundancy
`techniques applied to a DRAM with memory-array division.
`
`2
`
`

`
`24
`
`1996 Innovative Systems in Silicon Conference
`
`number of address compara-
`tors equals L, the number of
`spare wordlines
`in a sub-
`array. Each address com-
`parator compares only the
`intra-subarray address signals
`(here, A0 - An-3), and the
`output is commonly supplied
`to all the subarrays. The
`inter-subarray address signals
`(here, An-2 and An-1) in turn
`select one of the four spare
`wordlines. As many defec-
`tive wordlines can be repaired
`as are shown in Fig. 1, if L is
`the same as that of Fig. 1. In
`this approach four normal
`lines are replaced simultane-
`ouslv bv mare lines. That is.
`to replace one defective normal line, three other normal lines with the same intra-subarray
`address are also replaced even if they are not defective. This causes the following problems.
`First, the usage efficiency of spare lines is lower, and the number of spare lines should be
`larger, which results in chip-area increase. Second, the probability of unsuccessful repair due
`to defects in the spare lines that replaced normal lines is higher, which results in yield
`degradation.
`In the individual replacement (Fig. qb)), every spare line in every subarray has its own
`address comparator. The number of address comparators is therefore L*M, where M (= 4) is
`the number of subarrays. Each address comparator compares both intra- and inter-subarray
`address signals.
`This approach has the following advantages over the simultaneous
`replacement. First, a smaller L is statistically required (here, L = 2) to repair as many defects.
`ticular subarrav is small under
`This is because the Drobabihtv of clustered defects in a I
`random defect distrib;tion. Second, since only one normal j
`e is at a time replaced by a spare
`line, the probability of a defect in the spare line is lower.
`his approach, however, has the
`
`Programmed: WO W3 Wi Wz
`
`Fig. 5 Flexible intra-submay replacement redundancy
`technique applied to a DRAM with memory-may division.
`
`1
`
`1
`
`1
`
`
`
`100
`80
`60
`
`40
`
`20
`
`10
`a
`6
`
`4
`
`2
`
`m = 4
`
`100
`80
`60
`
`40
`
`20
`
`10
`8
`6
`
`4
`
`2
`
`'
`
`0
`
`
`
`'
`
`0
`
`8
`6
`4
`2
`8
`6
`4
`2
`Defect Density (cm.2)
`Defect Density (cm-2)
`(c) I-Gbit DRAM
`(b) 64-Mbit DRAM
`(a) CMbit DRAM
`Fig. 6 Calculated DRAM yield with conventional and flexible inka-subarray replacement
`redundancy techniques.
`
`
`
`3
`
`

`
`Session 2: Advances in Configuration for Fault Tolerance
`
`25
`
`Sense Amplifier
`
`Defect
`
`...........
`
`. -. - -. -)(-. - -. .
`I
`CSL
`Defect
`
`zz:
`
`Bitline
`Sense amp.
`CSL
`
`1 without "don't-care"
`
`Number of address comparators
`with "don't-care''
`programming
`I
`1
`1
`
`proarammina
`1
`2
`n *
`
`disadvantage of lower usage efficiency of address comparators, resulting in an increase in the
`area of address comparators.
`Fig. 5 shows the flexible intra-subarray replacement scheme [ I l l proposed to overcome the
`problems described above. The spare lines and address comparators are not connected directly,
`but through the OR gates GO and GI. Each address comparators compares both intra- and inter-
`subarray address signals. This connection provides a flexible relationship between spare lines
`and address comparators. In the architecture shown in Fig. 4, this relationship is fixed so that a
`spare line can be activated only by a particular address comparator. However in Fig. 5, a spare
`line can be activated by one of several address comparators. Another advantage of this
`architecture
`is
`that more
`flexible
`selection of the number of address
`as well as the
`comparators C.
`relationship L 5 C 5 L*Mlm stands,
`where m is the number of subarrays in
`which defective normal
`lines are
`simultaneously replaced by
`spare
`lines.
`The calculated yield through the
`conventional (Fig. 4(a)) and flexible
`(Fig. 5 ) intra-subarray replacement
`redundancy techniques is shown in
`Fig. 6. The yield improvement factors
`through the both techniques are almost
`the same in a 4-Mbit DRAM. The
`advantage of the flexible technique
`becomes apparent in 64-Mbit and 1-
`Gbit DRAMS, especially for a large
`defect density, that is, in the early
`stages of production. For a 1-Gbit
`DRAM, however,
`the yield
`is
`determined mainly by fatal defects,
`such as those causing excessive
`standby current.
`When the flexible intra-subarray
`replacement
`is applied
`to bitline
`redundancy, the problem of a ' global'
`defect (a defect over two or more
`subarrays) arises. A defect on a
`sense-amplifier or a column selection
`line (CSL) in a DRAM using the
`multidivided bitline architecture [6],
`[7] causes two or more bitlines to fail
`simultaneously as shown in Fig. 7.
`Thus
`these
`types of defects are
`'global' and require more than one
`address comparators to be repaired.
`To solve this problem, programming
`"don' t-care"
`values
`in
`address
`[ 1 I].
`comparators was proposed
`Table I shows the number of addIess
`comparators required to repair the
`various defects with and without
`"don't-care'' programming.
`The access-time penalty due to
`redundancy is the delay time required
`for the address comparison. Fig. 8
`
`"8'
`
`Fig. 8 No access-penalty intra-subarray replacement
`redundancy technique [ 121 (simultaneous activation of
`normal and spare lines).
`
`4
`
`

`
`26
`
`1996 Innovative Systems in Silicon Conference
`
`shows a technique to eliminate this delay time for a high-speed SRAM [12]. In this technique, a
`defective line in a subarray is replaced by a spare line in the adjacent subarray. The two
`subarrays are activated simultaneously and one of the data from them is selected according to the
`result of address comparison. This technique is difficult to be applied to wordline redundancy
`of a DRAM because of the doubling of the bitline charginddischarging current. However, it
`can be applied to bitline redundancy [13]. Note that this technique is not inter-subarray
`replacement. This will be clear if the hatched areas in Fig. 8 are assumed to be a subarray and
`the white areas are assumed to be another subarray.
`3. Inter-subarray replacement redundancy
`With the further increase in memory-array division, the probability of clustered defects in a
`particular subarray becomes no more negligible. In the intra-subarray replacement, the number
`of spare lines in a subarray, L, must be larger or equal to the maximum number of defective
`lines in a subarray to repair clustered defects. This causes the increase in L and chip-area
`penalty
`To solve this problem, inter-subarray replacement redundancy techniques [ 141 - [ 161 were
`proposed, which permit a defective l i e to be replaced by a spare line in any subarray. They are
`classified into two categories as shown in Fig. 9.
`In the distributed-smre-lie amroach 1141 shown in Fig. 9(a), each subarray has its own
`Each spare line, however, c& replace any
`spare lines like the &tra-subarrai replacement.
`defective normal line not only
`in the same subarray but also
`in another subarray. There-
`
`clustered fore at most in L*M
`
`
`a particular defects
`
`~~~
`
`ACo # ACi #AC2#AC3# AC4]
`AO - An-3
`Awn, An.1
`Programmed: WO Wi W2 W3 W4
`
`I
`
`I
`
`I
`
`I
`
`1
`
`subarray can be repaired,
`where M is the number of
`subarrays. In this example,
`four
`clustered
`defective
`normal wordlines WO - W3
`are replaced by the spare
`wordlines in subarrays M A O ,
`MA1 and MA2.
`It is suffi-
`cient for successful repair that
`the number L is the average
`number of defective lines in a
`subarray and is smaller than
`that of
`intra-subarray
`re-
`placement. The number of
`address comparators C
`is
`equal to L*M in this case.
`The number, however, can
`through
`reduced
`be
`the
`similar technique shown i
`Fig. 5 .
`In the concentrated-spare-
`[16]
`line approach [15],
`shown in Fig. 9(b), each
`subarray has no spare lines.
`There is a spare subarray
`MAS, instead, composed of
`L' (here, L' = 5 ) spare lines.
`Each spare line can replace a
`defective normal line in any
`subarray. Therefore at most
`
`(a) distributed spare lines
`
`A&# A& #A&# A&# A&#AC5# A&# A b 1
`Awn, An-3 An-i
`Programmed: WO WI W2 W4 W3 none none none
`
`(b) concentrated spare lines
`Fig.9 Inter-submay replacement redundancy techniques.
`
`5
`
`

`
`Session 2: Advances in Configuration for Fault Tolerance
`
`27
`
`.,
`
`16 Subarrays
`. . . . . . . .... Intra-subarray
`- Inter-subarray
`
`',,
`
`',.,
`
`
`
`.**,-L=l
`
`Y
`.,
`
`/'
`
`/ L = 2
`
`0
`
`'
`
`'
`
`'
`
`'._
`'
`
`'
`
`~
`
`~
`
`~
`
`'
`
`8
`
`' . . _ c .
`
`,
`8
`
`,
`
`'
`
`,
`
`i
`
`I
`
`,
`
`
`
`Fig. 10 Comparison between intra- and inter-subarray
`replacement redundancy techniques.
`
`p 60
`0
`jt
`
`40
`
`20
`
`0
`1
`
`2
`Chip Area (cmz)
`Fig. 11 Yield improvement through line and subarray
`replacement.
`
`4
`
`S I . _ _ _
`
`'..(
`100
`.
`g
`- , . ,
`.- -
`-
`b 80
`-
`5
`60-
`l
`i
`-
`al
`6 4 0 -
`.-
`!!
`m
`-
`rr" 20-
`Q
`
`'.,
`
`
`
`L' defects clustered in a subarray can
`be repaired. The number of address
`comparators C is equal to L'. This
`approach has an advantage of more
`flexible selection of L' (= C) and
`better usage of address comparators
`compared to the distributed-spare-
`line approach. This is because the
`size of the spare subarray need not
`be the same as that of a normal
`subarray.
`The problem of
`this
`approach is that additional circuits (a
`decoder, a sense amplifier, etc.) for
`MAS are needed. A solution of this
`problem using the hierarchical bitline
`architecture is proposed in [ 151.
`Fig. 10 compares the repairable
`probability using intra- and inter-
`subarray replacement
`redundancy
`techniques [ 141, [ 161. Here, defects
`causing fatal faults and defects on
`spare
`lines
`are neglected
`for
`In the intra-subarray
`simplicity.
`replacement, the repairable probabil-
`ity of a memory composed of M
`subarrays
`decreases with
`the
`increase in the number of defects, K ,
`because the probability of excessive
`(> L ) defects in a particular subarray
`increases. On the other hand, the
`repairable probability is constantly
`100% as long as K 5 L*M in the
`inter-subarray replacement.
`The
`expectation of
`repairable defects
`through inter-subarray replacement
`is about three times that through
`intra-submay replacement when the
`number of subarrays is 16.
`The access-time penalty of the inter-subarray replacement is usually larger than that of intra-
`subarray replacement. This is because not only an activated-line but also an activated subarray
`may be changed according to the result of address comparison.
`4. Repair of DC-characteristics faults
`As described in Section 2, the yield of gigabit DRAMS will be mainly determined by defects
`causing DC-characteristics faults, especially excessive standby current (ZSB) faults. The
`conventional line-replacement redundancy is not sufficient for DRAMS of 256 Mbit or larger,
`due to ISB faults as shown in Fig. 11 [lo]. Several redundancy techniques were proposed to
`enable the repair of such faults [IO], [16], [17].
`Fig. 12 shows two techniques to repair a short circuit between a wordline and a bitline. Both
`technique modify the bitline precharge circuit. The fist approach (Fig. 12(a)) [16] limits the
`illegal E-current through the short circuit to a small value (-15 p 4 / short circuit) by a current
`limiter. The ZSB of a memory chip with a relatively small number of short circuits is thereby
`limited within the specification. The second approach (Fig. 12(b)) [ 171 cuts off the DC-current
`path by a power switch controlled by a fuse. It is reported that the test to locate short-circuit
`faults is possible using the switch.
`
`6
`
`

`
`28
`
`1996 Innovative Systems in Silicon Conference
`
`Fig. 13 shows another
`technique [lo] using spare
`A defective
`subarrays.
`subarray including an ISB
`fault is replaced by an on-
`chip spare subarray. Each
`subarray
`has
`power
`switches for bitline pre-
`charge voltage VON2 and
`memory-cell plate voltage
`VPL, logic gates for timing
`signals, and a fuse
`to
`control them. The power
`switches of the defective,
`subarray are tumed off and 1
`those of the spare subarray
`are turned on. Thus the ISB
`fault is repaired by cutting
`of the DC current. The
`logic gates of the defective
`subarray are also tumed off
`to avoid unnecessary power
`dissipation in the subarray.
`This
`technique combined
`with the conventional line-
`replacement
`redundancy
`doubles the yield of a 256-
`Mbit DRAM as shown in
`Fig. 11. An advantage of
`this technique is that the
`in an unused
`wordlines
`spare subarray are used as
`spare wordlines of
`the
`concentrated-spare-line
`inter-submay replacement
`redundancy described
`in
`Section 3 [ 181.
`Since this redundancy
`technique requires spare
`subarrays, it is not suitable
`for a small-capacity mem-
`ory with a small number of
`subarrays. However, the
`number of subarrays in-
`creases with every DRAM
`generation as shown in Fig.
`2. The areapenalty will be
`allowable for DRAMS of
`256 Mbit and beyond as
`shown in Fig. 14.
`It is
`interesting that the memory-
`array division, which was
`the barrier
`to
`the
`line-
`replacement redundancy, in
`turn, supports the subarray-
`replacement redundancy.
`
`Bitline
`Precharge
`
`Bitline
`
`PC
`
`Vod2
`
`(a) current limiter
`(b) power switch
`Fig. 12 Short-circuit defect repairing schemes [ 161, [ 171.
`
`Fig. 13 Subarray-replacement redundancy technique [IO].
`
`8 Spare Subarrays
`4 Spare Lines I Subarray
`EBZ4 ROMs and Circuitry
`0 Spare Cells
`
`I
`
`
`
`I
`64
`
`I
`I
`256
`128
`Number of Subarrays
`
`I
`
`I
`512
`
`
`
`Fig. 14 Chip-area penalty due to redundancy.
`
`7
`
`

`
`Session 2: Advances in Configuration for Fault Tolerance
`
`29
`
`5. Conclusion
`Redundancy techniques to solve the problems arisen with the increase in DRAM capacity
`were discussed. Enhancing the replacement flexibility between defective lines and spare lines
`through the flexible intra-subarray replacement or through inter-subarray replacement is
`effective for DRAMs of increased memory-array division. The Dc-characteristics faults,
`especially excessive standby-current faults, are repaired through the modification of bitline
`precharge circuit or the subarray-replacement redundancy. The optimal combination of these
`techniques will be critical for the yield enhancement and bit-per cost reduction of gigabit
`DRAMs.
`Acknowledgment
`The author would like to thank K. Itoh, M. Aoki, G. Kitsukawa, and Y. Nakagome for their
`suggestions and discussions.
`References
`[l] R. P. Cenker et al., "A fault-tolerant 64K dynamic random-access memory," IEEE Trans.
`Electron Devices, vol. ED-26, pp. 853-860, June 1979.
`[2] T. Mano et al., "A redundancy circuit for a fault-tolerant 256K MOS RAM," IEEE J. Solid-
`State Circuits, vol. SC-17, pp. 726-731, Oct. 1982.
`[3] S. S. Eaton et al., "A lOOns 64K dynamic RAM using redundancy techniques," in ISSCC
`Dig. Tech. Papers, Feb. 1981, pp. 84-85.
`[4] R. T. Smith et al., "Laser programmable redundancy and yield improvement in a 64K
`DRAM"lEEE J. Solid-state Circuits, vol. SC-16, pp. 506-514, Oct. 1981.
`[5] K. Shimohigashi et al., "Redundancy techniques for dynamic RAMS," in Proc. 14th Conf.
`Solid State Devices, Aug. 1982, pp. 63-67.
`[6] R. Hori et al., "An experimental 1 Mbit DRAM based on high SIN design," IEEE J. Solid-
`State Circuits, vol. SC-19, pp. 634-640, Oct. 1984.
`[7] K. Itoh, "Trends in megabit DRAM circuit design," IEEE J. Solid-state Circuits, vol. 25,
`pp. 778-789, June 1990.
`[8] D. Galbi et al., "A 33-ns 64-Mbit DRAM with master-wordline architecture," in ESSCIRC
`Dig. Tech. Papers, Sep. 1992, pp. 13 1 - 134.
`[9] T. Sugibayashi et al., "A 30-11s 256-Mb DRAM with multidivided array structure, I' IEEE J.
`Solid-state Circuits, vol. 28, pp. 1092-1098, Nov. 1993.
`[ 101 G. Kitsukawa et al., "256-Mb DRAM circuit technologies for file applications," IEEE J.
`Solid-state Circuits, vol. 28, pp. 1105-1 113, Nov. 1993.
`[ 1 11 M. Horiguchi et al., "A flexible redundancy technique for high-density DRAMs" IEEE J.
`Solid-state Circuits, vol. 26, pp. 12-17, Jan. 1991.
`[12] K. Sasaki et al., "A 9-11s I-Mbit CMOS SRAM," IEEE J. Solid-state Circuits, vol. 24,
`pp. 1219-1225, Oct. 1989.
`[ 131 H. Yamauchi et al., "A circuit teF-iology for high-speed battery-operated 16-Mb CMOS
`DRAM'S," lEEE J. Solid-state Circuits, vol. 28, pp. 1084-1091, Nov. 1993.
`[I41 K. Ishibashi et al., "A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-
`layout sense amplifiers," IEEE J. Solid-state Circuits, vol. 29, pp. 41 1-418, Apr. 1994.
`[15] M. Asakura et al., "A hierarchical bit-line architecture with flexible redundancy and block
`compare test for 256Mb DRAM," in Symp. VLSI Circuits Dig. Tech. Papers, May 1993, pp.
`93-94.
`. [I61 T. Kirihata et al., "Fault-tolerant designs for 256 Mb DRAM," IEEE J. Solid-state
`Circuits, vol. 31, pp. 558-566, Apr. 1996.
`[17] K. Furutani et al., "A board level parallel test and short circuit failure repair circuit for
`high-density, low-power DRAMS," in Symp. VLSI Circuits Dig. Tech. Papers, June 1996, pp.
`70-71.
`[18] M. Asakura et al., "A 3411s 256Mb DRAM with boosted sense-ground scheme," in ISSCC
`Dig. Tech. Papers, Feb. 1994, pp. 140-141.
`
`8