United States Patent [19]
`Gallia et a].
`
`[54] REDUNDANCY SCHEME FOR
`ELIMINATING DEFECTS IN A MEMORY
`DEVICE
`[75] Inventors: James D. Gallia, Dallas; Jim
`Childers, Fort Bend. both of Tex.
`Texas Instruments Incorporated,
`Dallas, Tex.
`-
`Appl. No.: 479,510
`Filed;
`Feb. 14, 1990
`
`[73] Assignee:
`
`Int. Cl.-‘ .............................................. .. GllC 7/00
`US. Cl. ............................. .. 365/200; 365/230.03;
`365/23006
`Field of Search ............ .. 365/200. 230.03, 230.06;
`371/103, 11.1, 8
`
`References Cited
`US. PATENT DOCUMENTS
`
`[Z1]
`22]
`[51]
`[52]
`
`[53]
`
`[56]
`
`371/103
`4,047.16} 9/1977 Choate et al. ..
`.... ._ 365/200
`4,604,730 8/1986 Yoshida 6131,
`4.754.434 6/i988 \Vang et al. ....................... .. 365/200
`Primary Examiner—-_loseph A. Popek
`Attorney. Agent, or Firm—-Ronald O. Neerings;
`Lawrence J. Bassuk; Richard L. Donaldson
`
`llllllllllllllllllllllllllllllllllllllllllIllllllllllllllllllllllllllllllll
`5,126,973
`Jun. 30, 1992
`
`USOO5126973A
`Patent Number:
`Date of Patent:
`
`[11]
`[45]
`
`ABSTRACT
`[57]
`A redundancy scheme for a memory device, as well as
`a method for developing a redundancy scheme. result
`ing in improved repairability for given space con
`straints. A memory device is formed with a plurality of
`data blocks having individual input/output paths. Each
`block comprises an array of memory cells arranged in
`addressable rows and columns along row lines and col
`umn lines. The array is con?gured in sub»blocks each
`comprising a plurality of the memory cells. The device
`includes row address circuitry for selecting a row of the
`memory cells, column address circuitry for selecting a
`column of the memory cells and address repair cir
`cuitry. The address repair circuitry is con?gurable to
`render a ?rst portion of a ?rst of the columns of cells
`responsive to the address ofa portion ofa second of the
`columns of cells, There is also provided a method for
`eliminating a defect in a memory device having a logi
`cal data block formed with addressable rows and col
`umns of memory cells. A defect associated with a ?rst
`column of cells is eliminated by programming a portion
`of a second column of cells to be responsive to the
`addresses of a portion of the cells in the ?rst column.
`
`4 Claims, 10 Drawing Sheets
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`June 30, 1992
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`US. Patent
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`June 30, 1992
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`June 30, 1992
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`5,126,973
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`US. Patent
`
`June 30, 1992
`
`Sheet 9 0f 10
`
`5,126,973
`
`[2] [2]
`
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` 10
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`

`
`US. Patent
`
`June so, 1992
`
`Sheet 10 of 10
`
`5,126,973
`
`['3] [31m
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` 11
`
`

`
`1
`
`5,126,973
`
`REDUNDANCY SCHEME FOR ELIMINATING
`DEFECTS IN A MEMORY DEVICE
`
`The present invention relates to semiconductor mem
`ory devices and. more particularly, to devices which
`include repair circuitry for eliminating defects in mem
`ory devices.
`
`5
`
`BACKGROUND OF THE INVENTION
`In the fabrication of semiconductor memory devices
`it is common for an array of memory cells to include
`one or more defects which prevent the proper perfor
`mance of the memory circuit. Ifa type of defect occurs
`systematically it can often be causally analyzed and
`designed out. Other defects which are generally not
`systematic include short circuits between adjacent col
`umns and open circuits within individual columns of
`memory cellsv For analysis purposes the distribution of
`such defects in a memory device, as well as the distribu
`tion of the number of defects among a given production
`lot, may be considered random so that the yield of good
`devices in a lot can be modelled according to a Poisson
`distribution function. Typically, over the period oftime
`that a particular device or family of devices is being
`produced in a given manufacturing facility the product
`yield can be improved by removing causes, e.g., partic
`ulate matter, of the above-mentioned random defects.
`In many fabrication processes the causes of random
`defects cannot be completely eliminated and it is desir
`able to further improve the yield of memory devices
`with redundant circuitry. During testing of a chip de
`fective memory cells can be identi?ed and replaced.
`Such redundancy techniques are especially suited for
`35
`semiconductor memories because large numbers of
`repeating elements are arranged in columns and rows.
`This array format lends itself to replacement ofa defec
`tive column or row with any of multiple identical re
`dundant columns or rows.
`A redundant circuit scheme may be implemented
`with a plurality of universal decode circuits connected
`to the redundant columns. To activate the redundant
`circuitry appropriate fuses are included for program
`ming individual decoder circuits to be responsive to the
`addresses of defective memory cells. For example, in
`dynamic random access memory devices (DRAM‘s)
`address integrity can be maintained by simply program
`ming redundant column circuits to respond to defective
`column addresses. Thus the address of each defective
`column is assigned to a redundant column circuit. In
`video and frame memory circuits ‘the replacement pro
`cedure may require greater complexity in order to
`maintain the sequential nature of memory output. See
`U.S. Pat. No. 4,598,388 assigned to the assignee of the
`present invention.
`Semiconductor memories of all types are being made
`with progressively higher bit densities and smaller cell
`sizes as the density of integrated memory circuits in
`creases. In 1972 4K bit DRAMs were being designed
`while in 1982 one megabit devices were planned. Six
`teen megabit device densities will become mass pro
`duced during the 19905. As memory capacity continues
`to progress there must be further improvement in asso
`ciated performance parameters such as memory access
`time. As a result memory architectures, which have
`already become relatively complex. are likely to be
`come even more elaborate as device densities increase.
`
`45
`
`55
`
`60
`
`65
`
`2
`In order to improve performance it is now common
`place to partition higher density memory arrays into
`logical data blocks wherein all cells associated with a
`particular block have common I/O paths. With this
`arrangement data blocks in an array can be individually
`accessed. Accordingly, each data word, e.g., possibly
`16 or 32 bits wide in a 64 Megabit device, could be
`stored entirely within one of the blocks so that the
`entire word can be retrieved from the memory at a
`given time. Thus there is no loss in availability of data.
`Advantageously, the blocks in a partitioned array have
`shorter signal paths, smaller propagation delays and
`hence faster access times. Further, since only one of
`many blocks is accessed at a time, the overall device
`power consumption is also reduced.
`Such partitioning requires that at least some of the
`support circuitry, which functions to select desired
`memory locations as well as to sense and maintain data
`states, be repeated for each data block. When the con
`cept of internally partitioning a memory array into
`smaller logical data blocks was introduced, the memory
`densities were lower than now achievable and repeti
`tion of support circuitry for each data block was an
`acceptable cost in view of the above-noted performance
`bene?ts. That is, the resulting increase in chip size over
`that required for a slower, more power consuming
`array design was not critical.
`Now, with the development of even denser memory
`devices, the requisite reduction in feature sizes renders
`these circuits susceptible to defects caused by particu
`late matter which previously caused no problems in the
`fabrication process. Thus with further improvements in
`circuit density there will be a greater challenge to elimi
`nate random-type defects. Accordingly, greater reli
`ance may be placed on redundant circuit repair
`schemes.
`In theory, by providing a sufficient number of redun
`dant circuits on a device, all column defects of the type
`described above would be repairable in order to maxi
`mize the yield ofa production lot. Practically, however,
`cost effectiveness usually dictates that space constraints
`will limit the quantity of redundant circuits to be placed
`on each integrated circuit. It is undesirable to increase
`repair circuitry in proportion to memory density.
`
`SUMMARY OF THE INVENTION
`In the past redundancy schemes have consisted of
`only a few extra rows and columns in order to replace
`up to a predetermined maximum number of defective
`elements. As long as each logical data block of an inter
`nally partitioned memory device included separate ad
`dress circuitry, the inclusion of sufficient redundant
`row and column lines within these data blocks did not
`present difficulties.
`Now, due to cost constraints which limit the package
`size of higher density circuits, it is undesirable to repeat
`for each memory data block all of the support circuitry
`needed to replace defective cells. By way of example,
`redundant column select circuitry need not be repeated
`for each data block. In fact, it is more space efficient to
`generate the repair column select signals for all of the
`data blocks with one series or bank of decoder circuits.
`Although sharing of support circuitry among data
`blocks results in significant saving of space for a circuit
`layout, it is now‘ recognized that such schemes both
`complicate and reduce the efficiency of prior art repair
`techniques.
`
` 12
`
`

`
`5,126,973
`3
`It is an object of the invention to provide a redun
`dancy scheme which includes a predetermined number
`of decoder circuits and is more space ef?cient or more
`effective than other redundancy schemes having the
`same number of decoder circuits.
`More generally, there is provided a redundancy
`scheme, as well as a method for developing a redun
`dancy scheme, resulting in improved device repairabil
`ity for given space constraints. A memory device is
`formed with a plurality of data blocks having individual
`input/output paths. Each block comprises an array of
`memory cells arranged in addressable rows and col
`umns along row lines and column lines. The array is
`con?gured in sub-blocks each comprising a plurality of
`the memory cells. The device includes row address
`circuitry for selecting a row of the memory cells, col
`umn address circuitry for selecting a column of the
`memory cells and address repair circuitry. The address
`repair circuitry is con?gurable to render a ?rst portion
`of a ?rst of the columns of cells responsive to the ad
`dress ofa portion of a second of the columns of cells.
`There is also provided a method for eliminating a
`defect in a memory device having a logical data block
`formed with addressable rows and columns of memory
`cells. A defect associated with a ?rst column of cells is
`eliminated by programming a portion of a second col
`umn of cells to be responsive to the addresses ofa por
`tion of the cells in the ?rst column.
`In a preferred embodiment of the invention the ad
`dress repair circuitry includes at least ?rst and second
`decoders. The ?rst decoder is programmable to render
`the ?rst portion ofthe ?rst column ofcells responsive to
`the address of the portion ofthe second of the columns
`ofcells. The second decoder is programmable to render
`a second portion ofthe ?rst column of cells responsive
`to the address ofa portion ofa third one ofthe columns
`of cells. Alternately the second decoder may be pro
`grammed to render a portion ofa ?rst of the columns of
`cells in a second of the data blocks responsive to the
`40
`address ofa portion ofa second of the columns of cells
`in the second data block.
`According to one example of the preferred embodi
`ment a memory device is formed with a plurality of
`logical data blocks each having individual input/output
`45
`paths. One of the blocks comprises an array of memory
`cells arranged in rows and columns and con?gured in
`sub-blocks. Each sub-block includes a plurality of mem
`ory cells arranged in rows and subcolumns. The block
`also contains row address circuitry for selecting a row
`50
`of memory-cells and column address circuitry for se
`lecting a memory cell in a column which intersects a
`selected row. A second group of memory cells is ar
`ranged in a repair column which includes a repair sub
`column for each sub-block of memory cells in the logi
`cal data block. Address repair circuitry is provided for
`replacing subcolumns in the array with repair sub
`columns. The repair circuitry includes a plurality of
`programmable repair column decoders for selecting a
`repair subcolumn or a segment of repair subcolumns
`based on row and column address information.
`With this scheme incorporating a level of row decod
`ing in the repair column decoders, portions of redun
`dant columns can be allocated to replace portions of
`array columns containing defective memory cells.
`Thus, with multiple decoders, a single redundant col
`umn can be utilized to replace multiple defects occuring
`in different columns.
`
`60
`
`4
`BRIEF DESCRIPTION OF THE DRAWINGS
`The invention may be best understood by reference
`to the following detailed description of a preferred
`embodiment when read in conjunction with the accom
`panying drawing, wherein:
`FIG. 1 is a plan view ofa memory device which may
`incorporate the invention;
`FIG. 2 illustrates the general layout ofa logical data
`block in the device of FIG. 1;
`FIG. 3 is a partial view of a sub-block of one of the
`data blocks;
`FIG. 4 schematically illustrates a fusible comparator
`decoder according to the invention;
`FIG. 5 illustrates in block diagram form a column
`repair scheme according to the invention;
`FIGS. 6A through 6E portray an analysis and me
`thodolgy for improving the achievable level of column
`repair for a logical data block; and
`FIGS. 7A through 7F illustrate statistical trends re
`lating to device repairability according to the invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`The block diagram of FIG. 1 illustrates a semicon
`ductor memory device with which the invention may
`be practiced. This exemplary device 10 is a DRAM of
`the socalled l6 Megabit size, having an array 12 of 224
`or 16,777,216 onetransistor storage cells arranged in
`rows and columns. According to a preferred architec
`ture the array 12 is partitioned into four identical subar
`rays or blocks, individually designated 12a, 12b, 12c and
`12d. Each block 12 is of the four megabit size, compris
`ing 4,194,304 memory cells arranged in an array of
`4,096 rows and 1,024 columns C.
`Device 10 operates as a standard DRAM part to read
`and write data bits DQl-DQ4 into data in buffer 15 and
`out from data out buffer 17 in response to normal time
`multiplexed address signals AO-All received in ROW
`address buffers 22 and column address buffers Mind in
`response to timing signals including m, CKS‘, W and
`6 received at timing and control circuits 19. Row de
`coders l6 and 18 and column decoders 20 use the buff
`ered address signals to select the desired memory cells
`and connect their contents to I/O buffers 21. From
`there the selected data is read out of data out buffer 17.
`Writing data occurs in a known similar manner from
`data in buffer 15, through I/O buffers 21 to the selected
`memory cells.
`Circuit details of the device 10 which are helpful to
`understanding the invention are illustrated in FIGS. 2, 3
`and 4. As indicated in FIG. 2 each data block 12 is
`partitioned into sixteen sub-blocks 14. The portion of a
`column C within each sub-block 14 is formed as a pair
`of interdigitated subcolumns SC. See FIG. 3. Thus 1024
`pairs of subcolumns are in each sub-block. Banks of
`sense ampli?ers SA border upper and lower opposing
`sides of each sub-block.
`The partial view of FIG. 3 illustrates two adjacent
`pairs of interdigitated subcolumns SC. The ?rst pair
`comprises subcolumns SC 1 and SC; and the second pair
`comprises subcolumns SC; and 5C4. Each of the pairs
`of subcolumns is associated with one of two adjacent
`columns C1 and C2 in the sulrblock. As is common in
`high density DRAM devices the subcolumns are ar
`ranged in a folded bitline con?guration. Thus each
`subcolumn SC comprises two bitline segments BL and
`K each connected to memory cells, such as memory
`
` 13
`
`

`
`5
`cell 308. and connected to the same sense ampli?er SA.
`The two subcolumns within the sub-block 14 that are
`associated with the same column C are coupled to dif
`ferent sense ampli?ers SA on opposing sides of the
`sub-block 14. Except for the outermost banks of sense
`ampli?ers in the data block 12 (i.e., those situated along
`the outer sides of the ?rst and last of the sixteen sub
`blocks) each bank of sense ampli?ers is shared by sub
`columns in an adjacent pair of sub-blocks.
`Within each sub-block 14 there are 256 row or word
`lines R and 256 column select lines Y5. For simplicity of
`illustration only one row line R and one column select
`line Y5 are shown in FIGS. 2 and 3. A row line is select
`able based on row address information input to a one of
`sixteen row decoder stage 16 and a one of 256 row
`decoder stage 18 (See FIG. 2). There are l6 of the one
`of 256 stages 18, one for each sub-block 14. In each data
`block 12 column address decoders 20 turn on a select
`line Y5 to control read/write data transfer for two col
`umns.
`The four sub-columns in a sub-block that are associ
`ated with each select line Y5 are grouped in pairs for
`independent and parallel data l/O along one of two,
`2-bit wide, local data paths Cj/o. FIG. 3 illustrates two
`such paths. designated cum and Cl/oq. Path CI/m
`comprises two pairs of data lines D1, D1 and D2, D5
`each pair providing one bit of information. Sin_1_ilarly
`path CV03 comprises two pairs of data lines D3, D3 and
`D4. Ii.
`Lines D1, D3. D3 and D4 are connected by transistors
`310, 312. 314 and 316__t_o_re_ce_i_\ie signals from bitline
`segments BL and lines D1, D3, D3 and Etare connected
`by transistors 318, 320. 322 and 324 to receive comple
`mentary signals from bitline segments a‘. Thus each
`pair of bitlines, in the four subcolumns of a sub-block
`that are associated with a particular selg:_t line Y5, is
`paired to one of the data line pairs D,-, D1. A four-bit
`wide global data path connects the local paths in each
`sub-block 14 of a logical data block 12 to the data I/O
`buffers 21. Thus, when a row of memory cells in a
`particular sub-block is addressed and a select line Y5is
`also addressed, data is simultaneously transfered be
`tween four memory cells within two adjacent pairs of
`sub-columns SC and the I/O buffers 21.
`For this exemplary DRAM embodiment the row
`45
`decoding arrangement enables simultaneous transfer of
`data to or from one sub-block 14 in each of the four data
`blocks 12 at a given time. The column select arrange
`ment provides X 4 output from each data block 12.
`Thus the I/O buffers 21 could provide 16 bit parallel
`I/O.
`During a data transfer operation row address signals
`RAO through RA11 and column address signals CAO
`through CA1] are input in conventional time-multi
`plexed manner being latched into row and column ad
`dress buffers 22 and 24 according to timing signals R_A_S
`and CAS. See FIG. 1. Based on 4 bits of row address
`information RAO through RA3, the first row decoder
`stage 16 selects one of the 16 sub-blocks in each of the
`data blocks 12. The second row decoderstage 18 selects
`one of the 256 rows within each selected sub-block
`based on the remaining 8 bits of row address informa
`tion RA4 through RA11. The decoder circuitry 20
`receives eight bits of column address data. A0 through
`A7, to provide a logic~high signal along one of the 256
`select lines Y5 in a data block 12. With this selection the
`data block provides four bits of data on a pair of 2-bit
`paths CJ/O associated with the accessed sub-block. The
`
`35
`
`55
`
`60
`
`65
`
`5,126,973
`
`a. 5
`
`40
`
`6
`next two bits of column address data CA8 and CA9 can
`be applied in any of several well known decoder circuit
`arrangements to vary the output of the data block from
`X 1 to X 4.
`The memory array of each data block 12 includes, in
`addition to the 4,194,304 cells arranged along 1024 col
`umns C, a predetermined number of redundant columns
`RC. Data I/O of the memory cells such as redundant
`memory cell 309 in each column RC is controlled by a
`redundant column select line YR5. One redundant col
`umn select line YR5is illustrated in FIG. 2. In principle,
`the number of redundant columns RC provided in each
`data block can be sufficient to maximize the yield of a
`production lot. On the other hand, given typical space
`constraints, it is desirable that individual data blocks in
`the device 10 comprise less than ?ve redundant select
`lines YRS.
`As further illustrated for the sub-block 14 of FIG. 3,
`the redundant columns RC are formed as pairs of redun~
`dant sub-columns RSC and a redundant column select
`line YRS is connected to access data from each sub
`column pair. All of the sub-blocks 14 in a data block 12
`include the same number of redundant column selects.
`Recalling that the four sub-columns SC associated
`with each select line Y5 in a sub-block 14 are also ar
`ranged in pairs, portions of each pair of redundant col~
`umns can be wired to replace one or more portions of a
`pair of subcolumns in a column C. In order to substitute
`defective memory cells with functioning cells, memory
`cells in each redundant column are arranged along the
`4,096 rows of a data block 12 with each cell connected
`to a different row line so that all cells in a redundant
`column can be accessed with the row address decoder
`stages 16 and 18.
`As schematically illustrated in FIG. 3, each redun
`dant select line YR5 enables data transfer between each
`of two constituent subcolumns RSC in a sub-block and
`a pair of data lines Di, E associated with each of the
`paths Cl/m and Cj/OZ. More specifically, a logic-high
`signal on redundant select YR51 connects each pair of
`folded bitline segments in the two selected redundant
`sub-@umns RSC_|and RSC2 to the pairs of data lines
`D1, D1 and D4, D4 through gating transistors 330, 332,
`334 and 336. For example, a logic high signal on select
`line YR51 will COI‘IIECI the bitline segments of RCS1 to
`data lines D1 and D1 and will connectlhe bitline seg
`ments of RCSZ to data lines D4 and D4. During this
`transfer period all of the sub-colurlis SC in the sub
`block 14 are disconnected from D1, D1 and D4, D4. This
`disconnection occurs through action of the outputs of
`inverters 338 and 340 turning off pass transistors 342,
`344, 346 and 348. Similarly a logic high signal on select
`line YRS; will conrgt the bitline segments of RCS3 to
`data lines D; and D2 and will connect the bitline seg
`ments of RCS4 to data lines D3 and T53 through gating
`transistors 350, 352, 354 and 356. The outputs of invert
`ers 358 and 360 disconnect_all of the sub-columns SC in
`the sub-block 14 from D2, D2 and D3, D3, through gating
`transistors‘ 362, 364, 366 and 368.
`With this arrangement column repair decode cir
`cuitry can advantageously incorporate a level of row
`decoding in order to replace defective sections of col
`umns C with equivalent sections of redundant columns
`RC. In a simple implementation of this replacement
`procedure corresponding sections of columns C and
`redundant columns RC are responsive to the same level
`of row decoding. For the device 10 a comparator is
`programmed to replace a subcolumn pair, or a column
`
` 14
`
`

`
`5,126,973
`7
`segment of subcolumn pairs spanning multiple sub
`blocks 14, with a corresponding section ofa redundant
`column.
`Such segmentation is useful for allocating two or
`more portions of the same redundant column for repair
`of multiple defects occuring in different column seg
`ments, e.g., occurring in sections of memory having
`different column addresses. In the example implementa
`tion of the replacement procedure for the device 10,
`with a given level of row decoding each pair of column
`sections which is to be replaced must be identi?able
`with different row address data. When two or more
`defective sections in different pairs of column sections
`are identi?ed with the same row address information, a
`different redundant column RC will be required to
`replace each of these. Otherwise, as long as sufficient
`row decoding is provided to associate each of the col
`umn sections which is to be replaced with a different
`section in the repair column, a single redundant column
`can be segmented to replace all column sections con
`taining the defects in a data block 12. Generally, one
`redundant column RC can be used to eliminate defects
`occuring in multiple columns.
`The feature of decoding row address information in
`25
`the column repair circuitry increases the number of
`repairs which can be made with a given number of
`redundant columns RC. For example, with a one of
`?fteen comparator decoder (receiving eight bits of col
`umn and three bits of row address information) any one
`of 8 segments in a redundant column RC can be pro
`grammed to replace any one of eight corresponding
`column segments in any of the four data blocks 12.
`Alternately, with a one of sixteen comparator decoder
`(receiving eight bits of column and four bits of row
`address information) the redundant columns RC can be
`segmented into sixteen sections each corresponding to a
`different pair of sub-columns SC in a different one of
`sixteen sub-blocks 14.
`To effect substitution of redundant column cells for
`defective cells, the column repair decode circuitry in
`cludes a plurality of fusible comparator decoders 40.
`Typically the a decoder 40, shown schematically in
`FIG. 4. will include a number of input circuits 41 each
`wired to receive an address signal and its complement.
`Given n column address signals provided to the address
`buffers 24 and 111 row address signals provided to the
`address buffers 22, the decoder 40 includes n-x input
`circuits for receiving column address signals and m-y
`input circuits for receiving row address signals. The
`value ofx corresponds to the number of columns C in a
`data block 12 and the value of y will depend on the
`desired level of segmentation. Each address input cir
`cuit 41 includes a fuse F for programming the decoder
`with the row or col-umn address information needed to
`substitute one segment of memory cells along one re
`dundant select line YRS in a data block for a defective
`segment of memory cells in a column C ofthe same data
`block.
`The number of column repairs which can be made on
`the entire device 10 is equal in count to the total number
`of comparator decoders. As illustrated schematically in
`FIG. 5 the decoders 40 are arranged in segment select
`groups S5,. Assuming that each data block 12 has the
`same number of redundant columns RC, all of the de
`coders 40 in a particular group SSiare wired to turn on
`the same redundant select line YR5,-(i = l, N) in all ofthe
`data blocks.
`
`8
`For a given level of row decoding in the decoders 40
`any one ofa predetermined number of sections within a
`repair column is addressable in the manner described
`above to replace a defective section along one of the 256
`column select lines in any one of the four data blocks.
`Thus by programming a decoder 40, a section in a re
`dundant column is de?nable with a combination of row
`address information to replace a defective section in one
`of the data blocks. One of four data block select logic 42
`presents a second stage of fusible decoders for identify
`ing the data block to which each decoder 40 is to be
`dedicated.
`All of the second stage decoders in the logic block 42
`include input circuits 41, like those of the decoders 40,
`receiving column address bits CA10 and CA1] to effect
`the one of four selection. Of course, in other redun
`dancy schemes the decoders of block 42 could provide
`a higher level of selection in order to allocate sections of
`the redundant columns RC to portions of the data
`blocks 12. For example, different redundant columns
`could be assigned to each half of each data block with
`the decoders in each group SS,- wired to turn on the
`same redundant select line YRS in each data half block.
`With this partitioning the second stage of decoders 42
`would include fusible circuits for dedicating each de
`coder 40 within each group 88; to a particular half
`block.
`In the present embodiment the second stage of decod
`ers 42 provides a one of four selection and the number
`of seg