UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC,
`Patent Owner.
`____________________
`
`Case IPR2016-01567
`U.S. Patent No. 5,894,441
`____________________
`
`DECLARATION OF DR. PINAKI MAZUMDER IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW
`
`
`
`
`
`Apple – Ex. 1001
`Apple Inc., Petitioner
`1
`
`

`
`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1 
`
`INTRODUCTION ......................................................................................... .. 1
`
`TABLE OF CONTENTS
`
`BACKGROUND AND QUALIFICATIONS ................................................. 1 
`BACKGROUND AND QUALIFICATIONS ............................................... ..l
`
`I. 
`
`II. 
`
`III.  ASSIGNMENT AND MATERIALS REVIEWED ........................................ 9 
`
`AS SIGl\H\/[ENT AND MATERIALS REVIEWED ...................................... ..9
`
`III.
`
`IV.  UNDERSTANDING OF THE LAW ............................................................ 10 
`
`UNDERSTANDING OF THE LAW .......................................................... ..lO
`
`IV.
`
`A.  Anticipation ......................................................................................... 10 
`A.
`Anticipation ....................................................................................... .. 10
`
`B. 
`
`B.
`
`C. 
`
`C.
`
`Obviousness ......................................................................................... 10 
`
`Obviousness ....................................................................................... .. 10
`
`Claim Construction ............................................................................. 12 
`
`Claim Construction ........................................................................... ..l2
`
`V. 
`
`LEVEL OF ORDINARY SKILL IN THE ART ........................................... 13 
`
`LEVEL OF ORDINARY SKILL IN THE ART ......................................... .. 13
`
`VI.  TECHNOLOGY BACKGROUND ............................................................... 14 
`
`TECHNOLOGY BACKGROUND ............................................................. .. 14
`
`VI.
`
`A.  DRAM Memory Cell .......................................................................... 14 
`A.
`DRAM Memory Cell ........................................................................ .. 14
`
`B. 
`
`B.
`
`C. 
`C.
`
`Basics of DRAM Architecture ............................................................ 15 
`
`Basics of DRAM Architecture .......................................................... .. 15
`
`An Architectural Snapshot of a Multi-Bank DRAM Chip ................. 17 
`An Architectural Snapshot of a Multi-Bank DRAM Chip ............... .. 17
`
`D.  DRAM Chip Size Growth and Yield .................................................. 24 
`D.
`DRAM Chip Size Growth and Yield ................................................ ..24
`
`E. 
`E.
`
`F. 
`F.
`
`G. 
`G.
`
`H. 
`H.
`
`Using Spare Memory Cells to Replace Defective Cells ..................... 26 
`Using Spare Memory Cells to Replace Defective Cells ................... ..26
`
`Redundancy Techniques for Word Lines ............................................ 30 
`Redundancy Techniques for Word Lines .......................................... ..3O
`
`Redundancy Technique for Bit Lines ................................................. 34 
`Redundancy Technique for Bit Lines ............................................... ..34
`
`Redundancy Techniques in Commercial DRAM Devices ................. 35 
`Redundancy Techniques in Commercial DRAM Devices ............... ..35
`
`VII.  THE ’441 PATENT ....................................................................................... 36 
`
`THE ’44l PATENT ..................................................................................... ..36
`
`VII.
`
`A. 
`A.
`
`B. 
`
`B.
`
`C. 
`C.
`
`Background ......................................................................................... 36 
`Background ....................................................................................... . .3 6
`
`The Admitted Prior Art ....................................................................... 39 
`
`The Admitted Prior Art ..................................................................... ..39
`
`The Alleged Invention ......................................................................... 44 
`The Alleged Invention ....................................................................... ..44
`
`
`
`
`
`i
`
`i
`
`2
`
`

`
`VIII.  THE CHALLENGED CLAIMS ................................................................... 51 
`
`IX.  PRIOR PROSECUTION ............................................................................... 54 
`
`A.  Original Prosecution ............................................................................ 54 
`
`B. 
`
`Inter Partes Review............................................................................. 54 
`
`X.  DESCRIPTION OF PRIOR ART ................................................................. 56 
`
`U.S. Patent No. 5,265,055 (“Horiguchi”) ................................. 56 
`1. 
`U.S. Patent No. 5,126,973 (“Gallia”) ....................................... 65 
`2. 
`XI.  PATENTABILITY ANALYSIS ................................................................... 75 
`
`A.  Horiguchi Discloses Each of the Limitations of Claims 6-
`12, 14 and 15 ....................................................................................... 75 
`
`Horiguchi Anticipates Independent Claim 6 ............................ 75 
`1. 
`Horiguchi anticipates dependent claim 7 .................................. 86 
`2. 
`Horiguchi anticipates dependent claim 8 .................................. 89 
`3. 
`Horiguchi anticipates dependent claim 9 .................................. 91 
`4. 
`Horiguchi anticipates dependent claim 10 ................................ 93 
`5. 
`Horiguchi anticipates dependent claim 11 ................................ 96 
`6. 
`Horiguchi anticipates dependent claim 12 ................................ 98 
`7. 
`Horiguchi anticipates dependent claim 14 ..............................100 
`8. 
`Horiguchi anticipates dependent claim 15 ..............................101 
`9. 
`Gallia Discloses Each of the Limitations of Claims 6, 7,
`9, 11, 12, 14, and 15 .......................................................................... 102 
`
`1. 
`2. 
`3. 
`4. 
`5. 
`6. 
`7. 
`
`Gallia anticipates independent claim 6 ...................................102 
`Gallia anticipates dependent claim 7 ......................................115 
`Gallia anticipates dependent claim 9 ......................................117 
`Gallia anticipates dependent claim 11 ....................................119 
`Gallia anticipates dependent claim 12 ....................................120 
`Gallia anticipates dependent claim 14 ....................................123 
`Gallia anticipates dependent claim 15 ....................................124 
`
`B. 
`
`
`
`
`
`ii
`
`3
`
`

`
`C. 
`
`Gallia in view of Horiguchi Discloses Each of the
`Limitations of Claims 8 and 10 ......................................................... 126 
`
`1. 
`
`2. 
`
`3. 
`
`Gallia and Horiguchi disclose every limitation of dependent
`claim 8 .....................................................................................126 
`Gallia and Horiguchi disclose every limitation of dependent
`claim 10 ...................................................................................127 
`A person of ordinary skill in the art would have been motivated
`to combine the teachings of Gallia and Horiguchi, rendering
`claims 8 and 10 obvious ..........................................................130 
`
`
`
`iii
`
`
`
`
`
`4
`
`

`
`EXHIBITS
`
`Exhibit #
`
`Exhibit Description
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`Declaration of Dr. Pinaki Mazumder
`
`Curriculum Vitae of Dr. Pinaki Mazumder
`
`U.S. Patent No. 5,894,441
`
`File History for U.S. Patent No. 5,894,441
`
`U.S. Patent No. 5,265,055 to Horiguchi
`
`U.S. Patent No. 5,126,973 to Gallia
`
`Inter Partes Review No. IPR2016-00094, Petition for Inter Partes
`Review filed October 27, 2015 (without exhibits)
`
`U.S. Patent No. 5,270,975 to McAdams
`
`Japanese Patent Appl. No. H06-052696 to Minami
`
`Inter Partes Review No. IPR2016-00094, Patent Owner’s
`Preliminary Response filed January 27, 2016
`
`Inter Partes Review No. IPR2016-00094, Decision Denying
`Institution filed April 12, 2016
`
`1012
`
`U.S. Patent No. 5,956,285 to Watanabe
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`Masashi Horiguchi et al., A Flexible Redundancy Technique for High-
`Density DRAMs, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26,
`No. 1, Jan. 1991, at 12-17
`
`U.S. Patent No. 5,267,214 to Fujishima
`
`U.S. Patent No. 5,349,556 to Lee
`
`U.S. Patent No. 5,355,339 to Oh
`
`U.S. Patent No. 5,359,560 to Suh
`
`U.S. Patent No. 5,798,974 to Yamagata
`
`
`
`
`
`iv
`
`5
`
`

`
`1019
`
`U.S. Patent No. 5,808,948 to Kim
`
`1020
`
`Masashi Horiguchi, Redundancy Techniques for High-Density
`DRAMs, INNOVATIVE SYSTEMS IN SILICON CONFERENCE, Oct. 1997, at
`22-29
`1021 Masashi Horiguchi et al., NANOSCALE MEMORY REPAIR (Springer
`2011)
`
`1022
`
`Robert T. Smith et al., Laser Programmable Redundancy and Yield
`Improvement in a 64 K DRAM, IEEE JOURNAL OF SOLID-STATE
`CIRCUITS, VOL. SC-16, NO. 5, Oct. 1981, at 506-14
`
`
`
`
`
`v
`
`6
`
`

`
`I, Pinaki Mazumder, hereby declare:
`
`I.
`1.
`
`INTRODUCTION
`
`I have been retained by Apple Inc. (hereinafter “Apple”) to serve as a
`
`technical expert and provide expert opinions relating to U.S. Patent No. 5,894,441
`
`(hereinafter “’441 Patent”) (Ex. 1003), including opinions on the validity of the
`
`’441 Patent in support of Apple’s petition for inter partes review.
`
`2.
`
`I am being compensated for my time at a rate of $350 per hour. My
`
`compensation is in no way dependent on the substance of the opinions I have
`
`offered below, or upon the outcome of Apple’s petition for inter partes review (or
`
`the outcome of the inter partes review, if trial is instituted).
`
`II. BACKGROUND AND QUALIFICATIONS
`3.
`I received my PhD in Electrical and Computer Engineering from the
`
`University of Illinois at Urbana-Champaign in 1988. Prior to that, I received my
`
`MS degree in Computer Science from University of Alberta in Canada, BS degree
`
`in Electrical Engineering from Indian Institute of Science at Bangalore, and BSc
`
`Physics Honors degree from Guwahati University in India.
`
`4.
`
`Currently, I am a Professor of Electrical Engineering and Computer Science
`
`at the University of Michigan where I have been teaching for the past 25 years. I
`
`spent 3 years at National Science Foundation serving as the lead Program Director
`
`of Emerging Models and Technologies Program in the CISE Directorate as well as
`
`
`
`
`
`1
`
`7
`
`

`
`a Program Director in the Engineering Directorate. I had worked for 6 years in
`
`industrial R&D laboratories that included AT&T Bell Laboratories in USA and
`
`Bharat Electronics Ltd. in India. I spent my sabbatical at Stanford University,
`
`University of California at Berkeley, and NTT Center Research Laboratory in
`
`Japan.
`
`5.
`
`In 1985, when I joined the University of Illinois for my PhD, I was recruited
`
`to work in a Semiconductor Research Corporation (SRC) research project to
`
`develop new testing methodologies for semiconductor memory chips. At that time,
`
`commercial test equipment used simple functional testing methods to detect
`
`rudimentary manufacturing defects, and the university research was primarily
`
`confined in refinement of functional test algorithms. Since I had worked six years
`
`in industrial R&D laboratories after my BS degree, I had recognized the need for
`
`new way of accelerated memory chip testing with the aggressive increase in
`
`density of integration.
`
`6.
`
`I studied the DRAM architecture while doing my PhD and proposed the
`
`concept of internal testing by introducing a new method called “in-line” testable
`
`design, where a single word-line address was asserted to access up to 50% of
`
`memory cells on a word line to write the same data on those cells. To read the
`
`contents of those memory cells in one memory cycle, an internal “parallel 0/1
`
`detector” was invented to verify whether all the cells that were written in one
`
`
`
`
`
`2
`
`8
`
`

`
`memory write cycle, preserves the same data bit after several other READ and
`
`WRITE operations performed on other memory cells. While the row decoder was
`
`retained unaltered to access one word line at a time, the “column address decoder”
`
`was modified in order to allow the access to 100’s of bit lines in the test mode.
`
`This design for testability technique was utilized to accelerate the test procedures
`
`and reduce memory testing cost significantly. I combined the concepts of VLSI
`
`process technology, memory layout, circuit design, and mathematical techniques
`
`like graph theory and Markov chain modeling to develop comprehensive
`
`accelerated test procedures for the testable memory. This is explained in the
`
`synopsis of my doctoral thesis, which is included in my Curriculum Vitae (“CV”).
`
`Ex. 1002.
`
`7.
`
`After I joined the University of Michigan in 1987, I continued working on
`
`testing and fault-tolerance of high-density semiconductor random-access memories
`
`that resulted in numerous publications of archival journal papers and two books on
`
`testing and reliability of high-density semiconductor memories (“Testing and
`
`Testable Design of Random-Access Memories,” Kluwer Academic Publishers,
`
`1996, 428 pages, and “Fault Tolerance and Reliability Aspects of Random-Access
`
`Memories,” Prentice Hall, 2002, 440 pages). These two books are widely used by
`
`VLSI practicing engineers as well as academic researchers even several years after
`
`their publication. Amongst several new research ideas my students and I proposed
`
`
`
`
`
`3
`
`9
`
`

`
`during the period from 1987 to 1997 include efficient memory test algorithms,
`
`built-in self-testing of memories, on-chip error correction of semiconductor
`
`memory, self-healing techniques for memories, self-repairable RAM compiler that
`
`generates memory layout automatically, and ultra-low power CMOS memories for
`
`wearable products (see Publications: 10-21, 23-26, 46, 47, 62, 77, 94, 96-100, 126,
`
`128, 130, 131, 133, 135-137, 142, 146, 155, 166, 179-182, 185, 219, 226, 237, 279,
`
`301-303 in my CV).
`
`8.
`
`Besides working on conventional CMOS static random-access memory
`
`(SRAM) and dynamic random-access memory (DRAM) technologies, my research
`
`group has also performed extensive research in emerging memory technologies
`
`such as nonvolatile resistive random-access memory (Publications: 82 and 279 in
`
`my CV), magnetoresistive random-access memory (Publications: 94, 96-100 in my
`
`CV), and resonant tunneling memory (Publications: 36, 80, 208, 237 and 239 in
`
`my CV). My research group had conducted extensive research in quantum
`
`tunneling technologies and we had designed new type of storage devices to
`
`improve speed and reduce power consumption.
`
`9.
`
`I have published over 280 technical papers and 4 books on various aspects of
`
`VLSI technology and systems. My research interest includes CMOS VLSI design,
`
`semiconductor memory systems, CAD tools and circuit designs for emerging
`
`technologies including quantum MOS, spintronics, plasmonics, and resonant
`
`
`
`
`
`4
`
`10
`
`

`
`tunneling devices.
`
`10.
`
`I was a recipient of Digital’s Incentives for Excellence Award, BF Goodrich
`
`National Collegiate Invention Award, and DARPA Research Excellence Award.
`
`11.
`
`I am a 2007 Fellow of American Association for the Advancement in
`
`Science (AAAS) for my “distinguished contributions to the field of very large
`
`scale integrated (VLSI) systems.” The honor of being elected a Fellow of AAAS
`
`is given to those whose “efforts on behalf of the advancement of science or its
`
`applications are scientifically or socially distinguished.”
`
`12.
`
`I am also a 1999 Fellow of IEEE for my “contributions to the field of VLSI
`
`Design.”
`
`13. Over the course of the past 29 years, I have secured 51 research contracts
`
`from National Science Foundation, Air Force Office of Scientific Research, Office
`
`of Naval Research, Army Research Office, Defense Advanced Research Projects
`
`Agency, State of Michigan, and several private sources. The aggregated amount of
`
`these grants exceeds $11 Million for my individual share and about $40 Million for
`
`co-investigators work on these grants.
`
`14. For the past 29 years, I have been teaching at the Department of Electrical
`
`Engineering and Computer Science of the University of Michigan, Ann Arbor,
`
`Michigan, where I taught the following courses more frequently: 1) VLSI System
`
`Design, 2) Optimization and Synthesis of VLSI Layout, 3) Introduction to Digital
`
`
`
`
`
`5
`
`11
`
`

`
`Logic Design, and 4) Digital Integrated Circuit Design. Besides these courses, I
`
`introduced three advanced level graduate courses: 5) Circuits and Architectures for
`
`Nanodevices, 6) Ultra-Low-Power Subthreshold CMOS Circuits, and 7) Terahertz
`
`Technology and Applications.
`
`15. The IEEE Electron Devices Society recognized me as an IEEE
`
`Distinguished Lecturer. I presented over 70 invited talks at universities and
`
`companies around the world.
`
`16. Below is an exemplary list of inventions of mine that have either been
`
`awarded as US patents or are currently under review by the USPTO (a full list is in
`
`my CV):
`
`
`
`US Patent on Adaptive Reading and Writing of a Resistive Memory,
`
`US Patent No. 9,111,613, awarded on Aug. 18, 2015, (Inventors: P.
`
`Mazumder and E. Idong; Patent Assigned to Regents of University of
`
`Michigan).
`
`
`
`US Patent on High-Speed, Compact, Edge-Triggered Flip-Flop
`
`Circuit Topologies Using NDR Diodes and FET’s, US Patent No.
`
`6,323,709, awarded on Nov. 21, 2001, (Inventors: S. Kulkarni and P.
`
`Mazumder; Patent Assigned to Regents of University of Michigan).
`
`
`
`US and International Patents on Method and Apparatus to Improve
`
`Noise Tolerance of Dynamic Circuits, US Patent No. 7,088,143,
`
`
`
`
`
`6
`
`12
`
`

`
`awarded on Aug. 8, 2006, (Inventors: L. Ding and P. Mazumder;
`
`Patent Assigned to Regents of University of Michigan).
`
`
`
`US Patent Provisional Application filed on Memristor Crossbar
`
`Memory for Hybrid Ultra Low Power Hearing Aid Speech Processor,
`
`(Inventors: J. Shah, P. Mazumder and M. Barangi).
`
`
`
`US Patent on Static Random Access Memory Cell having Improved
`
`Write Margin for use in Ultra-Low Power Application, International
`
`application number: PG/US 13/78262, (Inventors: P. Mazumder, Z.
`
`Nan and J. Kim).
`
`
`
`Invention disclosure for Yield Improvement of VLSI Chips by Using
`
`Electronic Neural Networks for Built-in Self-Repair, Feb. 15, 1990,
`
`(Inventor: P. Mazumder).
`
`
`
`Invention disclosure for A Zero-Delay Overhead Circuit Technique
`
`for Built-in Self-Repair of Random-Access Memories, Oct. 17, 1996,
`
`(Inventors: K. Chakraborty and P. Mazumder).
`
`17. A few papers on relevant subject areas authored or co-authored by me are
`
`listed below. Notably, the first three publications are pertaining to redundancy and
`
`repair of DRAM chips, which is the main goal of the ’441 Patent. A complete list
`
`of my publications are in my CV.
`
`
`
`A New Built-In Self-Repair Approach to VLSI Memory Yield
`
`
`
`
`
`7
`
`13
`
`

`
`Enhancement by Using Neural-Type Circuits, IEEE Transactions on
`
`Computer Aided Design of Integrated Circuits and Systems, Vol. 12,
`
`No. 1, January 1993, pp. 124-136.1
`
`
`
`Analysis and Design of Hopfield-type Network for Built-in Self-
`
`Repair of Memories, IEEE Transactions on Computers, Vol. 45, No.
`
`1, Jan. 1996, pp. 109-115.2
`
`
`
`BISRAMGEN: A Built-In Self-Repairable SRAM and DRAM
`
`Compiler, IEEE Transactions on VLSI Systems, Vol. 9, No. 2, Apr.
`
`2001, pp. 352-364.3
`
`
`
`Parallel Testing of Parametric Faults in a Three-Dimensional
`
`Dynamic Random-Access Memory, IEEE Journal of Solid-State
`
`Circuits, Vol. 23, No. 4, August 1988, pp. 933-942.
`
`
`
`Design of a Fault-Tolerant Three-Dimensional Dynamic Random-
`
`Access Memory with On-Chip Error-Correcting Circuit, IEEE
`
`
`1
`In this paper, I have described an efficient redundancy technique that allows
`a DRAM chip with multiple scattered defective cells to be reconfigured in order to
`improve the yield to nearly 100% from below 30% if there is no redundancy
`incorporated in the DRAM chip.
`2
`In this paper, I have shown how the reconfiguration technique described in
`the above paper can be implemented very efficiently inside a DRAM chip using
`digital circuits so that the chip can self-heal in the presence of manufacturing
`defects as well as failures occurring during to the operation of the chip.
`3
`In this paper, I have shown how redundancy circuits can be automatically
`incorporated in a memory compiler by using the address remapping technique in
`the form of a table look-aside buffer (TLB). This is a soft repair technique.
`
`
`
`
`
`8
`
`14
`
`

`
`Transactions on Computers, Vol. 42, No. 12, December 1993, pp.
`
`1453-1468.
`
`
`
`Design and Analysis of Resonant-Tunneling-Diode (RTD) Based
`
`High Performance Memory System, IEICE Trans. Electronic, Vol.
`
`E82-C, No. 9, September 1999, pp. 1630-1637.
`
`
`
`Performance Modeling of Resonant Tunneling-Based Random-Access
`
`Memories, IEEE Transactions on Nanotechnology, Vol. 4, No. 4, July
`
`2005, pp. 472-480.
`
`III. ASSIGNMENT AND MATERIALS REVIEWED
`18.
`I have been asked to provide opinions regarding the patentability of the ’441
`
`Patent. Specifically, I have been asked to provide an opinion as to whether every
`
`limitation of claims 6-12, 14, and 15 are disclosed to one of ordinary skill in the art
`
`by, or in the alternative, whether claims 6-12, 14, and 15 would have been obvious
`
`in view of, U.S. Patent No. 5,265,055 (“Horiguchi”) (Ex. 1005) and/or U.S. Patent
`
`No. 5,126,973 (“Gallia”) (Ex. 1006).
`
`19. The opinions expressed in this declaration are not exhaustive of my opinions
`
`on the patentability of claims 6-12, 14, and 15 of the ’441 Patent. Therefore, the
`
`fact that I do not address a particular point should not be understood to indicate any
`
`opinion on my part that any claim otherwise complies with the patentability
`
`requirements.
`
`
`
`
`
`9
`
`15
`
`

`
`20.
`
`In forming my opinions, I have reviewed the ’441 Patent, the prosecution
`
`history of the ’441 Patent (Ex. 1004), and the inter partes review history relating to
`
`the ’441 Patent (Ex. 1007-1011).
`
`21.
`
`I am familiar with the prior art and the knowledge of one of ordinary skill in
`
`the art at the relevant time. I specifically have analyzed Horiguchi and Gallia, and
`
`have reviewed the various references cited in this declaration.
`
`IV. UNDERSTANDING OF THE LAW
`A. Anticipation
`I have been informed that, under 35 U.S.C. § 102, for a claim to be invalid
`
`22.
`
`as “anticipated,” every limitation of the claim must be found in a single prior art
`
`reference, either expressly or inherently.
`
`B. Obviousness
`I also have been informed that, under 35 U.S.C. § 103, where each and every
`
`23.
`
`element is not present in a single reference, a claim may still be invalid as
`
`“obvious” if the differences between the subject matter sought to be patented and
`
`the prior art are such that the subject matter as a whole would have been obvious at
`
`the time the invention was made to a person having ordinary skill in the art to
`
`which said subject matter pertains. I understand that the following factors must be
`
`evaluated to determine whether the claimed subject matter is obvious: (1) the scope
`
`and content of the prior art; (2) the difference or differences, if any, between each
`
`claim of the patent and the prior art; and (3) the level of ordinary skill in the art at
`
`
`
`
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`10
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`16
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`

`
`the time the patent was filed.
`
`24.
`
`I understand that obviousness may be shown by considering more than one
`
`item of prior art and by considering the knowledge of a person having ordinary
`
`skill in the art and that obviousness may be based on various rationales, including:
`
`
`
`
`
`
`
`
`
`
`
`
`
`Combining prior art elements according to known methods to yield
`
`predictable results;
`
`Simple substitution of one known element for another to obtain
`
`predictable results;
`
`Use of known techniques to improve similar devices (methods, or
`
`products) in the same way;
`
`Applying a known technique to a known device (method, or product)
`
`ready for improvement to yield predictable results;
`
`“Obvious to try” – choosing from a finite number of identified,
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`predictable solutions, with a reasonable expectation of success;
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`Known work in one field of endeavor may prompt variations of it for
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`use in either the same field or a different one based on design
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`incentives or other market forces if the variations are predictable to
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`one of ordinary skill in the art; and
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`
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`Some teaching, suggestion, or motivation in the prior art that would
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`have led one of ordinary skill to modify the prior art reference or to
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`combine prior art reference teachings to arrive at the claimed
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`invention.
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`25.
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`I also have been informed and I understand that when present so-called
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`“objective indicia” of non-obviousness, also known as “secondary considerations,”
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`like the following are also to be considered when assessing obviousness: (1)
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`commercial success; (2) long-felt but unresolved needs; (3) copying of the
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`invention by others in the field; (4) initial expressions of disbelief by experts in the
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`field; (5) failure of others to solve the problem that the inventor solved; and (6)
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`unexpected results. I also understand that there must be a nexus between the
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`claimed subject matter and the evidence of objective indicia of non-obviousness,
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`and that the evidence of objective indicia of non-obviousness must be
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`commensurate in scope with the claimed subject matter.
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`C. Claim Construction
`I have been informed that the claims of a patent subject to inter partes
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`26.
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`review are given their “broadest reasonable construction in light of the
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`specification.” I also have been informed that the words of the patent claims are to
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`be given their plain meaning in view of the specification as interpreted by one of
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`ordinary skill in the art.
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`27. Consistent with these guidelines, I believe that the ’441 Patent terms should
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`be construed to have their plain and ordinary meaning in view of the specification.
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`V. LEVEL OF ORDINARY SKILL IN THE ART
`28. A person of ordinary skill in the art of the ’441 Patent at the time of
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`invention in 1997 would have had a Bachelor of Science and Master's degree in
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`electrical engineering or computer engineering (or an equivalent subject) and three
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`to four years of post-graduate experience working with dynamic random access
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`memory systems, or a PhD in electrical engineering or computer engineering (or an
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`equivalent subject) and at least 1-2 years of post-graduate experience working with
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`such dynamic random access memory systems, or an equivalent amount of work
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`experience.4
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`29. The subject matter of the ’441 Patent relates to DRAM architecture, and the
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`ordinarily skilled artisan would have an understanding of DRAM yield modeling,
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`reconfiguration techniques deployed in DRAM for improving chip yield, tradeoffs
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`between reconfiguration overhead and yield improvement, and DRAM array
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`architecture. Based on my experience and education, I consider myself (as of no
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`I understand that in the previous IPR of the ’441 Patent, i.e., IPR2016-
`4
`00094, Petitioner MTI proposed that a person having ordinary skill in the art would
`be a person with a Bachelor of Science in electrical engineering, computer
`engineering, computer science or a closely related field, along with at least 2-3
`years of experience in the design of memory devices. In my experience, a person
`of ordinary skill would have a Bachelor of Science and a Master’s in electrical
`engineering (or an equivalent subject) or a PhD in electrical engineering (or an
`equivalent subject). Nonetheless, even if the person of ordinary skill had a
`Bachelor of Science in electrical engineering (or an equivalent subject) and at least
`2-3 years of experience in the design of memory devices, my conclusion regarding
`the patentability of claims 6-12, 14, and 15 of the ’441 Patent would not change.
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`later than 1988, and since) to be a person of at least ordinary skill in the art with
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`respect to the field of technology implicated by the ’441 Patent. To be clear, my
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`conclusions of obviousness relate to whether Claims 6-12, 14, and 15 as a whole
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`would have been obvious at the time of invention to a person of ordinary skill in
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`the art.
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`30.
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`In 1997, a person of ordinary skill in the art, as defined above, would have
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`been aware of and able to review and implement the teachings of the prior art like
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`(i) Horiguchi (U.S. Patent No. 5,265,055), with a priority date of December 27,
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`1991 and published November 23, 1993, (ii) Gallia (U.S. Patent No. 5,126,973),
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`with a priority date of February 14, 1990 and published June 30, 1992, which
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`anticipate or render obvious claims 6-12, 14, and 15 of the ’441 Patent.
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`VI. TECHNOLOGY BACKGROUND
`A. DRAM Memory Cell
`31. A Dynamic Random Access Memory (“DRAM”) cell is a compact memory
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`cell comprising one transistor and one capacitor (“1T1C”) (see diagram of DRAM
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`Basic Cell in Fig. 1 below).
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`DRAM Basic Cell
`WL
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`Hold State (WL=0)
`WL=0
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`Data
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`Q
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`Data
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`Write (Data is an input)
`WL=1 Q
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`Data
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`Q=1
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`++++++
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`−−−−−−
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`WL=0
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`Q=0
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`Data
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`Read (Data is an output)
`WL=1 Q
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`Data
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`Fig. 1. DRAM cell showing the storage of Logic 1 and Logic 0.
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`32. The DRAM cell is said to contain a logic value of “1” when the capacitor
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`contains a charge (Q=1), and “0” when the capacitor contains no charge (Q=0). As
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`denoted in Fig. 1, a logic value can be written to the cell by enabling the gate WL
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`(i.e., WL=1) of the access transistor. Conversely, while WL is held low (WL=0),
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`the cell holds its charge. A READ operation is performed by asserting WL (i.e.,
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`WL=1) to enable data to be read out through a sense amplifier. The WL terminal
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`is referred to as a “word line” or “row”, while the data terminal is connected to a
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`column, and is referred to as a “bit line.”
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`B.
`Basics of DRAM Architecture
`33. Fig. 2 below shows an exemplary 4x4 memory cell array along with its
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`peripheral components. The row (word line) addresses 0-3 and column (bit line)
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`addresses 0-3 are marked for each distinct row and column.
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`21
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`Fig. 2. Basic DRAM Architecture with 4x4 Memory Array.
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`34. To read the value stored in an arbitrary cell, for example the cell located at
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`the intersection of row 2 and column 3, a Row Address Strobe (“/RAS”) signal is
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`first asserted while the row address bits A0 and A1 are provided to an Address
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`Input Buffer, which then transfers them to a Row Decoder. If A0 = 0 and A1 = 1,
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`for instance, the Row Decoder will activate Row Address Line 2. When this row
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`(word line) is activated by the Row Decoder, all the access transistors connected to
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`it will turn ON, while all other access transistors on other word lines will remain
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`turned OFF. Therefore, all the memory cells on the word line will propagate their
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`charges via their respective Column Address Lines (or Column Select Lines) (bit
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`lines).
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`35. The associated Sense Amplifiers will be activated simultaneously to
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`determine the logic state of DRAM cells connected to Row Address Line 2. Once
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`the sense amplifiers are activated, a Column Address Strobe (“/CAS”) signal is
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`asserted and the Write Enable (“/WE”) is asserted to perform a READ operation.
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`At the same time, the column address is provided on address bits, A0 and A1 to the
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`Address Input Buffer, which then transfers them to the Column Decoder. If A0 = 1
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`and A1 = 1, for instance, the Column Decoder will activate Column Address Line
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`3. The logic state of the Sense Amplifier connected to this Column Address Line
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`will then be transferred to a data output buffer completing the read operation.
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`C. An Architectural Snapshot of a Multi-Bank DRAM Chip
`36. While the operation of a single memory cell is described above with
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`reference to Fig. 1, a modern Giga-bit DRAM chip with multiple memory banks
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`and memory array blocks is capable of higher-speed READ and WRITE operations
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`by incorporating fast pipeline interfaces, low power consumption, good noise
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`immunity, and redundancy circuits that help improve chip yield.