UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC,
`Patent Owner.
`____________________
`
`Case IPR2016-01567
`Patent No. 5,894,441
`____________________
`
`PETITIONER’S REQUEST FOR REHEARING
`UNDER 37 C.F.R. § 42.71(d)
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`
`
`1
`
`
`
`____________________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC,
`Patent Owner.
`____________________
`
`Case IPR2016-01567
`Patent No. 5,894,441
`____________________
`
`PETITIONER’S REQUEST FOR REHEARING
`UNDER 37 C.F.R. § 42.71(d)
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`1
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`
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`
`
`I.
`
`INTRODUCTION
`
`On January 18, 2017, the Board issued a Decision denying institution of
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`inter partes review of U.S. Patent No. 5,894,441 (“the ’441 patent”) on Petitioner’s
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`Ground 1. Paper No. 11 (“Decision”) at 9. In Ground 1, Petitioner contends that
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`claims 6-12, 14 and 15 of the ’441 patent are invalid under (pre-AIA) 35 U.S.C. §
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`102(b) because they are anticipated by U.S. Patent No. 5,265,055 (“Horiguchi”).
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`Paper No. 1 (“Petition”) at 4 & 26-51. In denying institution, the Board
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`erroneously concluded that Horiguchi did not teach the “plurality of column
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`selection lines” limitation of the semiconductor memory device described in
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`independent claim 6. Decision, 9. Petitioner requests rehearing seeking
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`reconsideration of Ground 1.
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`Horiguchi discloses multiple column selection lines, explicitly in its
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`specification and by using a well-known variable notation in its figures to represent
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`multiple lines. This disclosure is well understood by a person of ordinary skill in
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`the art because multiple column selection lines are required for even the most basic
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`dynamic random access memory (“DRAM”) devices to function. This is
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`confirmed by the unrebutted testimony of Dr. Pinaki Mazumder. Petitioner
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`respectfully submits that the Board overlooked this basic fact of DRAM
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`architecture in misapprehending the teachings of and contentions regarding
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`Horiguchi set forth in the Petition. As a result, the Board clearly erred in finding
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`2
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`
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`that Horiguchi discloses only a single column selection line and abused its
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`discretion in denying institution of the Petition.
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`II.
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`LEGAL STANDARD
`
`Under 37 C.F.R. § 42.71(d), a petitioner may request rehearing on a decision
`
`denying institution of inter partes review. A request for rehearing “must
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`specifically identify all matters the party believes the Board misapprehended or
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`overlooked, and the place where each matter was previously addressed in a motion,
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`an opposition, or a reply.” 37 C.F.R. § 42.71(d). When evaluating a request for
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`rehearing on a decision, the Board will review the decision for an abuse of
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`discretion. 37 C.F.R. § 42.71(c). An abuse of discretion occurs when a decision is
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`based on an “erroneous conclusion of law or clearly erroneous factual findings, or .
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`. . a clear error of judgment.” PPG Indus. Inc. v. Celanese Polymer Specialties
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`Co., 840 F.2d 1565, 1567 (Fed. Cir. 1988); see, e.g., Facebook, Inc. v. Software
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`Rights Archive, LLC, IPR2013-00478, Paper No. 31 (Apr. 14, 2014).
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`III.
`
`ARGUMENT
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`A. The Board failed to appreciate or overlooked the testimony
`from Dr. Mazumder regarding basic DRAM architecture.
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`The ’441 patent is directed to semiconductor memory with redundant
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`circuitry. Horiguchi discloses a semiconductor memory device “and, more
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`particularly a redundancy technique for a dynamic random access memory
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`(DRAM) having a storage capacity of 16 mega bits or more.” Petition, 26 (citing
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`3
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`
`
`
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`Horiguchi). As discussed in the technology background of Dr. Mazumder’s
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`Declaration, DRAM cells are compact memory cells, with each cell comprising
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`one transistor and one capacitor. Ex. 1001 (“Mazumder Decl.”) at ¶ 31. Dr.
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`Mazumder explained the basic structure of DRAM by referencing an exemplary
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`4x4 memory cell array along with its peripheral components. Id. at ¶ 33, Fig. 2.
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`
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`Each DRAM cell is located at the intersection of a word line and bit line,
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`each cell having its own unique address. Id. at ¶ 34. In the exemplary figure
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`above, the row (word line) addresses 0-3 and column (bit line) addresses 0-3 are
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`marked for each distinct row and column. Id. at ¶ 33, Fig. 2. Each memory cell in
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`the array is accessed by activating the respective Row Address Line (word line)
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`and Column Address Line (Column Selection Line) (bit line) in order to, for
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`example, read the value stored in the cell. Id. at ¶¶ 34-35. As depicted in the
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`4
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`
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`
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`figure, there are two address bits, A0 and A1, used to identify the location of a
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`particular memory cell, and there are four column selection lines, one for each
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`column of memory cells, that enable access to all memory cells in the array. Id. at
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`Fig. 2. Put mildly, the necessary existence of multiple column selection lines in
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`DRAM is well-known. Id. at ¶¶ 33-35, 76-77; see, e.g., Ex. 1006, 5:10-20.
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`Claim 6 of the ’441 patent recites these well-known structures of DRAM,
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`including the limitation “a plurality of column selection lines including at least a
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`first column selection line.” With respect to this claim limitation, the Petition
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`explains that Horiguchi (Ex. 1005, 22:7-10) in fact discloses multiple column
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`selection lines YS[j]: “[a]n output YS[j] of the Y-decoder is applied to each
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`memory mat through a wiring conductor which is indicated by a dot-dash line in
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`FIG. 26.” Petition, 30-31. Each memory mat includes an array of memory cells
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`disposed at the crossings of word lines and bit lines. Ex. 1005, 21:51-22:3;
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`Mazumder Decl., ¶¶ 117-118; Petition, 12-13. Horiguchi further explains, with
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`reference to Fig. 26 (shown below), that “[t]he present invention is specifically
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`effective for a semiconductor memory, in which a plurality of memory mats use
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`circuit means (for example, a Y-decoder and output lines thereof) in common,
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`such as the present embodiment.” Ex. 1005, 22:18-22 (emphasis added). The
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`multiple output lines from the Y-decoder are necessary to access all of the bit lines,
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`5
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`
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`and thus each memory cell, in the memory array. See Mazumder Decl., ¶¶ 117-
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`118; Petition, 12-13.
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`The Petition also explains, with citation to paragraphs 152-153 of Dr. Mazumder’s
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`testimony, that “j” is an iterative variable (i.e., j=0, 1, 2, …) and there are multiple
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`column selection lines disclosed in Horiguchi, one for each value of “j.” Petition,
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`
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`30-31.
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`Thus, Dr. Mazumder testified that the single column address decoder in
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`Horiguchi (i.e., the Y-decoder) activates a particular column selection line YS[j]
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`(out of a plurality of column selection lines). Id. at ¶¶ 117-118 & 152-153. Dr.
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`Mazumder further explained that Horiguchi discloses that there are nB column
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`address bits and 2nB bit lines in the array. Id. at 59 n.23, ¶¶ 117-118. Accordingly,
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`the Y-decoder in Horiguchi includes 2nB outputs (i.e., column selection lines)
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`6
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`
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`
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`corresponding to each of the 2nB bit lines of the memory array, and activates a
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`certain column selection line (e.g., YS[0], YS[1], … YS[2nB-1]) based on the
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`received column address bits in order to access the memory cell at that address. Id.
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`at ¶¶ 117-118. Specifically, Dr. Mazumder explained the connection between each
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`column selection line and the bit lines in each sub-array as follows:
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`Fig. 26 shows column selection lines YS[j] running horizontally
`through all of the sub-arrays 130-133. For each value of “j”, column
`selection line YS[j] selects bit line B[j,n] in each of the sub-arrays.
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`Mazumder Decl., ¶ 152 (emphasis added). Dr. Mazumder also explained how the
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`iterative notation of YS[j] (a commonly used variable notation) represents separate
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`column selection lines for different values of j, as shown in the annotated Fig. 26:
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`For ease of reference, column selection lines YS[0] (i.e., j=0) and
`YS[1] (i.e., j=1), where YS[0] selects at least bit lines B[0,0] in sub-
`array 130 and B[0,1] in sub-array 131, are shown in annotated Fig.
`26 above. Thus, by disclosing, for instance, column selection lines
`YS[0] and YS[1], where YS[0] selects at least bit lines B[0,0] and
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`
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`7
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`
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`B[0,1] when activated. Horiguchi discloses a plurality of column
`selection lines including at least a first column selection line; said
`first and second bit lines being selected when said first column
`selection line is activated.
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`Mazumder Decl., ¶ 153 (emphasis added).
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`In its Preliminary Response, the Patent Owner did not rebut the testimony of
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`Dr. Mazumder. The Patent Owner merely argued that the “annotated reproduction
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`of FIG. 26 . . . includes pink lines added by the Petition,” and misled the Board by
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`ignoring the testimony of Dr. Mazumder and falsely stating that “the Petition offers
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`no support whatsoever for the idea that there exists multiple column selection lines
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`YS[0] and YS[1] in Horiguchi.” Paper No. 8 (“Prelim. Resp.”) at 42.
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`Swayed by the Patent Owner, in the Decision, the Board found that:
`
`Petitioner does not offer sufficient, persuasive evidence for its
`contention that “Fig. 26 shows column selection lines YS[j] running
`horizontally through all of the sub-arrays 130-133” (Pet. 30).
`Comparing Petitioner’s annotated Figure 26 (Pet. 30) and Figure 26
`without annotations reveals that, although the first of the pink lines
`added by Petitioner corresponds to YS(j) in Horiguchi, the second of
`the pink lines does not have a corresponding column selection line YS
`in Figure 26.
`
`Decision, 8. The Board also stated that the language in Horiguchi regarding “an
`
`output YS[j]” is consistent with only a single output in Fig. 26. Id. at 8-9.
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`The fact that Fig. 26 of Horiguchi depicts an exemplary column selection
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`line, as opposed to all 2nB column selection lines, is not evidence that the other
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`column selection lines are not disclosed or do not exist. See, e.g., Ex. 1006, 5:10-
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`8
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`
`
`
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`20 (depicting a single YS “[f]or simplicity” instead of all 256 column select lines).
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`One of skill in the art would immediately recognize that the notation YS[j]
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`represented multiple column selection lines, one for each iteration of variable “j.”
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`See Kennametal, Inc. v. Ingersoll Cutting Tool Co., 780 F.3d 1376, 1381 (Fed. Cir.
`
`2015) (explaining that prior art can anticipate a claim even if it “does not expressly
`
`spell out” all the limitations arranged or combined as in the claim, if a person of
`
`skill in the art, reading the reference, would “at once envisage” the claimed
`
`arrangement or combination); see, e.g., 10X Genomics, Inc. v. Raindance Techs.
`
`Inc., IPR2015-01558, Paper No. 13 (Jan. 19, 2016). In short, to one of ordinary
`
`skill in the art, versed in basic DRAM architecture, Horiguchi, with its description
`
`of the Y decoder and its multiple “output lines thereof,” undisputedly discloses
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`multiple column selection lines.
`
`B.
`
`The Board’s
`inoperable.
`
`interpretation of Horiguchi renders
`
`it
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`The Board’s factual finding that Horiguchi discloses only one column select
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`line also is clearly erroneous because it renders the circuit in Horiguchi inoperable.
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`Specifically, were there only one column selection line, the Y-decoder in
`
`Horiguchi would only be able to access a single bit line (instead of a plurality of bit
`
`lines as Horiguchi contemplates). See Ex. 1005, 21:61-65. In addition, having one
`
`Y-decoder does not mean there is only one column selection line. On the contrary,
`
`Horiguchi discloses multiple output lines (i.e., column selection lines) from the Y-
`
`9
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`
`
`
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`decoder. Id. at 22:18-22 (“Y-decoder and output lines thereof”). The common Y-
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`decoder is used to select, with a particular column selection line (out of a plurality
`
`of column selection lines), a particular bit line (out of a plurality of bit lines) based
`
`on the column address bits received by the Y-decoder. Mazumder Decl., ¶¶ 34-35,
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`117-118, 152-153. For this reason also, the Board clearly erred in finding that “a
`
`column selection line YS[j]” referred to only one column selection line. See
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`Boston Scientific Corp. v. UAB Research Foundation, IPR2015-00918, Paper No.
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`14 (Mar. 7, 2016) (granting rehearing request and instituting inter partes review
`
`where the Board’s analysis was based on an erroneous fact).
`
`C. The Board misapprehended the connection between the
`variable “j” in the bit lines expression “B[j,n]” and the same
`variable “j” in the column selection lines expression “YS[j]”
`in Horiguchi.
`
`The Board also erred in misapprehending the connection between the
`
`variable “j” in the bit lines expression “B[j,n]” and the same variable “j” in the
`
`column selection lines expression “YS[j].” In reaching its decision that Horiguchi
`
`only discloses a single column selection line, the Board explained:
`
`Comparing Petitioner’s annotated Figure 26 (Pet. 30) and Figure 26
`without annotations reveals that, although the first of the pink lines
`added by Petitioner corresponds to YS(j) in Horiguchi, the second
`of the pink lines does not have a corresponding column selection
`line YS in Figure 26.
`
`Decision, 8.
`
`10
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`
`
`
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`The Board overlooked Dr. Mazumder’s testimony and Horiguchi’s
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`disclosure that the variable “j” in the bit line expression “B[j,n]” is iterative and
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`corresponds to a set of numbers from 0 to NB-1, where NB denotes the total number
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`of bit lines. Ex. 1005, 21:61-65; Mazumder Decl., ¶ 118 (NB = 2nB); Petition, 13.
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`Further, the Board misapprehended the relevance of this variable “j” and its
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`relationship to the same iterative variable “j” in the column selection line
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`expression “YS[j]” in Fig. 26. Specifically, both the Petition and Dr. Mazumder’s
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`Declaration provide: “[f]or each value of “j”, column selection line YS[j] selects
`
`bit line B[j,n] in each of the sub-arrays” and “[f]or ease of reference, column
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`selection lines YS[0] (i.e., j=0) and YS[1] (i.e., j=1), . . . , are shown in annotated
`
`Fig. 26 above.” Mazumder Decl., ¶¶ 152-153 (emphasis added); Petition, 30-31
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`(emphasis added). Given that there are multiple bit lines in each memory array,
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`there must be multiple column selection lines in order to access all of the memory
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`cells in the array. Mazumder Decl., ¶¶ 33-35 & 117-118; Ex. 1005, 21:58-65.
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`Thus, the iterative variable “j” in the bit lines expression “B[j,n]” and the
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`column selection lines expression “YS[j]” indicates that there are multiple column
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`selection lines (i.e., YS[0], YS[1], … YS[NB-1]) disclosed in Horiguchi.
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`Mazumder Decl., ¶¶ 117-118 & 152-153; Petition, 13 & 30-31; see also Ex. 1005,
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`22:7-10 & 18-22 (referring to “output lines” YS[j] of the Y-decoder).
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`11
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`
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`
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`IV.
`
`CONCLUSION
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`For the reasons set forth above, the Board clearly erred in overlooking the
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`unrebutted testimony of Dr. Mazumder and misapprehending the disclosure and
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`contentions regarding Horiguchi set forth in the Petition and Declaration of Dr.
`
`Mazumder. The Board abused its discretion in denying inter partes review on
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`Ground 1 of the Petition. Therefore, Petitioner respectfully requests that the Board
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`grant this request for rehearing and institute a trial.
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`Respectfully submitted,
`
`/John R. Hutchins/
`John R. Hutchins (Reg. No. 43,686)
`Lead Counsel for Petitioner
`
`
`
`Dated: February 17, 2017
`
`
`John R. Hutchins (Reg. No. 43,686)
`jhutchins@kenyon.com
`Andrews Kurth Kenyon LLP
`1350 I Street, NW, Suite 1100
`Washington, DC 20005
`T: 202.662.2700
`F: 202.662.2739
`
`Rose Cordero Prey (rcordero@kenyon.com)
`Andrews Kurth Kenyon LLP
`One Broadway
`New York, NY 10004
`T: 212.425.7200
`F: 212.425.5288
`
`Michael Zachary (mzachary@kenyon.com)
`Andrews Kurth Kenyon LLP
`1801 Page Mill Road, Suite 210
`Palo Alto, CA 94304
`
`12
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`
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`13
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`
`
`T: 650.384.4700
`
`T: 650.384.4700
`F: 650.384.4701
`
`F: 650.384.4701
`
`
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`
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`CERTIFICATE OF SERVICE
`
`The undersigned hereby confirms that the foregoing PETITIONER’S
`
`REQUEST FOR REHEARING UNDER 37 C.F.R. § 42.71(d) was served on
`
`February 17, 2017, via electronic mail upon the following:
`
`Nicholas T. Peters (Reg. No. 53,456)
`Paul B. Henkelmann (Reg. No. 65,891)
`FITCH EVEN TABIN & FLANNERY, LLP
`120 South LaSalle Street, Suite 1600
`Chicago, Illinois 60603-3406
`Telephone: (312) 577-7000
`Facsimile: (312) 577-7007
`Email: LimestoneIPR@fitcheven.com
`
`/John R. Hutchins/
`John R. Hutchins (Reg. No. 43,686)
`Lead Counsel for Petitioner
`
`
`
`
`
`
`
`14
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`
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