Ulllted States Patent
`
`[19]
`
`[11] Patent Number:
`
`6,003,148
`
`Yamauchi et al.
`
`[45] Date of Patent:
`
`Dec. 14, 1999
`
`US006003148A
`
`[54]
`
`A
`MEMORY CELL WITH A REDUNDANT
`A
`
`[75]
`
`Inventors: Tadaaki Yamauchi; Mikio Asakura;
`Takashi It°> a11°fHY°g°>JaPa“
`
`[73] Assignee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo, Japan
`
`[21] Appl. No.: 08/781,387
`.
`J311- 13: 1997
`Flledi
`Foreign Application Priority Data
`
`[22]
`[30]
`
`5,488,578
`5,535,161
`5,537,351
`5,544,106
`5,548,596
`
`5:654:924
`
`1/1996 Yamada ................................... .. 365/49
`
`7/1996 Kato . . . . . . . .
`. . . . . . .. 365/200
`7/1996 Suyva et al.
`...................... .. 365/189.02
`8/1996 Koike .................................... ..
`8/1996 Tobita ........... ..
`.. 371/21.2
`365/200
`%IS1l(1)iS‘}11:ae:ta:’1.”"'
`371/10.3
`...................... 365/189.05
`8/1997 Suzuki et al.
`
`FOREIGN PATENT DOCUMENTS
`
`63—140499
`2-3199
`
`6/1988
`1/1990
`
`Japan.
`Japan.
`
`Primary Examiner—Robert W. Beausoliel, Jr.
`Assistant Examiner—Nadeern Iqbal
`Attorney, Agent, or Firm—McDermott, Will & Emery
`
`May 30, 1996
`
`[JP]
`
`Japan .................................... 8—136935
`
`[57]
`
`ABSTRACT
`
`In a predetermined rnultibit test mode, a multibit test circuit
`114 issues determination result data pairs RDMO and
`/RDMWORDM3 and/RDM3>ea°h°fWh1ChC°“eSP°“dS‘°
`mitch/Enifmatch OE 1°gi"S1°f dfta Fead fmm mfflory Ce“:
`se ecte
`y one co umn se ect 1ne 1n correspon 1ng one o
`memory cell plane blocks. In each memory cell plane block,
`memory cell columns selected by one single column select
`line can be replaced as a unit. The unit of ‘memory cell
`columns containing a defective memory cell is replaced in
`accordance with determination result data RDMO and
`
`Int. Cl.5 .................................................... .. G06F 11/00
`[51]
`U_S_ CL
`..... N 714/711; 365/201
`[52]
`[58] Field of Search .................................. 371/103,102,
`371/212, 21.1, 20.4, 22.5, 27.5, 40.2; 395/183.01,
`183.06’ 182.04’ 182.05’ 183.18’ 185.01’
`185.07; 365/201’ 200’ 189.01’ 189.07; 324/73.1
`
`
`
`[56]
`
`References Cited
`US. PATENT DOCUMENTS
`
`5,091,884
`5,293,386
`5,416,741
`
`2/1992 Kagami ................................. .. 365/200
`3/1994 Muhmenthaler et al.
`.
`371/21.1
`5/1995 Ohsawa ................................. .. 365/201
`
`/RDMO K’ RDM3 and /RDM3"
`
`24 Claims, 16 Drawing Sheets
`
`M#0
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`pLANES
`TEST CIRCUIT
`
`
`
`RDT
`/RDT
`
`RDMO~RDM3
`/RDMO~/RDM3
`
`Apple — Ex. 1013
`Apple Inc., Petitioner
`1
`
`Apple – Ex. 1013
`Apple Inc., Petitioner
`1
`
`

`
`U.S. Patent
`
`Dec. 14,1999
`
`Sheet 1 of 16
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`6,003,148
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`U.S. Patent
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`Dec. 14,1999
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`6,003,148
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`U.S. Patent
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`Dec. 14,1999
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`U.S. Patent
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`Dec. 14,1999
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`Sheet 5 of 16
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`U.S. Patent
`
`Dec. 14,1999
`
`Sheet 6 of 16
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`6,003,148
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`Sheet 9 of 16
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`Dec. 14,1999
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`Sheet 10 of 16
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`6,003,148
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`FIG. 10
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`
`U.S. Patent
`
`Dec. 14,1999
`
`Sheet 11 of 16
`
`6,003,148
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`FIG. 11
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`U.S. Patent
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`Dec. 14,1999
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`Sheet 15 of 16
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`6,003,148
`
`FIG. 76
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`
`U.S. Patent
`
`Dec. 14,1999
`
`Sheet 16 of 16
`
`6,003a148
`
` VccpVtcs
` STEP DOWNCIRCUIT
`
`MEMORYCELLPLANE
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`
`

`
`6,003,148
`
`1
`SEMICONDUCTOR MEMORY DEVICE
`ALLOWING REPAIR OF A DEFECTIVE
`MEMORY CELL WITH A REDUNDANT
`CIRCUIT IN A MULTIBIT TEST MODE
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`
`The present invention relates to a semiconductor memory
`device, and in particular to a circuit structure for controlling
`a test operation of a dynamic semiconductor memory
`device.
`
`2. Description of the Background Art
`FIG. 17 schematically shows a whole structure of a
`dynamic semiconductor memory device in the prior art. In
`FIG. 17, a semiconductor memory device 1 includes four
`memory cell planes 2a—2a', which are formed on a semi-
`conductor chip and each has a plurality of memory cells
`arranged in a matrix form.
`In order to select a memory cell in accordance with an
`address signal, there are arranged a row select circuit (a row
`predecoder, a row decoder and a word line driver) and a
`column select circuit
`(a column predecoder, a column
`decoder and an I/O gate), which are not shown for simpli-
`fying the figure.
`Each of memory cell planes 2a—2a' is divided into four
`column groups. A global I/O line pair GIOP is arranged for
`each column group. When one of memory cell planes 2a—2a'
`is selected, the memory cell of one bit is selected in each of
`the column groups in the selected memory cell plane, and is
`coupled to global I/O line pair GIOP for the selected
`memory cell.
`The semiconductor memory device further includes
`preamplifier/write-buffers 7, which are provided corre-
`spondingly to global I/O line pairs GIOP for input/output of
`data to and from corresponding global I/O line pairs GIOP,
`respectively, read drivers 8, which amplify internal read data
`sent from the corresponding preamplifiers and send the same
`to the corresponding read data buses RDAP
`(RDAPa—RDAPd), respectively, first test mode circuits 9,
`which are provided correspondingly to memory cell planes
`2a—2a', respectively, and determine match/mismatch of log-
`ics of data read from preamplifier/write-buffers 7 in a test
`operation mode, a second test mode circuit 10, which
`receives signals indicative of results of determination sent
`from first test mode circuits 9 provided for memory cell
`planes 2a—2a', respectively, and determines match/mismatch
`of logics of the determination result signals thus received,
`and a driver circuit 11 which receives signals on read data
`buses RDAPa—RDAPd and a signal sent from test mode
`circuit 10, and selectively transmits the received signals to
`an output buffer 13 via an output bus RDP.
`Preamplifier/write-buffers 7 select one of the four column
`groups in each of memory cell planes 2a—2a', and the
`memory cell data in the selected column group is transmitted
`via read driver 8 onto the corresponding one of read data
`buses RDAPa—RDAPd.
`
`In the test operation mode, all the four column groups are
`selected in each of memory cell planes 2a—2a', and the output
`signals of four preamplifiers 7 are transmitted to correspond-
`ing first test mode circuit 9.
`In the normal operation mode, driver circuit 11 selects
`data read from the selected memory cell plate among data
`read onto read data buses RDAPa—RDAPd, and send the
`same to output buffer 13.
`In the test operation mode, driver circuit 11 selects the
`signal indicative of the test result sent from test mode circuit
`10, and transmits the same via output data bus RDP to output
`buffer 13.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`Write buffers of preamplifier/write-buffers 7 are coupled
`to an input buffer 12 via an input data bus WD. Write buffers
`7 corresponding to the selected one among memory cell
`planes 2a—2a' are activated, and data is written via the write
`buffer into selected memory cells contained in the selected
`column group in the selected memory cell plane.
`The semiconductor memory device further includes an
`address buffer 3 which receives an externally applied
`address signal and produces an internal address signal, an
`ATD generating circuit 4 which detects change in the
`internal address signal (internal column address signal) sent
`from address buffer 3 and generates an address change
`detection signal ATD, a PAE generating circuit 5 which is
`responsive to address change detection signal ATD sent from
`ATD generating circuit 4 to generate a preamplifier enable
`signal PAE for activating the preamplifier of preamplifier/
`write-buffer 7, and an IOEQ generating circuit 6 which is
`responsive to address change detection signal ATD sent from
`ATD generating circuit 4 and generates an equalize instruc-
`tion signal IOEQ for equalizing global I/O line pair GIOP.
`Global I/O line pair GIOP is formed of a pair of comple-
`mentary signal lines for transmitting data signals which are
`complementary to each other. Equalize signal IOEQ func-
`tions to equalize the potentials on global I/O lines of global
`I/O line pair GIOP.
`The semiconductor memory device further includes an
`internal voltage regulator 29, which receives an externally
`applied power supply potential Vcc, and generates a power
`supply potential Vccp for a peripheral circuit and a power
`supply potential Vccs for the memory cell plane, which are
`lower than external power supply potential Vcc. Power
`supply potential Vccp for peripheral circuit is supplied as an
`operation power supply potential
`to preamplifier/write-
`buffers 7, read drivers 8 and others.
`Power supply potential Vccs for memory cell plane is
`applied to circuits for driving memory cell planes 2a—2a'
`(i.e., sense amplifiers for charging/discharging bit lines) and
`substrate regions of p-channel MOS transistors in the planes.
`Output buffer 13 and input buffer 12 perform external
`input/output of data via a common data input terminal DQ.
`A multibit test operation related to the invention will be
`described below.
`
`As a storage capacity of the semiconductor memory
`device increases, the number of memory cells increases. If
`determination of defect/nondefect in memory cells is per-
`formed bit by bit, an extremely long test time is required,
`resulting in increase in cost of chips. Therefore, determina-
`tion of defect/nondefect is performed on multiple memory
`cells at a time, so that the test time can be reduced. This
`manner of performing the test on multiple memory cells at
`a time is called a multibit test mode.
`
`An operation of writing test data in the multibit test mode
`will be described below. In each of memory cell planes
`2a—2d, one memory cell row is selected. Then, in each of
`memory cell planes 2a—2a', memory cells of 4 bits are
`selected from memory cells belonging to the selected
`memory cell row. Test data to be written into the selected
`memory cells is transmitted to the write buffers in
`preamplifier/write-buffers 7 from input buffer 12.
`In the multibit test mode, all the write buffers are enabled.
`Thereby,
`the same test data is written into the selected
`memory cells of 4 bits in each of memory cell planes 2a—2a',
`and thus the same test data is written into the memory cells
`of 16 bits in total.
`
`Then, data reading in the multibit
`described below.
`
`test mode will be
`
`18
`
`18
`
`

`
`6,003,148
`
`3
`Similarly to the test data writing, memory cells of 4 bits
`are simultaneously selected in each of memory cell planes
`2a—2d. All the preamplifiers included in preamplifier/write-
`buffers 7 are enabled. Data of 4-bit memory cells selected in
`each of memory cell planes 2a—2a' is amplified by the
`preamplifiers, and is transmitted to corresponding first test
`mode circuits 9.
`Each first test mode circuit 9 determines match/mismatch
`of logics of received memory cell data of 4 bits, and sends
`a signal indicative of the result of determination to second
`test mode circuit 10.
`
`Second test mode circuit 10 operates in accordance with
`the determination results sent from four first
`test mode
`
`circuits 9, and determines whether match of logics of test
`data read from four first test mode circuits 9 is detected or
`not.
`The determination data issued from test mode circuit 10
`
`is applied to output buffer 13 via driver 11, and output buffer
`13 transmits this determination data to data I/O terminal DQ.
`Thus, second test mode circuit 10 determines match/
`mismatch of logics of all the data of memory cell groups
`each including the memory cells of 4 bits selected in each of
`memory cell planes 2a—2a', i.e., all the data of memory cells
`of 16 bits in total. Based on the determination data sent from
`second test mode circuit 10, it is determined whether a
`defective memory cell is present among the simultaneously
`selected memory cells of 16 bits.
`As described above, memory cells of 16 bits can be tested
`at a time, the test time can be significantly reduced.
`In the conventional structure of the semiconductor
`
`memory device, the first test mode circuits are provided for
`the plurality of memory cell planes, respectively, and the
`output signals of these first test mode circuits are transmitted
`to the second test mode circuit, so that the second test mode
`circuit determines defect/nondefect of simultaneously
`selected memory cells.
`In the above structures of the test mode circuits, however,
`it is impossible to specify the defective memory cell among
`the selected memory cells.
`For example, in semiconductor memory devices having
`increased storage capacities, when a defective memory cell
`was found by the test, a memory cell column containing the
`defective memory cell is replaced with a backup or spare
`memory cell column. This replacement can prevent a
`malfunction, even when the defective memory cell was
`found.
`
`In the multibit test of the semiconductor memory device
`in the prior art, however, the replacement with the spare
`memory cell column is impossible, because it is difficult to
`specify the memory cell column containing the defective
`memory cell. When an operation test was performed in the
`multibit test mode for reducing a test time, such a problem
`arises that a malfunction by the defective memory cell
`cannot be overcome.
`
`SUMMARY OF THE INVENTION
`
`An object of the invention is to provide a semiconductor
`memory device in which a memory cell column containing
`a defective memory cell can be specified in a multibit test
`mode.
`
`Another object of the invention is to provide a semicon-
`ductor memory device, which allows a multibit test for
`reducing a test
`time, and also allow replacement of a
`memory cell column containing a defective memory cell
`with a spare memory cell column for overcoming a mal-
`function.
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`the invention provides a semiconductor
`In summary,
`memory device including a control circuit, a first number of
`memory cell blocks more than one, and a test circuit.
`The control circuit controls a test mode operation of the
`semiconductor memory device in accordance with an exter-
`nally applied control signal. Each of the memory cell blocks
`includes a plurality of memory cells arranged in a matrix
`form, a column select circuit for simultaneously selecting a
`second number of memory cell columns more than one, and
`a read circuit for reading the second number of storage data
`from the memory cells belonging to the selected memory
`cell columns. The test circuit receives the second number of
`
`storage data from each of the memory cell blocks, and is
`controlled by the control circuit
`to issue either a first
`determination signal corresponding to a result of comparison
`of the storage data sent from all the memory cell blocks or
`the first number of second determination signals each cor-
`responding to a result of comparison performed on the
`second number of storage data.
`Preferably, each of the memory cell blocks includes a
`plurality of spare memory cell columns forming a unit(s)
`each including the second number of memory cell columns,
`and a spare column select circuit for storing an externally set
`address value and, when an external address signal corre-
`sponds to the set address value, selecting the corresponding
`unit of the spare memory cell columns.
`According to another aspect of the invention, a semicon-
`ductor memory device includes a control circuit, a first
`number of first memory cell blocks more than one, and a test
`circuit.
`
`The control circuit controls a test mode operation of the
`semiconductor memory device in accordance with an exter-
`nally applied control signal. Each of the memory cell blocks
`includes a plurality of memory cells arranged in a matrix
`form, a column select circuit for handling memory cell
`columns of n (n: natural number) in number as a unit and,
`in accordance with an externally applied address signal,
`simultaneously selecting the memory cell column units of m
`(m: natural number) in number depending on a test mode
`signal sent from the control circuit, a read circuit for reading
`storage data of (n><m) in number from the memory cells
`belonging to the selected memory cell columns, and data
`match detecting circuits of n in number. The ith (1§i§n)
`data match detecting circuit receives the storage data of m in
`number from the ith memory cell column in each of the
`memory cell column units, and issues a match detection
`signal depending on match/mismatch of the received storage
`data. The test circuit receives the match detection signals of
`n in number from each of the memory cell blocks, and is
`controlled by the control circuit
`to issue either a first
`determination signal corresponding to a result of comparison
`of the match detection signals sent from all the memory cell
`blocks or the first number of second determination signals
`each corresponding to a result of comparison performed on
`the match detection signals of n in number.
`Preferably, each of the memory cell blocks further
`includes spare memory cell columns including a plurality of
`memory cell column groups each formed of the memory cell
`column units of n in number, and a spare column select
`circuit for storing an externally set address value and, when
`an externally applied address signal corresponds to the set
`address value, selecting the corresponding group of the
`spare memory cell columns.
`Accordingly, a major advantage of the invention is as
`follows. For data which are read from the simultaneously
`selected memory cell column in each of the memory, match/
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`mismatch of logics can be detected independently from
`other data, so that it is possible to specify the memory cell
`column having a defective memory cell in a multibit test.
`Another advantage of the invention is as follows. In each
`memory cell block, the memory cells to be selected simul-
`taneously forms the unit, and this memory cell column unit
`can be replaced with the spare memory cell column unit, so
`that the memory cell column having a defective memory cell
`can be repaired in accordance with results of the multibit
`test.
`
`The foregoing and other objects, features, aspects and
`advantages of the present
`invention will become more
`apparent from the following detailed description of the
`present
`invention when taken in conjunction with the
`accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 shows a whole layout of a semiconductor memory
`device 1000 of an embodiment 1 of the invention;
`FIG. 2 specifically shows a structure of one memory cell
`plane shown in FIG. 1;
`FIG. 3 schematically shows arrangement of global I/O
`line pairs and local I/O line pairs;
`FIG. 4 specifically shows arrangement of sense amplifier
`bands shown in FIG. 3;
`FIG. 5 shows allocation of address signals in a memory
`cell plane of the semiconductor memory device of the
`embodiment 1 of the invention;
`FIG. 6 is a schematic block diagram showing a structure
`of a data input buffer 1100;
`FIG. 7 shows data write paths in the semiconductor
`memory device 1000 in a functional manner;
`FIG. 8 shows data read paths in the semiconductor
`memory device 1000 in a functional manner;
`FIG. 9 is a schematic block diagram showing a structure
`of a multibit test circuit 114 shown in FIG. 8;
`FIG. 10 is a schematic block diagram showing a structure
`of a data output buffer 1400;
`FIG. 11 is a first circuit diagram showing a structure of an
`internal control circuit 200;
`FIG. 12 is a second circuit diagram showing a structure of
`the internal control circuit 200;
`FIG. 13 is a timing chart for illustrating an operation of
`the internal control circuit 200;
`FIG. 14 is a timing chart for illustrating a multibit test
`operation of the semiconductor memory device 1000;
`FIG. 15 is a schematic block diagram showing data
`transmission paths in a semiconductor memory device of an
`embodiment 2;
`FIG. 16 is a schematic block diagram showing a structure
`of a control circuit 600 of an embodiment 2; and
`FIG. 17 is a schematic block diagram showing a structure
`of a conventional semiconductor memory device 1.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`[Embodiment 1]
`FIG. 1 is a schematic block diagram showing a semicon-
`ductor memory device 1000 of an embodiment 1 of the
`invention.
`
`Referring to FIG. 1, semiconductor memory device 1000
`includes four memory cell planes M#0 to M#3 isolated from
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`each other by central regions CR1 and CR2 which extend
`along long and short sides, respectively.
`Each of memory cell planes M#0 to M#3 has a storage
`capacity, e.g., 16 Mbits. Thus, semiconductor memory
`device 1000 has a storage capacity of 64 Mbits.
`Memory cell planes M#0 to M#3 include row decoders
`RDO to RD3 for selecting word lines, respectively, which are
`opposed to first central region CR1 and are arranged along
`the long side, and also include column decoders CDO to CD3
`for generating column select signals, respectively, which are
`opposed to second central region CR2 and are arranged
`along the short side. In the first central region CR1, pads PD
`including data I/O terminals DQ are arranged at central
`region CR1 along the long side. Address signal input pads
`PDA receiving externally supplied address signals are
`arranged at central region CR1 between memory cell planes
`M#0 and M#2.
`
`Similarly to the conventional semiconductor memory
`device, the semiconductor memory device 1000 includes, as
`will be described later, preamplifier/write-buffer circuits 7
`for data input/output with respect to global I/O line pairs
`arranged in memory cell planes M#0 to M#3, read drivers 8
`which amplify internal read data sent from preamplifier/
`write-buffer circuits 7 and transmit the same to correspond-
`ing read data buses, and a driver circuit 11 which receives
`signals on the read data buses and selectively transmits the
`same to an output buffer 13 via an output bus.
`Further, the semiconductor memory device 1000 includes
`an address buffer 3 which receives an address signal exter-
`nally applied via address input pads PDA and produces an
`internal address, an ATD generating circuit 4 which detects
`change in the internal address signal applied from address
`buffer 3 and generates an address change detection signal
`ATD, a PAE generating circuit 5 which is responsive to
`signal ATD to generate a signal PAE for activating pream-
`plifier included in preamplifier/write-buffer 7, and an IOEQ
`generating circuit 6 which is responsive to signal ATD to
`generate an equalize instruction signal IOEQ for equalizing
`the potential level on global I/O line pair.
`Semiconductor memory device 1000 further includes an
`internal voltage regulator 29 which receives an externally
`supplied power supply potential Vcc and issues an internal
`power supply potential, an output buffer 13 which receives
`an output of driver circuit 11 and drives the potential levels
`on data I/O terminals DQ (“DQ” generally indicates data I/O
`terminals DQO—DQ15), and an input buffer 12 which
`receives data sent from data I/O terminal DQ and transmits
`the same to preamplifier/write-buffers 7.
`Although the circuits described above are not shown in
`FIG. 1, they are arranged in the same manner as those in the
`conventional semiconductor memory device.
`FIG. 2 specifically shows a structure of a portion related
`to one of memory cell planes M# (“M#” generally indicates
`M#0 to M#3).
`In FIG. 2, each memory cell plane M# includes 32 row
`blocks MRBO—MRB31 each having memory cells of 512
`Kbits. In each of row blocks MRBO—MRB31, the memory
`cells of 512 Kbits are arranged in a matrix form.
`Sense amplifier bands SAB1—SAB31, which sense and
`amplify data of the memory cells selected in accordance
`with the external address signals, are disposed between row
`blocks MRBO—MRB31.
`
`Sense amplifier bands SABO and SAB32 are arranged
`outside row blocks MRBO and MRB31, respectively.
`Sense amplifier bands SABi and SAB(i+1) arranged at
`opposite sides of each row block MRBi (i=0—31) sense and
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`amplify data of the memory cells connected to one selected
`row in the same row block MRBi.
`
`Thus, each of sense amplifier bands SAB1—SAB31 are
`commonly used by two row blocks.
`FIG. 3 shows an arrangement of I/O lines, i.e., internal
`data write/read lines in one memory cell plane.
`Referring to FIG. 3, memory cell plane M# is divided into
`four column blocks MCBO to MCB3. Four global I/O line
`pairs GIOa to GIOd are arranged for each of column blocks
`MCBO to MCB3.
`
`Global I/O line pairs GIOa to GIOd extend in the column
`direction through all the row blocks in the corresponding
`column block. In each row block (in FIG. 3, row block
`MRBN is shown as a representative example, word lines WL
`which transmit a row select signal sent from row decoder
`RD extend through column blocks MCBO—MCB3. Each
`word line WL is connected to memory cells (not shown)
`belonging to one row in the memory cell plane.
`Sense amplifier bands SABN and SABN+1 are arranged
`at opposite sides in the column direction of row block
`MRBN. In each of sense amplifier bands SABN and SABN+
`1, there are arranged local I/O line pairs LIOa to LIOd which
`extend in the row direction through only each column block.
`At each column block in row block MRBN, there are
`arranged four local I/O line pairs, i.e., local I/O line pairs
`LIOa, LIOb, LIOc and LIOd.
`Local I/O line pairs LIOa to LIOd are connected to global
`I/O line pairs GIOa to GIOd arranged in the corresponding
`column block via row block line pair gates RSG which are
`represented by solid circles in FIG. 3, respectively. Row
`block select gates RSG are selected in accordance with row
`address signal bits for row block selection, respectively.
`FIG. 4 is a circuit diagram specifically showing a structure
`of sense amplifier bands SABN and SABN+1 shown in FIG.
`3.
`
`FIG. 4 shows, as a representative example, a structure of
`a portion related to one column select line CSL. Column
`select line CSL is arrange in each of the column blocks
`MCBO to MCB3 in FIG. 3, and extends through a plurality
`of row blocks.
`
`Only column select line CSL in the column block selected
`in accordance with the externally applied address signal is
`selected to attain the potential level at “H” level.
`Four bit line pairs BLPO—BLP3 are arranged for each
`column select line CSL. Each of bit line pairs BLPO—BLP3
`includes bit lines BL and /BL transmitting data signals which
`are complementary to each other. Memory cells MC are
`arranged correspondingly to crossings between bit line pairs
`BLPO—BLP3 and word line WL.
`
`in which
`FIG. 4 shows an example of arrangement
`memory cells MC are arranged correspondingly to crossings
`between bit lines BL and word line WL.
`
`Bit line pairs BLPO and BLP2 are connected to sense
`amplifiers SAO and SA2 contained in sense amplifier band
`SABN via isolation gates TGa0 and TGa2, respectively,
`which are turned on in response to a bit line isolation control
`signal BRIb.
`Bit line pairs BLP1 and BLP3 are connected to sense
`amplifiers SA1 and SA3 contained in sense amplifier band
`SABN+1 via isolation gates TGa1 and TGa3, respectively,
`which are turned on in response to a bit line isolation control
`signal BRIa.
`Sense amplifiers SA in sense amplifier band SABN are
`connected to bit line pairs included in row block MRB(N—1)
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`via isolation gates TGb0 and TGb2, respectively, which are
`turned on in response to isolation control signal BRIb.
`Sense amplifiers SA included in sense amplifier band
`SABN+1 are connected to bit line pairs included in row
`block MRBN+1 via isolation gates TGb1 and TGb2,
`respectively, which are turned on in response to isolation
`control signal BRIa.
`Sense amplifier SA is provided correspondingly to each
`bit line pair, and is commonly used by the bit line pairs in
`the row blocks adjacent to each other. In each row block
`MRBN, sense amplifiers SA are arranged alternately at
`opposite sides of the bit line pairs, and therefore form a
`so-called shared sense amplifier arrangement of an alternate
`arrangement type.
`In sense amplifier band SABN, local I/O line pairs LIOa
`and LIOb are arranged parallel to word line WL, and extend
`through one column block.
`In sense amplifier band SABN+1, local I/O line pairs
`LIOc and LIOd are arranged in a similar manner.
`Column select gates IGO—IG3, which are turned on in
`response to the signal potential on column select line CSL,
`are arranged for sense amplifiers SAO—SA3, respectively.
`These column select gates IGO—IG3 are turned on to connect
`sense amplifiers SAO—SA3 to local
`I/O line pairs
`LIOa—LIOd, respectively, when the signal potential on cor-
`responding column select line CSL is at “H” level indicating
`the selected state.
`
`When row block MRBN is selected, bit line isolation
`control signals BLIa and BRIb attain “H” level, and bit line
`isolation control signals BRIa and BLIb attain “L” level.
`Thereby, bit line pairs BLPO—BLP3 are connected to sense
`amplifiers SAO—SA3, respectively.
`In a standby state, all bit line isolation control signals
`BLIa, BLIb, BRIa and BRIb attain “H” level, and all
`isolation control gates TGa0—TGa3 and TGb0—TGb3 are
`turned on.
`
`In a read operation and others, only the selected row block
`is connected to sense amplifier SA, so that a capacity of the
`bit line pair connected to sense amplifier SA is reduced,
`which allows a rapid sense operation and transmission of a
`sufficient read voltage (read data of the memory cell) to the
`sense node.
`
`Local I/O line pairs LIOa—LIOd are connected to global
`I/O line pairs GIOa—GIOd in FIG. 3 which are arranged in
`the corresponding column groups (not shown in FIG. 4),
`respectively.
`FIG. 5 shows an example of allocation of address signal
`bits related to one memory cell plane shown in FIG. 1.
`Referring to FIG. 5, allocation of the address signal bits
`in one memory cell plane