United States Patent [19]
`Hidaka et a].
`‘
`
`USOO5687123A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,687,123
`Nov. 11, 1997
`
`[54] SEMICONDUCTOR MEMORY DEVICE
`
`FOREIGN PATENT DOCUMENTS
`
`[75] Inventors: Hideto Hidaka; Mikio Asakura;
`Kazuyasu Fujishima; Tsukasa Ooishi;
`Kazutami Arimoto; Shigeki
`Tomishima', Masaki Tsukude, all of
`Hyogo, Japan
`
`[73] Assignee:
`
`Mitsubishi Denki Kabushiki Kaisha.
`Tokyo. Japan
`
`Appl. No.: 312,968
`[21]
`Filed:
`Sep. 30, 1994
`[22]
`Foreign Application Priority Data
`[30]
`Oct 14, 1993
`Jan. 10, 1994
`Jun. 29, 1994
`
`[JP]
`[JP]
`[JP]
`
`Japan .................................. .. 5-257328
`Japan
`..... .. 6-001017
`Japan .................................. .. 6-148007
`
`[51] Int. Cl.6 ..................................................... .. GllC 7/00
`[52] US. Cl. ............. .. 365118909; 365/174; 365/189.01;
`365118911; 36512.01; 365/226; 365/230.06
`Field of Search ............................. .. 365/189.0l. 226.
`365118911. 189.09. 230.06. 174. 201
`
`[53]
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,679,172
`5,299,154
`5,444,659
`5,446,697
`
`7/1987 Kirsch et a1. ......................... .. 365/222
`3/1994 OOWaki et a1.
`365/149
`8/1995 Yokokura ..... ..
`365/189.09
`8/1995 Yoo et a1. ............................. .. 365/226
`
`62-208496 9/1987 Japan .
`4-70718 11/1992 Japan .
`5-89677
`4/1993 Japan .
`5-54265
`8/1993 Japan .
`
`OTHER PUBLICATIONS
`
`ISSCC 89/Digest of Technical Papers. Feb. 17. 1989. pp.
`248-249.
`
`Primary Examiner—Do Hyun Yoo
`Attorney Agent, or Firm-Lowe. Price. LeBlanc & Becker
`
`[57]
`
`ABSTRACT
`
`Drains of ?rst and second transistors are connected to a low
`level line of an internal circuitry such as a sense ampli?er
`related to determination of a potential in a memory cell. The
`?rst transistor has its gate diode-connected to a sense drive
`line and its source grounded. The second transistor receives
`at its gate an internally generated signal. and its source is
`grounded. In the standby state. the potential of the sense
`drive line is set higher than low level of said word lines by
`the threshold voltage Vthn of the ?rst transistor and used as
`dummy GND potential Vss', and in the active state. the
`second transistor is rendered conductive so as to prevent
`?oating of the sense drive line from the dummy GND
`potential Vss‘.
`
`42 Claims, 57 Drawing Sheets
`
`A Vcc
`T
`
`INT. CKT
`
`Vthn
`
`Vss
`
`Vss
`
`/
`
`Vss'
`
`l ;
`
`l
`
`1
`l
`
`I
`l
`
`Apple – Ex. 1011
`Apple Inc., Petitioner
`1
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 1 of 57
`
`5,687,123
`
`
`
`
`
`S5 26%: mmoxnz @522
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`
`
`
`2
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 2 of 57
`
`5,687,123
`
`F I G. 2
`
`-—“- Vcc
`I
`INT. CKT
`
`5
`1/
`
`r- ------------------------ -—|
`i
`-
`‘
`i
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`l
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`I
`
`30
`/ Vss
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`
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`
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`
`
`
`3
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 3 of 57
`
`5,687,123
`
`FIG. 4
`
`llllllllllll
`
`71 Vcc
`
`/
`
`Vss
`
`FIG. 5
`
`INT. CKT
`
`INT. CKT
`
`Tr3
`
`Vss
`
`REF. VOLTAGE
`GENERATION CKT
`
`
`
`4
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 4 of 57
`
`5,687,123
`
`F I G. 6
`
`A Vcc
`T
`INT. CKT
`
`5
`./
`
`30
`
`/
`
`l
`
`D1
`
`+
`
`REF. VOLTAGE ¢----
`
`/Tr3
`
`‘
`Vss
`
`8
`
`F I G. 7
`
`A Vcc
`I
`INT. CKT
`
`5
`_/
`
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`
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`
`/Tr3
`
`8
`
`V55
`
`30
`
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`V
`
`REF. VOLTAGE c
`
`‘
`
`+
`-
`
`
`
`5
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 5 of 57
`
`5,687,123
`
`FIG. 8
`
`f- Vcc
`
`INT. CKT
`
`w/
`
`REF. VOLTAGE o_+
`
`q <
`
`_m m m .m E ¢ m w w m w w m Q
`
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`
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`9
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`
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`
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`
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`BM
`
`
`
`6
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 6 of 57
`
`5,687,123
`
`
`
`(a) EE§
`
`(b) 5
`
`(C) ¢
`
`(e) SN
`
`(1) 31.1%?
`
`l/2(Vcc+Vss’)
`
`
`
`
`7
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 7 of 57
`
`5,687,123
`
`FIG.12
`
`/Tr9
`PM
`
`NEGATIVE POTENTIAL /9
`GENERATING CKT
`
`t1
`
`Vss
`
`Vss'
`
`Yum;
`
`
`
`8
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 8 of 57
`
`5,687,123
`
`FIG. l4<
`
`FIG. 15
`
`WORD DRIVER
`
`
`
`9
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 9 of 57
`
`5,687,123
`
`F I G. l 6
`
`(a)
`
`El
`
`(b) ADD
`
`FIG. 17‘
`(e) WL
`
`(f) vi
`
`(g)
`
`(h) WL
`
`SELECTED
`f worm LINE
`
`> NON
`SELECTED
`WORD L {NE
`
`V55
`
`
`
`10
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 10 of 57
`
`5,687,123
`
`F I G. 1 8
`
`BS1
`11
`\f m V81 0-; ,
`
`VSTSF’SI /sw1
`
`in
`
`'
`SENSE ARP.
`
`_
`.
`worm
`
`LINE 5 __ DRIVER
`
`
`wu
`
`MEMORY CELL ARRAY BLOCK
`\ R01
`
`8A2
`'5” SENSE ARP
`B52
`EELECTED "L
`'
`wnz v52 °—r-- '
`" mm
`.-—woRn
`7//////////////////////////////////.""121
`$ 5
`LINE
`gMERORY CELL ARRAY BLOCK AC2 gEgEEEgECTED
`8 __ DRIVER
`"§///4////////%/4///////////////////im22
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`:
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`__. DRIVER
`
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`MEMORY CELL ARRAY BLOCK\
`
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`BLOCK BB
`
`sAs
`
`SENSE AMP.
`
`“C3
`
`‘\
`8A4
`
`FIG. 1 9
`
`V51
`
`
`
`11
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 11 of 57
`
`5,687,123
`
`F I G. 2 0
`
` SELECTED
`
`BLOCK
`
`(e) WL22 ___r """""""" "Vss'
`
`(f) 351.3
`
`5
`1
`
`:
`
`NON-
`
`CTED
`
`V55
`
`V55
`
`(b) ¢2
`
`(c) WD21
`
`SELECTED
`BLOCK
`
` (a) BS2
`
`F I G. 2 1
`
`(d) W121
`
`(2) W122
`
`:
`
`(f) BSl,3 I
`5
`(S) V513 .-?—-—-:**—— Vss
`(h) WLL3:
`Vss
`
`Vss
`
`NON-
`SELECTED
`BLOCK
`
`12
`
`
`
`12
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 12 of 57
`
`5,687,123
`
`FIG. 22
`
`- _ _ _ . _ _ _ _ "'-1
`
`I
`
`____ “$191111. CKT
`E
`r/16
`: OSCILLATOR
`I
`
`._':_.v
`
`I
`
`.xls
`T cc )7:
`PUMPING c141 ‘
`i
`I
`l
`
`REF . VOLTAGE
`GENERATING CKT \18
`
`
`
`13
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 13 of 57
`
`5,687,123
`
`7 I
`
`ti i It
`
`w m m H
`A; \ 5 \ 3 \ 2m 3m \ i.
`
`mm .2@
`
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`2\ :5 uzzzés
`as 225 w +
`
`@5525
`
`
`
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`
`
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`
`
`
`14
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 14 of 57
`
`5,687,123
`
`1
`:\
`
`I
`
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`5
`
`2
`
`FIG. 244“) E9
`
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`
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`
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`DUMMY GND LEVEL /19
`GENERATING cm
`
`
`
`15
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 15 of 57
`
`5,687,123
`
`F I G. 2 6
`
`SN
`_ /
`
`I /Trl5
`
`I /Trl6
`
`ACTIVATING
`SIGNAL (S02)
`
`VGND ACTIVATING
`SIGNAL (S01)
`
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`
`.............. -
`
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`
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`
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`
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`
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`
`FIG. 27<
`
`
`
`16
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 16 of 57
`
`5,687,123
`
`FIG. 28
`
`1
`
`/Trl5
`
`/Trl7
`
`SN
`
`- /
`
`I /Trl6
`
`ACTIVATING
`SIGNAL (s02)
`
`ACTIVATING
`SIGNAL (501)
`
`FIG. 29
`
`SN
`1
`
`ACTIVATING SIGNAL>—¢| \ml
`@\
`
`REF. VOLTAGE
`
`{
`ACTIVATING
`SIGNAL (5))
`
`1
`
`Trlg
`:
`
`-
`
`/TI'26
`
`
`
`17
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 17 of 57
`
`5,687,123
`
`L
`
`m?
`l
`1
`/T1'26
`
`SN
`/
`
`I
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`ACTIVATING
`SIGNAL (-55)
`
`ACTIVATING SIGNAL>—-#
`22 x
`
`REF. VOLTAGE
`
`NEGATIVE POTENTIAL /9
`GENERATING CKT
`
`FIG. 31
`
`REF. VOLTAGE
`
`ACTIVATING
`SIGNAL
`
`
`
`18
`
`

`
`US. Patent
`
`Nov. 11, 1997
`
`Sheet 18 0f 57
`
`5,687,123
`
`FIG. 32
`
`REF . VOLTAGE >
`
`FIG. 33
`
`1m A k
`
`“I!
`
`. a
`
`REF. VOLTAGE >
`
`(1mm
`
`m
`INPUT —| g:
`Tr37
`
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`
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`W F F ALULILT
`
`‘
`
`I
`
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`
`
`
`19
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 19 of 57
`
`5,687,123
`
`F‘I C}. 344
`
`4*-Vcc
`
`
`
`Vout
`
`20
`
`
`
`20
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 20 of 57
`
`5,687,123
`
`F I G. 3 6
`
`SN
`
`-‘-Vcc
`
`Tr31 \
`
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`
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`
`3-3
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`1 33
`r \
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`/Tr34
`
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`
`1:2
`
`In
`
`}1”35
`
`REF. VOLTAGE
`
`/Trl6
`
`4°
`
`CONTROL
`CKT
`
`CURRENT
`
`Tr38\
`
`$1-r37
`
`Trag /
`
`F I G. 3 7
`
`SN
`
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`
`'
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`
`\‘‘Tr42
`
`31
`
`CURRENT
`SENSOR
`
`50
`TEST
`
`41
`
`CONTROL
`cxr
`
`
`
`21
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 21 of 57
`
`5,687,123
`
`GENERATiNG
`CKT
`
`
`
`LEVEL
`
`
`
`GENERATING
`CKT
`
`22
`
`
`
`22
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 22 of 57
`
`5,687,123
`
`F‘I C}. <4(3
`
`Trl4
`
`SN Trl6
`
`50
`
`-1
`
`_Efi'i-
`
`23
`
`
`GENERATING
`SO
`REF
`CKT
`VOLTAGE
`
`
`
`
`FIG.4l
`
`'l‘rl7 ms SN Tr16
`
`50
`
`
`
`
`
`
`-“""'fi‘h'-
`
`
`
`23
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 23 of 57
`
`5,687,123
`
`F‘IC3. 4-2
`
`MEMORY CELL BLOCK
`
`24
`
`
`
`24
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 24 of 57
`
`5,687,123
`
`(3) RE'
`(b) GE? 2
`<c> An $111911 \
`T
`<d> Rm (111
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`‘INIIIiiIlE:E:HEEg:::::::::::::::::::::!l|
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`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 25 of 57
`
`5,687,123
`
`FIG.44
`
`BL
`
`NON-SELECTED wL(ov=vss)
`
`
`
`Vss ’>OV
`
`F IC}. 4:5
`
`MMORY ARRAY
`(INCLUDING SENSE AMP.)
`
`
`PERIPHRAL CKT
`
`
`G(Vss)
`
`
`
`26
`
`
`
`26
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 25 of 57
`
`5,687,123
`
`FIG. 46
`
`FIG. 4-7
`
`Iqfix SUB DECODER
`
`-63
`
`27
`
`
`
`27
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 27 of 57
`
`5,687,123
`
`FIG. 48
`
`RESET SIGNAL >_}
`
`TrS2\
`
`Xl(X3)
`X2(X4)
`
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`
`.
`
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`
`F I G. 5 O
`
`69
`
`:§——.—-CSL
`
`fifisfifiif.
`
`28
`
`
`
`28
`
`

`
`
`
`U.S. PatentU.S. Patent
`
`
`
`Nov. 11, 1997Nov. 11, 1997
`
`
`
`Sheet 23 of 57Sheet 23 of 57
`
`
`
`5,687,1235,687,123
`
`
`
`2929
`
`
`
`29
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 29 of 57
`
`5,687,123
`
`FIG. 53
`
`Vac’
`
`-
`sun.-{ ’
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`Tr6
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`2
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`
`III 3
`
`BL
`
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`
`30
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`
`
`30
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`

`
`U.S. Patent
`
`1’1v.0N
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`31
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`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 31 of 57
`
`5,687,123
`
`FIG. 55
`
`wtE"‘
`
`DUMMY GND
`
`LEVEL
`
`GENERAT I NC
`CKT
`
`32
`
`
`
`32
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 32 of 57
`
`5,687,123
`
`3
`
`v
`
`I I
`
`“Q 56 W ¢___l_l_____
`
`IC OPERATIONAL VOLTAGE DUMMY GND
`
`EXT. GND ———-—-———...____:._j____
`
`33
`
`
`
`33
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 33 of 57
`
`5,687,123
`
`I’§[C3.
`
`E323
`
`
`
`111111111111(C
`
`a SUB THRESHOLD CHARACTERISTIC WITHOUT BACKGATE
`bISUB THRESHOLD CHARACTERISTIC WITH VBB=-1V APPLIED
`CISUB THRESHOLD CHARACTERISTIC UNDER ACTUAL DISTURB
`CONDITION
`dILEAK CURRENT DETERMINED BY JUNCTION
`
`IF IC}. 5E9
`
`EXT. Vcc
`
`INT VCC
`
`DUMMY GND
`
`34
`
`
`
`REF. VOLTAGE
`A
`
`coupaxmc cm:
`
`REF. VOLTAGE
`b
`
`COMPARING CKT
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`EXT. GND
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`
`
`34
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 34 of 57
`
`5,687,123
`
`EXT. Vcc
`
`INT. Vcc
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`DUMMY GND
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`EXT. GND
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`IC OPERATIONAL
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`VOLTAGE
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`EXT. GND
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`F1G_ e1(a)
`
`FIG. 61(b)
`
`FIG. 61(c)
`
`35
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`
`
`35
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 35 of 57
`
`5,687,123
`
`F I G. 6 2
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`__:_
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`A EXT. Vcc
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`R1
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`R1
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`36
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`36
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`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 36 of 57
`
`5,687,123
`
`F'I¢3; 6«4
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`Vref2
`
`Vrefl
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`37
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`37
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`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 37 of 57
`
`5,687,123
`
`
`
`IF IC}. 656
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`Vrefz
`
`Vrefl
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`38
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`38
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`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 38 of 57
`
`5,687,123
`
`F‘I C}. 657
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`H
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`SIGNAL
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`39
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`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 39 of 57
`
`5,687,123
`
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`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 40 of 57
`
`5,687,123
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`“0CKm___fl
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`FIG. 70
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`41
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`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 41 of 57
`
`5,687,123
`
`FIG. 73
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`Trl34
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`as -4
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`42
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`42
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`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 42 of 57
`
`5,687,123
`
`FIG.74
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`43
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`43
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`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 43 of 57
`
`5,687,123
`
`P‘I C}. 7'5
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`44
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`44
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`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 44 of 57
`
`5,687,123
`
`FIG.77
`
`Vcc
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`45
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`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 45 of 57
`
`5,687,123
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`F'I(3. 8(3
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`U.S. Patent
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`mN
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`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 47 of 57
`
`5,687,123
`
`FIG. 84
`
`9" test
`
`GENERATING cm
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`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 43 of 57
`
`5,687,123
`
`FIG. 86
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`
`
`U.S. PatentU.S. Patent
`
`
`
`Nov. 11, 1997Nov. 11, 1997
`
`
`
`Sheet 49 of 57Sheet 49 of 57
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`
`5,687,1235,687,123
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`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 50 of 57
`
`5,687,123
`
`FIG. 91
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`ROWDECODER
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`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 51 of 57
`
`5,687,123
`
`FIG.92
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`52
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`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 52 of 57
`
`5,687,123
`
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`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 53 of 57
`
`5,687,123
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`
`U.S. PatentU.S. Patent
`
`
`
`Nov. 11, 1997Nov. 11, 1997
`
`
`
`Sheet 54 of 57Sheet 54 of 57
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`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 55 of 57
`
`5,687,123
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`F‘IC3. 953
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`FIG. 99
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`56
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`
`56
`
`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 56 of 57
`
`5,687,123
`
`FIG.
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`

`
`U.S. Patent
`
`Nov. 11, 1997
`
`Sheet 57 of 57
`
`5,687,123
`
`
`
`FIG. 102
`
`PRIORART (<1) 50
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`58
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`

`
`5,687,123
`
`1
`SEMICONDUCTOR MEMORY DEVICE
`
`BACKGROUND OF THE INVENTION
`
`FIELD OF THE INVENTION
`
`The present invention relates to a semiconductor memory
`device. More specifically. the present invention relates to a
`semiconductor memory device in which low level potential
`of sense amplifiers. memory cells and bit lines constituting
`a memory cell array is adapted to be higher than the low
`level of the word lines of the chip body.
`in a dynamic
`random access memory including a memory cell array
`arranged on a semiconductor substrate. sense amplifiers and
`circuitry for controlling these.
`
`10
`
`DESCRIPTION OF THE BACKGROUND ART
`
`2
`incidental to memory array operation flows to the side of the
`ground. floating of the “L” level of the non-selected word
`line. increase of the sub threshold leak current of the word
`line and degradation of the refresh characteristics.
`SUMMARY OF THE INVENTION
`
`Therefore. an object of the present invention is to provide
`a semiconductor memory device in which threshold voltage
`of memory cell transistors can be set low and reliability can
`be improved. and in addition. which eliminates the need of
`a triple well structure.
`Briefly stated. the semiconductor memory device of the
`present invention includes a memory cell array including
`memory cells each connected to one of a plurality of bit lines
`and one of a plurality of word lines; a sense amplifier for
`amplifying a small potential dilference read from the
`memory cell array to the bit line. a control circuit for
`controlling reading of data from the memory cell array and
`writing of data to the memory cell array. and a potential
`setting circuit for setting lines of low level potential in the
`sense amplifier. the memory cells and bit lines to a potential
`higher than the low level of the word lines.
`Therefore. according to the present invention, since the
`lines of the low level potential of the sense amplifier group.
`the memory cells and the bit lines are set to a potential higher
`than the low level of the word lines. the threshold voltage of
`the memory cell transistor can be set lower. reliability can be
`improved. a boosted voltage generating circuit becomes
`unnecessary. and the triple well structure becomes unnec-
`essary.
`
`More preferably. in order to enhance the potential of the
`low level potential line by the threshold voltage of a semi-
`conductor element. the potential setting circuit discharges
`the potential of the low level potential line by a second
`semiconductor element in response to a signal which cor-
`responds to a period in which large current flows.
`More preferably, the potential setting circuit includes a
`reference voltage generating circuit for generating a refer-
`ence voltage which is approximately equal to the low level
`potential. and a potential compensating circuit for compar-
`ing the reference voltage with the low level potential line.
`and for compensating the potential of the low level potential
`line so that the potential becomes higher than the low level
`of the word lines. The potential compensating circuit
`includes a comparing circuit and a switching circuit which
`switches in response to the comparison output from the
`comparing circuit.
`Further. potential setting circuit includes a sustain circuit
`for intmmittently supplying a power supply potential to the
`low level potential
`line for compensafing the potential
`thereof so that it attains a level higher than the low level of
`the word lines. The sustain circuit includes an oscillating
`circuit and a pumping circuit.
`More preferably. the potential setting circuit includes a
`reference voltage generating circuit for generating a refer-
`enoe potential. a comparing circuit for comparing the ref-
`erence voltage with the potenfial of the low level potential
`line. and a switching circuit for discharging the potential of
`the low level potential line to the low level of the word lines
`side in accordance with the output from the comparing
`circuit.
`
`FIG. 10] is a schematic diagram showing a main portion
`of a conventional DRAM. Referring to FIG. 101. a memory
`cell MC is connected to a word line WL and a bit line pair
`BL. BIL Bit line pair BL and BC is connected to an 11 channel
`sense amplifier 2, an equalizer circuit 3 and a p channel
`sense amplifier 4 through transfer gates 'I‘r71 and 'I‘r72.
`Transfer gates Tr71 and Tr72 are controlled by a gate control
`signal BLL To equalizer circuit 3. a VBL signal at the
`potential of V2 Vcc as well as an EQ signal are applied. In
`response to the EQ signal. equalizer circuit 3 precharges bit
`lines BL and BC to ‘/2 Vcc by VBL signal. Sense amplifiers
`2 and 4 are to amplify a small potential difference read from
`the memory cell MC to the bit line pair BL and BIZ. Sense
`amplifier 2 is activated when a sense amplifier activating
`signal S0 is applied to a sense drive line SN. while sense
`amplifier 4 is activated when an activating signal 36 is
`applied to a sense drive line SP.
`FIG. 102 is a time chart showing the operation of the
`memory array shown in FIG. 10]. There are a plurality of
`blocks of the memory array shown in FIG. 101. and each
`block is activated when a corresponding block activating
`signal
`is applied thereto. However. at
`this time. sense
`amplifiers 2 and 4 have not yet been activated. When data is
`to be read from memory cell MC. the BLI signal attains to
`the “ " level. transfer gates TR71 and TR72 are rendered
`conductive. and bit line pair BL. BI is connected to sense
`amplifiers 2 and 4 and to equalizer circuit 3. When word line
`WLrises to the boosted voltage Vpp as shown in (a) of FIG.
`102. a small potential difierence is read from memory cell
`MC to bit line pair BL and BL, activating signal S0 attains
`to the “H” level and activating signal SO attains to the “L”
`level as shown in (b) and (c) of FIG. 102. and sense
`amplifiers 2 and 4 are activated. respectively. The small
`potential difference between the bit line pair BL and BL is
`amplified by sense amplifiers 2 and 4. and the potential is
`enhanced to the level of “H” or “L”.
`
`Now. the “L” level of the amplitude of the bit line pair BL
`and BL is the low level of the word lines. In this case. the
`“L” level of a non-selected word line is equivalent to the “L”
`level of the amplitude of the bit line pair BL and BE.
`Therefore. because of sub threshold leak current of the word
`line which is at the low level of the word lines. charges
`stored in the memory cell MC flows to the bit line and the
`amount of charges decrease. resulting in possible destruction
`of the data in the memory cell MC. In order to prevent this
`phenomenon. conventionally. a negative voltage bias Vbb is
`applied to the memory array portion. However. it requires a
`negative potential generating circuit for generating the nega-
`tive voltage bias Vbb. In addition. this approach has disad-
`vantage such as increase of array noise as the current
`
`25
`
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`
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`
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`
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`
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`More preferably. a low level lowering preventing circuit
`such as a diode is provided for preventing lowering of the
`potential of the low level potential line from the potential
`higher than the low level of the word lines.
`More preferably. a voltage comparison stopping circuit
`for disabling the voltage comparing circuit while a large
`
`59
`
`
`
`59
`
`

`
`5,687,123
`
`3
`current flows. and floating preventing circuit for preventing
`floating of the potential of the low level potential line by
`forcefully operating the switching circuit while the large
`current flows are provided.
`Further. more preferably. the sense amplifier includes a
`switching element connected between the low level potential
`line and the ground for enhancing the potential of the low
`level potential line by the threshold voltage thereof. The
`switching element includes a switching circuit which is
`rendered conductive when an input potential becomes equal
`to or lower than the low level of the word lines for applying
`a negative potential to an input electrode of the switching
`element whfle a large cmrent flows so as to make short the
`response time. The switching circuit applies the low level of
`the word lines to the input electrode of the switching element
`in the former half and a negative potential in the latter half
`of the period in which the large current flows.
`According to the another aspect, the present invention
`provides a semiconductor memory device having an internal
`circuit to which a power supply voltage is applied externally.
`which includes a potential setting circuit for setting a high
`level potential supplied in the internal circuit to a potential
`different from the externally supplied power supply voltage.
`and for setting a low level potential supplied in the internal
`circuit difierent from the low level of the word lines. and a
`circuit for changing the high level and low level potentials
`dependent on whether the semiconductor memory device is
`in and not in operation.
`In accordance with another aspect, the present invention
`provides a semiconductor memory device in which a chip is
`formed on a semiconductor substrate. which includes a
`memory cell array including memory cells each connected
`to one of a pltnality of bit lines and one of a plurality of word
`lines; a sense amplifier for amplifying a small potential
`difference read from the memory cell may to the bit line; a
`control circuit for controlling reading of data from the
`memory cell array and writing of data to the memory cell
`array; a substrate potential generating circuit for supplying
`a negative level substrate potential to the semiconductor
`substrate; a boosted voltage generating circuit for generating
`a boosted voltage to be supplied to the word line; and a
`potential setting circuit for switching the boosted voltage
`potential and the negative potential to arbitrary potentials
`dependent on whether the chip is in use or not in use.
`In accordance with a still another aspect of the present
`invention. the semiconductor memory device includes a
`memory cell array including a plurality of memory cells
`each connected to one of a plurality of bit lines and one of
`a plurality of word lines. a sense amplifier for amplifying a
`small potential dilference read from the memory cell array
`to a bit line. a control circuit for controlling reading of data
`from the memory cell array and writing of data to the
`memory cell array. a potential setting circuit for setting a low
`level potential line of the bit lines. memory cells and sense
`amplifier to a potential higher than the low level of the word
`lines. and a potential compensating circuit for compensating
`the set low level potential.
`According to a still another aspect of the present
`invention. the semiconductor memory device includes a
`memory cell array including a plurality of memory cells
`each connected to one of a plurality of bit lines and one of
`a plurality of word lines. a sense amplifier for amplifying a
`small potential difference read from the memory cell array
`to a bit line. a control circuit for controlling reading of data
`from the memory cell array and writing of data to the
`memory cell array. a potential setting circuit for setting a low
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`level potential line of the bit lines. memory cells and sense
`amplifier to a potential higher than the low level of the word
`lines. a potential elevating compensating circuit responsive
`to lowering of the set potential higher than the low level of
`the word lines, compensating for the lowering by elevating
`the potential. and voltage lowering compensating circuit
`responsive to rise of the potential for compensating the rise
`by lowering the potential.
`According to a still further aspect of the present invention.
`the semiconductor memory device includes a memory cell
`array including memory cells each connected to one of a
`plurality of bit lines and one of a plurality of word lines. a
`sense amplifier for amplifying a small potential difference
`read from the memory cell array to the bit line. a driving line
`for driving the sense amplifier. and a potential setting means
`for setting. when the sense amplifier is driven. the low level
`potential of the driving line to a potential higher than the low
`level of the word lines.
`
`According to a still further aspect of the present invention.
`the semiconductor memory device includes a memory cell
`array including memory cells each connected to one of a
`plurality of bit lines and one a plurality of word lines, a sense
`amplifier for amplifying a small potential difference read
`from the memory cell array to a bit line. a transfer gate
`connected between the bit line and the sense amplifier, and
`a control circuit for setting. when the sense amplifier is
`driven. the gate potential of the transfer gate to the low level
`of the word lines and the low level potential of the bit line
`to the threshold voltage of the transfer gate.
`According to a still further aspect of the present invention.
`the semiconductor memory device includes a memory cell
`array including a plurality of memory cells each connected
`to one of a plurality of bit lines and one of a plurality of word
`lines. a sense amplifier for amplifying a small potential
`diiference read from the memory cell array to a bit line. a
`con’n'ol circuit for controlling reading of data from the
`memory cell array and writing of data to the memory cell
`array, and a potential setting circuit for setting low level
`potential line of the bit lines, memory cells and sense
`amplifier to a potential higher than the low level of the word
`lines. and for setting a high level potential to a potential
`lower than the power supply voltage level externally
`applied.
`According to a still further aspect of the present invention.
`a semiconductor memory device provided with chips formed
`on a semiconductor substrate includes a memory cell array
`including memory cells each connected to one of a plurality
`of bit lines and one of a plurality of word lines, a sense
`amplifier for amplifying a small potential difierence read
`from the memory cell array to a bit line. a control circuit for
`controlling reading of data from the memory cell array and
`writing of data to the memory cell array, :1 potential setting
`circuit for setting low level potential line of bit
`lines.
`memory cells and sense amplifier to a potential higher than
`the low level of the word lines. and a low level of the word
`lines forcing circuit for forcing. when data retention time of
`a memory cell is to be tested. the low level potential line of
`the bit lines, memory cell and sense amplifier to the low
`level of the word lines.
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`According to a still further aspect of the present invention,
`the semiconductor memory device provided with chips
`formed on a semiconductor substrate includes a memory cell
`array including memory cells each connected to one of a
`plurality of bit lines and one of a plurality of word lines, a
`word line driving circuit for driving a word line. a sense
`amplifier for amplifying a small potential diiference read
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`5,687,123
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`6
`FIG. 15 is a schematic diagram showing a first embodi-
`ment in accordance with a fourth aspect of the present
`invention.
`
`FIG. 16 shows an example of a switch circuit shown in
`FIG. 15.
`
`FIG. 17 is a time chart showing operation of the embodi-
`ment of FIG. 15.
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`10
`
`FIG. 18 is a block diagram showing a second embodiment
`in accordance with the fourth aspect of the present invention.
`FIG. 19 is a schematic diagram showing an example of a
`switch circuit shown in FIG. 18.
`
`5
`
`from the memory cell array to a bit line. a control circuit for
`controlling reading of data from the memory cell array and
`writing of data to the memory cell array. and a potential
`setting circuit for setting. when data retention time of the
`memory cell is to be tested, the low level potential line of the
`word line driving circuit to a potential higher than the low
`level of the word lines.
`
`According to a still further aspect. the semiconductor
`memory device provided with chips formed on the semi-
`conductor substrate includes a memory cell array including
`memory cells each connected to one of a plurality of bit lines
`and one of a plurality of word lines. a sense amplifier for
`amplifying a small potential diflerence read from the
`memory cell array to a bit line. a control circuit for control-
`ling reading of data from the memory cell array and writing
`of data to the memory cell array. a substrate potential
`generating circuit for supplying a negative level substrate
`potential to the semiconductor substrate. and a substrate
`potential setting circuit for setting. when data retention time
`of the memory cell is to be tested. the substrate potential of
`the semiconductor substrate to a potential higher than the
`negative level substrate potential.
`The foregoing and other objects. features. aspects and
`advantages of the present
`invention will become more
`apparent from the following detailed description of the
`present
`invention when taken in conjunction with the
`accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. 1A and 1B are illustrations comparing concepts of
`the prior art and of the present invention.
`FIG. 2 is a schematic diagram showing a first embodiment
`of a first aspect of the present invention.
`FIG. 3 is a time chart showing the operation of the circuit
`of FIG. 2.
`
`FIG. 4 is a schematic diagram showing a second embodi-
`ment in accordance with the first aspect of the present
`invention.
`
`FIG. 5 is a schematic diagram showing a first embodiment
`in accordance with a second aspect of the present invention.
`FIG. 6 is a schematic diagram showing a second embodi-
`ment in accordance with the second aspect of the present
`invention.
`
`FIG. 7 is a schematic diagram showing a third embodi-
`ment in accordance with the second aspect of the present
`invention.
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`30
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`FIG. 20 is a time chart showing the operation of the
`embodiment shown in HG. 18.
`
`FIG. 21 is a time chart showing an operation of a third
`embodiment in a