Ulllted States Patent [19]
`Watanabe et al.
`
`US005956285A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,956,285
`Sep. 21, 1999
`
`[54] SYNCHRONOUS SEMICONDUCTOR
`MEMORY DEVICE WITH MULTI-BANK
`CONFIGURATION
`
`[75] Inventors: t1:1agyafvlgatanalje; Katsumi Dosaka,
`0t 0
`yogo’ apan
`[73] Assignee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo, Japan
`
`_
`[21] Appl' NO" 08/798’953
`[22] Filed;
`Feb 11, 1997
`_
`_
`_
`_
`_
`Forelgn Apphcatlon Pnonty Data
`[30]
`Apr. 22 1996
`[JP]
`Japan .................................. .. 8-100122
`7
`[51] Int. Cl.6 ..................................................... .. GllC 8/00
`[52] US. Cl.
`.... .. 365/230.03; 365/196
`[58] Field of Search ............................. .. 365/230.03, 196,
`365/191, 190
`
`[56]
`
`5,126,973
`5,384,745
`5,483,497
`
`References Cited
`U S PATENT DOCUMENTS
`'
`'
`6/1992 Gallia ............................... .. 365/230.03
`1/1995 Konishi
`...... .. 365/233
`1/1996 Mochizuki ....................... .. 365/230.03
`
`4/1997 Nakase .................................. .. 365/190
`5,621,693
`FOREIGN PATENT DOCUMENTS
`
`6-243674 9/1994 Japan .
`Primary Examiner_A' Zambian
`Attorney, Agent, or Firm—McDermott, Will & Emery
`[57]
`ABSTRACT
`
`.
`.
`Memory blocks provided to share a sense ampli?er bank, a
`global IO (GIOB) bus provided in common to the memory
`blocks for transferring internal data, and local IO bus lines
`provided corresponding to the memory blocks are
`connected-controlled based on signals related to a column
`select operation. Driving memory blocks independently
`from each other Permits each memory block to be used as a
`bank, and if one memory block is accessed during activation
`of another memory block, data can be prevented from
`colliding on the global IO bus. A main memory With high
`page hit rate is implemented using a semiconductor memory
`device With a shared-sense ampli?er con?guration. When a
`memory block sharing a sense ampli?er coupled to another
`memory block is addressed, the another memory block is
`inactivated and then addressed memory block is accessed,
`When a valid data is output, such valid data outputting is
`signaled by a data valid signal.
`
`9 Claims, 18 Drawing Sheets
`
`2
`
`8 13
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`
`COLUMN DECODER
`
`Apple – Ex. 1008
`Apple Inc., Petitioner
`1
`
`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 1 of 18
`
`5,956,285
`
`F 1 G. 1
`
`2
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`,
`
`COLUMN DECODER
`
`12/
`
`2
`
`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 2 of 18
`
`5,956,285
`
`FIG. 2
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`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet3 of 18
`
`5,956,285
`
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`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 4 of 18
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`5,956,285
`
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`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 5 of 18
`
`5,956,285
`
`
`
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`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 6 of 18
`
`5,956,285
`
`ACTIVE
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`
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`Us‘ Patent
`
`Sep- 21, 1999
`
`Sheet 7 of 18
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`5,956,285
`
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`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 8 of 18
`
`5,956,285
`
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`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 9 of 18
`
`5,956,285
`
`F 1 G. 1 4
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`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 10 of 18
`
`5,956,285
`
`F 1 G. 1 7
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`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 11 of 18
`
`5,956,285
`
`F I G. l 8
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`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 12 of 18
`
`5,956,285
`
`F 1 G. 2 0 A
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`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 13 of 18
`
`5,956,285
`
`
`
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`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 14 of 18
`
`5,956,285
`
`CLOCK P
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`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 15 of 18
`
`5,956,285
`
`F I G. 2 6
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`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 16 of 18
`
`5,956,285
`
`FIG. 29
`
`FIG. 30
`
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`
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`
`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 17 of 18
`
`5,956,285
`
`F I G. 3 l
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`

`
`U.S. Patent
`
`Sep.21, 1999
`
`Sheet 18 of 18
`
`5,956,285
`
`F I G. 8 4
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`

`
`5,956,285
`
`1
`SYNCHRONOUS SEMICONDUCTOR
`MEMORY DEVICE WITH MULTI-BANK
`CONFIGURATION
`
`BACKGROUND OF THE INVENTION
`
`2
`consideration of skeW (offset in timing) of the control signals
`and address signals. As a result, the timing for initiating
`internal operation is rendered faster and therefore the cycle
`time can be reduced, thus permitting accessing at higher
`speed.
`In a processing system such as image processing system
`the data bits of serial data addresses are sequentially
`accessed, While in the processing system a plurality of bits
`at serial memory positions are frequently accessed because
`of the localiZation of the process. Therefore, data is input/
`output in synchroniZation With a clock signal, the serial
`accessing time can be the same as that of the clock signal and
`the average access time can be comparable to that of the
`SRAM.
`In the SDRAM, the concept of multiple banks is further
`introduced. More speci?cally, a plurality of banks are pro
`vided in the SDRAM. These banks can be activated and
`inactivated (precharge) almost independently from each
`other.
`In a standard DRAM, a precharge operation must be
`performed in order to select a neW roW. DRAM has its
`internal signal lines dynamically driven, and therefore each
`signal line has to be maintained at a prescribed potential
`level at the time of precharging. For precharging, the time
`called RAS precharging time tRP is usually necessary (since
`each internal signal line should be returned to a prescribed
`potential level.) In the standard DRAM, time called RAS
`CAS delay time tRCD is necessary. This is because after a
`roW of memory cells have been selected in response to a roW
`address strobe signal /RAS, a column selecting operation
`must be executed in response to a column address strobe
`signal /CAS. Column address strobe signal /CAS must be
`returned to its inactive state at the of the completion of the
`column selecting operation. In order to select a memory cell
`on a neW page (a roW of memory cells), RAS precharge time
`tRP and RAS-CAS delay time tRCD are necessary, and
`therefore the cycle time of a standard DRAM is almost tWice
`its accessing time.
`HoWever, if a plurality of banks are provided in the
`SDRAM, and one bank being activated is accessed While
`another bank is returned to a precharge state (inactive state),
`that another bank in the precharge state may be accessed
`Without a Waiting time period for RAS precharge time tRP.
`Therefore, alternately or sequentially activating/precharging
`(inactivating) these banks permits RAS precharge time tRP
`to be seemingly eliminated, and therefore high speed access
`ing is alloWed. If one bank is accessed as another bank is
`precharged and activated, data can be Written/read out
`alternately to/from these banks, time loss by RAS precharge
`time tRP and RAS-CAS delay time tRCD may be
`eliminated, and therefore data can be Written/read at higher
`speed.
`In the above-described conventional SDRAM, a bank is
`formed using a memory array (memory mat) as a unit. The
`memory array (memory mat) has a plurality of memory
`blocks, and in one memory array, each memory block is
`driven into a selected or inactive state When a corresponding
`memory array is activated, and the memory blocks in a
`memory array cannot be activated/inactivated independently
`from each other. In the conventional SRAM, the number of
`banks is as feW as the number of memory arrays (memory
`mats) (usually four banks at most). This is because the array
`structure of a standard DRAM is employed for the array
`structure of the SDRAM, roW/column decoders are installed
`separately corresponding to each memory array (memory
`mat), so that these roW/column decoders can be driven
`independently for each memory array (memory mat).
`
`1. Field of the Invention
`The present invention relates generally to semiconductor
`memory devices, particularly to clock-synchronous semi
`conductor memory devices inputting/outputting data in syn
`chroniZation With a clock signal, and more particularly to a
`multi-bank semiconductor memory device having a plurality
`of banks inside.
`2. Description of the Background Art
`In recent years, microprocessors (MPUs) has come to
`have multiple functions, Which enables high speed process
`ing of a bulk of data. Accordingly, a Dynamic Random
`Access Memory (hereinafter referred to as DRAM) for use
`as main memory, has come to have an increased memory
`capacity as the miniaturiZing techniques have been devel
`oped. The operation speed of the DRAM, hoWever, cannot
`catch up With the operation speed of the MPU and the
`performance of the entire processing system is degraded
`With the bottleneck due to the time required for accessing the
`DRAM and the cycle time of DRAM. In order to prevent the
`performance of the processing system from being degraded,
`a high speed memory called cache memory, normally
`formed of a Static Random Access Memory (SRAM), is
`installed betWeen a DRAM and an MPU. Data/instruction
`frequently used by the MPU are stored in the cache memory
`and such data/instruction are transferred betWeen the MPU
`and the cache memory. Only When an instruction/data
`requested of accessing by the MPU is not present in the
`cache memory, the DRAM is accessed. It is highly probable
`that instructions/data required by the MPU are previously
`stored in the cache memory, and therefore the frequency of
`accessing the DRAM can be greatly reduced, thereby pre
`venting the operation speed of the processing system from
`being loWered.
`Since the SRAM for use in the cache memory is more
`expensive than the DRAM, the con?guration having such a
`cache memory installed is not suitable for relatively inex
`pensive devices such as personal computers. There is there
`fore a demand for improving the performance of processing
`system using inexpensive DRAMs. One solution to this is a
`synchronous DRAM (hereinafter referred to as SDRAM)
`Which is adapted to transfer data in synchroniZation With a
`clock signal such as system clock.
`In the SDRAM, an operation mode instruction signal is
`applied in a command form (a combination of the states of
`a plurality of control signals) in synchroniZation With a clock
`signal. In the SRAM, according to this command, a plurality
`of bits (such as 8 bits per one IO) are selected at a time and
`these simultaneously selected bits are sequentially output in
`synchroniZation With the clock signal. At the time of data
`Writing, data for Writing is sequentially taken and Written in
`a prescribed sequence into memory cells simultaneously
`selected in synchroniZation With a clock signal.
`In the SDRAM, in synchroniZation With a rising edge of
`a clock signal, externally applied control signals forming a
`command, in other Words a roW address strobe signal /RAS,
`a column address strobe signal /CAS, a Write enable signal
`/W E, and an address signal and data for Writing are taken in
`for executing internal operation. In synchroniZation With the
`clock signal, externally applied data is input and data is
`output. Therefore it is not necessary to secure a margin for
`a timing for inputting/outputting data, Which takes into
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`Use of such a conventional SDRAM with a plurality of
`banks as a main memory for a processing system will be
`considered. All the banks of the SDRAM are activated at a
`
`time, a row (page) of memory cells are maintained in a
`selected state in each bank. A sense amplifier provided
`corresponding to each column of memory cells is used as a
`pseudo cache. If data/instruction requested by the MPU is
`not stored in the cache memory (at the time of cache miss),
`it is determined whether or not the data/instruction requested
`of accessing by the MPU is present in the selected page of
`the SDRAM (page hit/miss determination). At the time of
`page hit, the corresponding page is accessed for transferring
`the block of data/instructions (cache block) to the cache
`memory, and the data/instruction requested of accessing is
`transferred to the MPU (for read accessing). Therefore, at
`page hit, it is requested that the block of the data instructions
`is selected from the page for reading out, and therefore after
`elapse of CAS access time ta(CAS) (or CAS latency) the
`necessary data/instruction may be transferred to cache
`memory and to the MPU (for read accessing).
`Meanwhile, in the case of page miss, the bank storing the
`data/instruction requested of accessing is once driven into a
`precharge state (inactive state), then after the page storing
`data/instruction required is brought into a selected state, the
`block including the requested data/instruction is transferred
`to the cache memory. If the page miss occurs,
`in the
`SDRAM,
`the bank should be once precharged and then
`activated, and the column must be selected from the selected
`page. The data/instruction requested is transferred to the
`cache memory after elapse of the total time period of RAS
`precharge time tRP, RAS-CAS delay time tRCD, and CAS
`accessing time ta (CAS) (or CAS latency). During the
`period, the MPU is in a wait state.
`Therefore,
`if the conventional multi-bank SDRAM is
`used as a main memory with a small number of banks, the
`number of pages to be in a selected state is small (the same
`as the number of banks),
`its page hit rate is small, and
`penalty at the time of page miss (the wait time for the MPU)
`is large.
`
`SUMMARY OF THE INVENTION
`
`It is therefore an object of the invention to provide a
`semiconductor memory device with a new configuration
`having a plurality of banks with increased page hit rate.
`Another object of the present invention is to provide a
`semiconductor memory device with a plurality of banks
`capable of accurately inputting/outputting (writing/reading)
`required data.
`Yet another object of the invention is to provide a semi-
`conductor memory device having a plurality of banks, using
`an array structure similar to a standard DRAM.
`A semiconductor memory device according to a first
`aspect of the invention includes a memory array having a
`plurality of memory blocks each with a plurality of memory
`cells arranged in rows and columns, a plurality of local
`input/output buses provided corresponding to each of these
`plurality of memory blocks each for transferring data to and
`from a selected column of a corresponding memory block,
`a global
`input/output bus provided in common for the
`plurality of memory blocks, bank activation circuitry pro-
`vided corresponding to each of the plurality of memory
`blocks, selectively activated in response to a first bank
`address and an operation mode instruction signal for acti-
`vating a corresponding memory block when activated, a
`plurality of bank select switches provided between each of
`the plurality of local
`input/output buses and the global
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`input/output bus for electrically connecting a corresponding
`local input/output bus and the global input/output bus when
`activated, and bank select control circuitry responsive to a
`column select operation instruction signal and a bank
`address signal applied simultaneously with the column
`select operation instruction signal for activating the bank
`select switch of a local input/output bus provided corre-
`sponding to a memory block specified by the simultaneously
`applied bank address signal.
`A semiconductor memory device according to a second
`aspect
`includes a memory array having a plurality of
`memory blocks having a plurality of memory cells arranged
`in rows and columns and aligned along the direction of
`columns, a plurality of sense amplifier bands provided
`between adjacent memory blocks in the memory array for
`sensing and amplifying data in a memory cell on a column
`of a corresponding memory block when activated, a plural-
`ity of block isolation/connection circuitry provided between
`each memory block and each of the plurality of sense
`amplifier bands for connecting each column of a correspond-
`ing memory block to a corresponding sense amplifier band
`when activated,
`isolation/connection control circuitry for
`inactivating the block isolation/connection circuitry pro-
`vided to a memory block sharing a sense amplifier band with
`a memory block addressed in response to a bank address
`signal, and sense activation control circuitry provided cor-
`responding to each of the plurality of sense amplifier bands
`and responsive to the bank address signal and a sense
`activating signal for activating the sense amplifier band
`provided to the addressed memory block. The sense activa-
`tion control circuitry includes a memory for storing bank
`address data to specify a memory block which has used a
`corresponding sense amplifier band most recently, and deter-
`mination circuitry for determining match/mismatch of the
`bank address data stored in the memory and an applied bank
`address.
`
`A semiconductor memory device according to a third
`aspect
`includes a memory array having a plurality of
`memory cells arranged in rows and columns, row select
`circuitry activated in response to array activation instruction
`signal for selecting a row in the memory array according to
`a first address signal, reading circuitry activated in response
`to a read operation instruction signal for selecting the row in
`the memory array in response to a second address signal
`simultaneously applied with the read operation instruction
`signal and reading out the data of memory cells on the
`selected column externally from the device, and data valid
`signal output circuitry for outputting externally from the
`device a data valid signal indicating that the data read out
`from the reading circuitry is valid in response to the read
`operation instruction signal.
`Since the memory array is divided into a plurality of
`memory blocks each of which can be driven independently
`from each other, the number of banks may be increased, and
`page hit rate may be increased accordingly.
`Furthermore, by connecting a local input/output bus and
`the global input/output bus in response to a signal related to
`column selection,
`the local
`input/output bus and global
`input/output bus can be connected only at
`the time of
`reading/writing operation, thereby permitting a plurality of
`banks to be activated at a time, and if a sense amplifier is
`maintained in an active state, the data of a plurality of banks
`may be prevented from being transferred onto the global
`input/output bus, and data can be read out accurately using
`a memory block as a bank.
`In the shared sense amplifier configuration in which
`adjacent memory blocks shares a sense amplifier band, when
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`a bank adjacent to a bank in an active state is accessed, the
`adjacent memory block in the active state is driven into an
`inactive state in order to prevent collision of data in the sense
`amplifier band, and data may be sensed and amplified. Since
`the inactive state is automatically established inside the
`device, an external device does not need a mechanism for
`preventing such collision of data in the sense amplifier band,
`and therefore the load of control for memory accessing by
`the external device (memory controller or processor) is
`alleviated.
`
`In addition, at the time of outputting valid data, the signal
`indicating that the valid data is output is externally output,
`and therefore the external device can be accurately notified
`of the timing for the valid data to be output.
`Furthermore,
`if the confiiction is caused for a sense
`amplifier band, a command input prohibition signal is output
`externally, the external device can be notified that a coun-
`termeasure for preventing such sense amplifier band conflict
`is executed inside the semiconductor memory device, apply-
`ing a next mode instruction signal can be surely prevented
`during the operation period and therefore erroneous access-
`ing to the device may be prevented.
`The foregoing and other objects, features, aspects and
`advantages of the present
`invention will become more
`apparent from the following detailed description of the
`present
`invention when taken in conjunction with the
`accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a diagram schematically showing the overall
`configuration of a semiconductor memory device according
`to the invention;
`FIG. 2 is a diagram schematically showing the configu-
`ration of an array driving circuit shown in FIG. 1;
`FIG. 3 is a timing chart for use in illustration of the
`operation of the array driving circuit shown in FIG. 2;
`FIG. 4 is a diagram schematically showing a configura-
`tion of a memory block and a sense amplifier band shown in
`FIG. 1;
`FIG. 5 is a diagram for specifically showing the configu-
`ration of the sense amplifier band shown in FIG. 4;
`FIG. 6 is a diagram schematically showing the configu-
`ration of a control circuit for connecting a local IO bus and
`a global IO bus shown in FIG. 5;
`FIG. 7 is a diagram schematically showing the configu-
`ration of a portion generating a control signal shown in FIG.
`6;
`
`FIG. 8 is a diagram schematically showing the configu-
`ration of a bit line isolation signal generation portion shown
`in FIG. 5;
`FIG. 9 is a timing chart for use in illustration of the
`operation of a semiconductor memory device according to a
`first embodiment of the invention;
`FIG. 10 is a diagram schematically showing the configu-
`ration of a main portion of a semiconductor device accord-
`ing to a second embodiment of the invention;
`FIG. 11 is a diagram schematically showing the configu-
`ration of an array driving circuit shown in FIG. 10;
`FIG. 12 is a diagram schematically showing the configu-
`ration of a row select activation circuit shown in FIG. 1;
`FIG. 13 is a diagram schematically showing the configu-
`ration of a sense driving circuit shown in FIG. 11;
`FIG. 14 is a diagram schematically showing the configu-
`ration of a variation of the second embodiment of the
`invention;
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`FIG. 15 is a diagram schematically showing the configu-
`ration of a variation of the row select activation circuit
`
`according to the second embodiment of the invention;
`FIG. 16 is a diagram schematically showing the configu-
`ration of a main portion of a semiconductor memory device
`according to a third embodiment of the invention;
`FIG. 17 is a diagram schematically showing the configu-
`ration of a column select portion in a semiconductor
`memory device according to a fourth embodiment of the
`invention;
`FIG. 18 is a diagram schematically showing the configu-
`ration of a data input/output portion in a semiconductor
`memory device according to the invention;
`FIG. 19 is a diagram schematically showing the configu-
`ration of a column select control circuit shown in FIG. 17;
`FIG. 20A is a diagram schematically showing the con-
`figuration of an output buffer in FIG. 18;
`FIG. 20B is a diagram schematically showing the con-
`figuration of an output control circuit in FIG. 19;
`FIG. 21 is a diagram schematically showing the configu-
`ration of a main portion of a data memory device according
`to the fourth embodiment of the invention;
`FIG. 22 is a timing chart for use in illustration of the
`operation of circuits shown in FIGS. 20 and 21;
`FIG. 23 is a diagram showing the configuration of a valid
`data signal output portion according to a fifth embodiment of
`the invention;
`FIG. 24 is a timing chart for use in illustration of the
`operation of the circuit shown in FIG. 23;
`FIG. 25 is a diagram schematically showing another
`configuration of the data valid signal output portion accord-
`ing to the fifth embodiment of the invention;
`FIG. 26 is a diagram schematically showing the configu-
`ration of a data valid signal output portion according to a
`sixth embodiment of the invention;
`FIG. 27 is a timing chart for use in illustration of the
`operation of the data valid signal output portion shown in
`FIG. 26;
`FIG. 28 is a timing chart for use in illustration of the
`operation of a data valid signal output portion according to
`a seventh embodiment of the invention;
`FIG. 29 is a diagram schematically showing the configu-
`ration of a data valid signal output portion implementing the
`operation timing in FIG. 28;
`FIG. 30 is a diagram schematically showing the configu-
`ration of a variation of the data valid signal output portion
`according to the invention;
`FIG. 31 is a diagram schematically showing the configu-
`ration of a data valid signal output portion according to an
`eighth embodiment of the invention;
`FIG. 32 is a diagram showing the configuration of a 1-bit
`portion in the output circuit shown in FIG. 31;
`FIG. 33 is a timing chart for use in illustration of the
`operation of the output circuit shown in FIG. 31; and
`FIG. 34 is a diagram showing the configuration of a
`variation of the eighth embodiment of the invention.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`FIG. 1 is a diagram schematically showing the overall
`configuration of a semiconductor memory device according
`to the invention. In FIG. 1,
`the semiconductor memory
`device includes memory blocks MB#0—MB#N each having
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`a plurality of memory cells arranged in a matrix of rows and
`columns, sense amplifier bands SA#1—SA#N provided
`between these memory blocks, a sense amplifier band SA#0
`provided outside memory block MB#0, and a sense ampli-
`fier band SA#N+1 provided adjacent
`to the outside of
`memory block MB#N. These sense amplifier bands SA#1 to
`SA#N (whose configuration will be later described in detail)
`are shared between adjacent memory blocks. A selected
`memory block is connected to a corresponding sense ampli-
`fier band, and a non-select memory block paired with the
`select memory block is isolated from the corresponding
`sense amplifier band.
`Array driving circuits DR#0—DR#N for activating/
`inactivating each memory block are provided to memory
`blocks MB#0 to MB#N, sense/connection control circuits
`SID#0 to SID#N+1 for controlling activation/inactivation of
`sense amplifiers included in a sense amplifier band are
`provided to sense amplifier bands SA#0 to SA#N+1. Array
`driving circuits DR#0 to DR#N each include a row decoder
`and a word line driver and generates a control signal related
`to a row selecting operation to a corresponding memory
`block when activated. Since these array driving circuits
`DR#0 to DR#N are activated/inactivated independently
`from each other each include a signal latch circuit such as
`row address latch circuit, though not explicitly shown.
`Sense/connection control circuits SID#0 to SID#N+1
`each activate a sense amplifier included in a corresponding
`sense amplifier band in response to a sense activation signal
`applied from a corresponding array driving circuit, and as
`will be described later, each includes a connection control
`circuit
`for controlling connection/isolation between a
`memory block and a sense amplifier band, and connection
`between a local IO bus (a data input/output bus provided to
`each memory block) and a global IO bus (a data input/output
`bus provided in common to all the memory blocks).
`The semiconductor memory device further includes a
`command latch 2 for latching an externally applied com-
`mand CM in synchronization with a clock signal P, a bank
`address latch 4 for latching an externally applied bank
`address signal in synchronization with clock signal P, an
`address latch 6 for latching an externally applied address
`signal in synchronization with clock signal P, a command
`decoder 8