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`USO052672l4A
`.
`5,267,214
`[11] Patent Number:
`[19]
`Ulllted States Patent
`
`Fujishima et al.
`[45] Date of Patent:
`Nov. 30, 1993
`
`.
`
`NIR
`4
`RED-
`IN OL
`[5 1 AL
`DYNAMIC TYPE SEMICONDUCTOR
`MEMORY DEVICE AND OPERATING
`METHOD THEREFOR
`Inventors: Kazuyasu Fujishima; Yoshio
`Matsuda; Kazutami Arimoto; Tsukasa
`Ooishi; Masaki Tsukude, all of
`HYOSO» Japan
`
`[75]
`
`[73] Assignee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo, Japan
`
`[21] Appl‘ NO’: 616’264
`[22] Filed:
`No“ 20’ 1990
`
`Foreign Application Priority Data
`[30]
`Feb. 16, 1990 [JP]
`Japan .................................... 2-36666
`
`Int. c1.s ............... ..
`[51]
`[52] U.S. Cl. .................... ..
`
`...................... .. G11C 11/34
`365/230.03; 365/230.06;
`365/149; 365/208
`[58] Field of Search ................. .. 365/230.03, 207, 208,
`365/230.06, 149, 189.11
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,241,425 12/1980 Cenker et al.
`................ .. 365/230.03
`4,351,034
`9/1982 Eaton, Jr. et al.
`..
`______ _. 365/189
`365/230.06
`5,014,246
`5/1991 Komatsu et al.
`5,016,224
`5/1991
`
`FOREIGN PATENT DOCUMENTS
`57-100689
`6/1982 Japan .
`60-694
`l/1985 Japan .
`Primary Examiner—Eugene R. LaRoche
`A-‘S’.-‘tan’ E"“’”i”9"‘_V“ LC
`_
`Attorney, Agent, or Firm-—-Lowe, Price, LeBlanc &
`Becker
`[57]
`
`ABSTRACT
`
`A dynamic random access memory amplifier arrange-
`ment includes a sense amplifier band shared between
`two different memory blocks. In this memory, only
`sense amplifiers related to a selected memory block are
`activated. The memory comprises a circuit for boosting
`a control signal voltage to a switching unit for connect-
`ing the selected memory block to the sense amplifiers
`“P t0 3 ‘"51 hlgher ma“ 3 P°“’°’ SUPPIY V°1‘aSe V°°
`during the activation of the sense amplifiers, and a cir-
`cuit for separating a memory block paired with the
`selected memory block from the activated sense ampli-
`fiers during the sensing operation. The memory further
`comprises a circuit for generating a control signal of the
`power supply voltage Vcc and connecting all the mem-
`ory blocks to the corresponding sense amplifiers in a
`stand-by state wherein a row address strobe signal is
`inactive. With this arrangement, a highly reliable mem-
`°’Y °°"5““““3 1655 P°W“" C“ be "°h‘°V°d “’h‘°h 3”‘
`sures data writing and/or rewriting at a full Vcc level.
`
`9 Claims, 15 Drawing Sheets
`
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`Apple — Ex. 1006
`Apple Inc., Petitioner
`1
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`Apple – Ex. 1006
`Apple Inc., Petitioner
`1
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`

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`4..netaP&U
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`Nov. 30, 1993
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`Sheet 1 of 15
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`Nov. 30, 1993
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`Sheet 3 of 15
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`F IG. 2 PRIOR ART
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`
`U.S. Patent
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`Nov. 30, 1993
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`Sheet 4 of 15
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`
`U.S. Patent
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`Nov. 30, 1993
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`Sheet 5 of 15
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`5,267,214
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`U.S. Patent
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`Nov. 30, 1993
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`Sheet 6 of 15
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`5,267,214
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`Nov. 30, 1993
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`Sheet 8 of 15
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`U.S. Patent
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`Nov. 30, 1993
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`Sheet 9 of 15
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`Nov. 30, 1993
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`U.S. Patent
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`Nov. 30, 1993
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`Sheet 11 of 15
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`5,267,214
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`U.S. Patent
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`Nov. 30, 1993
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`Sheet 12 of 15
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`U.S. Patent
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`Nov. 30, 1993
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`Sheet 14 of 15
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`5,267,214
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`Nov. 30, 1993
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`
`1
`
`5,267,214
`
`SHARED-SENSE AMPLIFIER CONTROL SIGNAL
`GENERATING CIRCUIT IN DYNAMIC TYPE
`SEMICONDUCIOR MEMORY DEVICE AND
`OPERATING METHOD THEREFOR
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates generally to dynamic
`type semiconductor memory devices, particularly to a
`semiconductor memory device having a shared sense
`amplifier arrangement wherein one sense amplifier is
`shared between the columns in two different memory
`blocks. More specifically, the present invention relates
`to circuit for generating a control signal to connect
`shared sense amplifiers to the corresponding columns,
`2. Description of the Background Art
`In a dynamic type semiconductor memory device
`(DRAM), information is stored in the form of electric
`charges in a capacitor. In reading data,
`the signal
`charges stored in the capacitor are transferred onto a bit
`line (data line). A small change in potential is produced
`on the bit line depending on the existence of the signal
`charges transferred onto the bit line, and the potential
`change is sensed and amplified by a differential opera-
`tion type sense amplifier to read the information.
`As a semiconductor memory device is highly inte-
`grated to reduce the size of a memory cell, the inevita-
`ble is a tendency of reduction in storage capacitance of
`a memory capacitor. Various improvements have been
`made for obtaining sufficient difference in input poten-
`tials (signal voltage) for a sense amplifier against the
`reduced size of the memory cell followed by the re-
`duced storage capacitance.
`One of such conventional countermeasures is U.S.
`Pat. No. 4, 351,034 issued Sep. 21, 1982, entitled
`“Folded Bit Line-Shared Sense Amplifier” by S. S.
`Eaton et al. and assigned to Inmos Corporation. This
`U.S. patent employs the shared sense amplifier arrange-
`ment wherein a memory cell array is divided into two
`blocks and sense amplifiers are disposed and shared
`between the two blocks. During the sensing operation,
`only the columns in one block are connected to the
`sense amplifiers and the columns of the other block are
`subsequently connected to the sense amplifiers after the
`sensing operation.
`With the above-described arrangement, since the
`number of memory cells connected to one bit line can
`be reduced, parasitic capacitance of a bit line associated
`with the memory cells is reduced, so that even if the
`same amount of signal charges are transferred onto the
`bit line, potential change on the bit line can be almost
`twice that in a non-divided cell array. This is possible
`because the potential on the bit line varies in proportion
`to a ratio Cs/Cb of a memory cell capacitance Cs to a
`bit line capacitance Cb.
`The development of the above-described shared
`sense amplifier arrangement is a multi-divisional bit line
`arrangement as disclosed in Japanese Patent Laying
`Open No. 57-100689. In the multi-divisional bit line
`arrangement, a memory cell array is divided into four or
`more blocks and the number of sense amplifiers is in-
`creased in order to reduce the number of memory cells
`connected to one bit line. In this case, one sense ampli-
`fier is shared between two bit line pairs included in
`different memory cell blocks. It is structured such that
`in the operation, while a cell block including selected
`memory cells is connected to sense amplifiers to be
`
`5
`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`subjected to sensing operation, sense amplifiers con-
`nected to memory cell arrays without
`the selected
`memory cells is not activated to be placed in a standby
`state. This arrangement enables not only the enhance-
`ment in a read signal voltage from a memory cell but
`also the reduction of power consumption associated
`with charge/discharge of bit lines during the operation
`of the sense amplifiers because the sense amplifiers are
`selectively activated. Therefore this arrangement will
`be widely and in large capacity DRAMS of 4 megabits
`and 16 megabits.
`FIG. 1 is a diagram showing an arrangement of a
`modified conventional DRAM chip employing the
`multi-divisional bit line arrangement. FIG. 1 shows an
`example of an arrangement of 256 KW (kilo word) by
`one bit. Referring to FIG. 1, a semiconductor chip 100
`comprises an address input terminal 52 for receiving a
`row address RAO-RA8 and a column address CAO--
`CA8 applied in a time-division multiplexing manner, an
`input terminal 51 for receiving a row address strobe
`signal RAT for supplying timing of strobing the row
`address applied in the time-division multiplexing man-
`ner into the device, an input terminal 53 for receiving a
`column address strobe signal '(TA'§ for supplying timing
`of strobing the column address into the device, an input
`terminal 54 for receiving a read/write control signal
`R/W for defining reading/writing operations of the
`memory device, a data input terminal 55 for receiving
`input_data DIN, and a data output terminal 56 for sup-
`plying output data Dour. The semiconductor chip 100
`is further provided with a terminal for supplying a
`power supply voltage Vcc which becomes a reference
`voltage and a terminal for supplying a ground potential
`Vss, though they are not shown.
`In FIG. 1,
`the semiconductor memory device in-
`cludes a memory cell array divided into four memory
`blocks la, lb, 1c and Id each having one or more rows
`of memory cells and sense amplifier bands 2a and 2b
`shared between two blocks. The sense amplifier band 2a
`is shared between the memory cell blocks la and lb and
`the sense amplifier band 2b is shared between the mem-
`ory cell blocks 1c and 1d. The sense amplifier bands 2a
`and 2b include sense amplifiers provided corresponding
`to the respective columns (bit line pairs) of the corre-
`sponding block for differentially amplifying signal po-
`tentials on the corresponding columns in response to
`control signals SFU, SU, S—U and SFL, SL and K,
`respectively.
`Row decoders 3, word drivers 4, a row address buffer
`5, a row predecoder 13, a cbx (word line drive master
`signal) generating circuit 7 and a (bx subdecoder 12 are
`provided for selecting one row (one word line) of the
`memory cell array in response to external address sig-
`nals. The row address buffer 5 receives 9-bit address
`signals A0—A8 applied to the address input terminals 52
`and generates complementary internal row address
`signals RAO, M-RA8 and ITS in response to inter-
`nal control signals from a RAS buffer 6.
`The row predecoder 13 decodes the internal row
`address signals RA2, RE—RA7 and T57 from the row
`address buffer circuit 5 and generates a total of 12
`predecoded signals X1—X4 (generically represented as
`Xi), X5—X8 (generically represented as Xj) and X9—X12
`(generically represented as Xk). While the correspon-
`dence of the predecoded signals X1-X12 to the memory
`cell blocks is arbitrary, for the purpose of the simplicity
`of description, it is assumed in the following that the
`
`17
`
`17
`
`

`
`5,267,214
`
`3
`predecoded signals Xi (Xl—X4) are used as signals for
`designating memory cell blocks.
`FIG. 2 schematically shows arrangements of the
`address buffer 5 for generating internal row address
`signals RA2 and RA3, and RA2 and E3 from the
`external address signals A2 and A3 and the row prede-
`coder 13 for generating the predecoded signals Xi. In
`FIG. 2, the row address buffer 5 includes a buffer cir-
`cuit 5a for generating the internal row address signals
`RA2 and E2 complementary with each other in re-
`sponse to the external address signal A2 and a buffer
`circuit Sb for generating the internal row address signals
`RA3 and $3 complementary with each other in re-
`sponse to the external address signal A3.
`The row predecoder 13 includes a decoder circuit
`13a for generating the predecoded signal X1 in response
`to the internal row address signals RA2 and RA3, a
`decoder circuit 13b for generating the predecoded sig-
`nal X2 in response to the internal row address signals
`RA3, a decoder circuit 13c for generating the prede-
`coded signal X3 in response to the internal row address
`signals RA2 and RX3, and a decoder circuit 13d for
`generating the predecoded signal X4 in response to the
`internal row address signals ‘T and IE3. Each of the
`predecoder circuits 13a to 13d has the‘ same circuit
`arrangement. When the predecoded signals X1 to X4
`are used as block designating signals, only one of the
`predecoded signals X1 to X4 enters a selected state to
`be, for example, a “H” (logical high) level. Each of the
`predecoder circuits 13a to 13d is comprised of an AND
`gate or NAND gate. The circuits for generating the
`other predecoded signals Xj and Xk have the same
`arrangement.
`Back to FIG. 1, the ¢X generating circuit 7 generates
`a word line drive master signal qbx for driving a word
`line in response to the internal clock signals from the
`RAS buffer 6 and applies the same to the qbx subdecoder
`12. The dax subdecoder 12 generates word line sub-
`decoded signals d>X1-¢X4 in response to the internal
`row address signals RAO, KAU, RA] and 155-1 and the
`word line driving signal «bx from the row address buffer
`5 to generate word line sub-decoded signals d>xl to cl>x4
`and applies the same to the word driver 4. Only one of
`the word line sub-decoded signals ¢xl—d>x4 rises to the
`“H” level.
`
`FIG. 3 is a schematic diagram of an arrangement of
`the cbx subdecoder. In FIG. 3, qbx subdecoder 12 in-
`cludes subdecoding circuit l2a—12d. The subdecoding
`circuit 120 selectively passes the word line driving mas-
`ter signal aim in response to the internal row address
`signals RAO and E1 to generate the word line sub-
`decoded signal <1>xl. The subdecoding circuit 12b selec-
`tively passes the word line driving master signal qbx in
`rflonse to the internal row address signals RAO and
`RA] to generate the word line sub-decoded signal ¢x2.
`The subdecoding circuit 12c selectively passes the word
`line driving master signal ¢x in response to the internal
`row address signals R-157) and RA1 to generate the word
`line sub-decoded signal d>x3. The subdecoding circuit
`12d selectively passes the word line driving master
`signal (bx in response to the internal row address signals
`RAO and RA1 to generate the word line sub-decoded
`signal d>x4.
`Back to FIG. 1, the row decoder 3 further decodes
`the predecoded signals Xi, Xj and Xk from the row
`predecoder 13 to generate decoded signals for selecting
`four word lines. The word driver 4 transmits the word
`line driving signal onto one word line in response to the
`
`4
`decoded signals from the row decoder 3 and the word
`line subdecoded signal d>x1—¢x4 from the qbx sub-
`decoder 12. FIG. 4 shows one example of a specific
`arrangement of the row decoder 3 and the word driver
`4.
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`FIG. 4 shows a unit row decoder and an associated
`word driver as representatives. Referring to FIG. 4, a
`unit row decoder 30 includes a 3-input AND circuit for
`receiving 3-bit predecoded signals Xi, Xj and Xk and an
`inverter for inverting an output of the NAND circuit.
`The NAND circuit includes a p channel insulated
`gate type field effect transistor (referred to as p MIS
`transistor hereinafter) PT1 and an n channel insulated
`gate type field effect transistor (referred to as n MIS
`transistor hereinafter) NT1 each having a gate for re-
`ceiving the predecoded signal Xi, an n MIS transistor
`NT2 with a gate for receiving the predecoded signal Xj,
`an n MIS transistor NT3 with a gate for receiving the
`predecoded signal Xk and a p MIS transistor PT2 with
`a gate for receiving inverter output. The p MIS transis-
`tors PT1 and PT2 are provided in parallel with each
`other between a power supply voltage Vcc and a node
`N1. The n MIS transistors NT1, NT2 and NT3 are
`connected in series between the node N1 and a ground
`potential Vss.
`The inverter includes a p MIS transistor PT3 and an
`n MIS transistor NT4 each having a gate for receiving
`an output of the NAND circuit. The p MIS transistor
`PT3 and the n MIS transistor NT4 are complementarily
`connected between the power supply potential Vcc and
`the ground potential Vss. The unit row decoder 30
`outputs the output of the NAND circuit (potential at
`the node N1) and an output of the inverter (potential at
`a node N2), which are transmitted to four word driving
`circuits.
`
`Four word driving circuits 4a, 4b, 4c and 4d are pro-
`vided for one unit row decoder 30. The word driving
`circuit 4a includes an n MIS transistor NT5 for trans-
`mitting the potential of the node N2 of the unit row
`decoder 30, an n MIS transistor NT6 having a gate for
`receiving the transmitted potential from n MIS transis-
`tor NT5 to selectively transmit
`the word line sub-
`decoded signal qbxl onto a word line WL1 and an n MIS
`transistor NT7 having a gate for receiving the potential
`at the node N1 of the unit row decoder 30 to selectively
`connect the word line WL1 to the ground potential.
`The transistor NT5 acts as a decoupling transistor for
`decoupling the gate of the transistor NT6 from the node
`N2.
`
`While each of the word driving circuits 4]), 4c and 4d
`has the samecircuit arrangement as that of the word
`driving circuit 4a, it differs from the circuit 40 in a name
`of the transmitted word line sub-decoded signal. More
`specifically,
`the word driving circuit 4b selectively
`transmits the word line sub-decoded signal ¢x2 onto a
`word line WL2 in response to the output of the unit row
`decoder 30. The word driving circuit 4c selectively
`transmits the word line sub-decoded signal d>x3 onto a
`word line WL3 in response to the output of the unit row
`decoder 30. The word driving circuit 4d selectively
`transmits the word line sub-decoded signal ¢x4 onto a
`word line WL4 in response to the output of the unit row
`decoder 30.
`
`In the unit row decoder 30, only when all the prede-
`coded signals Xi, Xj and Xk are at the “H” level, the
`potential of the node N1 attains an “L” (a logical low)
`level and correspondingly the potential of the node N2
`attains the “H” level. When the potential of the node N2
`
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`5
`is at the “H”, the n MIS transistor NT6 receives a signal
`of the “H” at its gate through the n MIS transistor NT5
`and becomes conductive in each of the word driving
`circuits 4a, 4b, 4c and 4d. As a result, the word line
`sub-decoded signal daxl-42x4 are transmitted onto the
`word lines WL1-WL4, respectively. Only one of the
`word line sub-decoded signal d>x1-x4 rises to the “H”
`level.
`Accordingly, only one of the word lines WL1—WLA
`is driven to the “H”.
`
`When at least one of the predecoded signals Xi, Xj
`and Xk is at the “L” level, the potential of the node N1
`attains the “H” level (charged through the p MIS tran-
`sistor PT2) and the potential of the node N2 attains the
`“L” level, so that the unit row decoder 30 enters a
`non-selection state.
`
`Back to FIG. 1 again, the semiconductor memory
`device further comprises a column address buffer 14 for
`receiving the address signals from the address input
`terminals 52 to select four columns of the memory cell
`array and for generating internal column address signals
`CAO-CA8 and C—zXT]-Cl-4'3, a column predecoder 15 for
`decoding the internal column address signals CAO—CA7
`and from the column address buffer 14 to generate 16-
`bit predecoded signals Y1-Y4 (generically referred to
`as Yi hereinafter), Y5—Y8 (generically referred to as Yi
`hereinafter), Y9-Y12 (generically referred to as Yk
`hereinafter) and Y13—Y16 (generically referred to as Y
`hereinafter) and a column decoder 16 for generating a
`column selecting signal CS for selecting four columns in
`response to the column predecoded signals Yi, Yj, Yk
`and Y1. In response to an internal control signal gener-
`ated from a CAS buffer 19 in response to the column
`address strobe signal CAS, the column address buffer 14
`strobes addresses applied to the address input terminals
`52 to generate internal column address signals.
`The column predecoder 15 has the same arrangement
`as that of the row predecoder 13 shown in FIG. 2.
`FIG. 5 shows one example of the specific arrange-
`ment of the column decoder 16.
`Referring to FIG. 5, the column decoder 16 com-
`prises p MIS transistors PT10, PT11, PT12 and PT13
`connected in parallel with each other between the
`power supply voltage Vcc and a node N10, n MIS
`transistors NT10, NT11, NT12 and NT13 connected in
`series between the node N10 and the ground potential
`Vss, and an inverter for inverting a potential of the node
`N10 and transmitting the inverted potential to a node
`N11. The inverter includes a p MIS transistor PT14 and
`an n MIS transistor NT14.
`
`Each of the p MIS transistor PTIO and the n MIS
`transistor NT10 has a gate for receiving the column
`predecoded signal Yi. Each of the p MIS transistor
`PT11 and the n MIS transistor NT11 has a gate for
`receiving the column predecoded signal Yj. Each of the
`p MIS transistor PT12 and the n MIS transistor NT12
`has a gate for receiving the column predecoded signal
`Yk. Each of the p MIS transistor PT10 and the n MIS
`transistor NTl3 has a gate for receiving the column
`predecoded signal Yl. A column selecting signal CS is
`generated from the node N11. In the arrangement of the
`column decoder shown in FIG. 5, when all the column
`predecoded signals Yi, Yj, Yk and Y1 are at the “H”
`level, the potential of the node N10 attains the “L”,
`whereby the column selecting signal CS of the “H” is
`generated. -
`Back to FIG. 1 again, an I/O decoder 17 for selecting
`one of the four columns selected by the column decoder
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`16 is provided. The I/O decoder 17 decodes the internal
`row address signals RA8 and A from the row ad-
`dress buffer 17 and the internal column address signals
`CA? a from the column address buffer 14 and selects a
`pair of buses among four pairs of buses on 1/0 bus 40.
`A read/write control circuit 18, a read/write buffer
`20, an input buffer 21 and an output buffer 22 are pro-
`vided in order to receive/transfer data between the one
`pair of buses selected by the I/O decoder 17 and the
`external devices. In response to a read/write control
`signal R/W applied through the input terminal 54 and
`an internal control signal (internal CAS signal) applied
`from the CAS buffer 19, the read/write buffer 20 gener-
`ates a timing signal for defining data writing/reading
`and applies the same to the read/write control circuit
`18. The read/write control circuit 18 connects the pair
`of buses selected by the I/O decoder 17 with the input
`buffer 21 or the output buffer 22 in-response to the
`control signal from the read/write buffer 20.
`The input buffer 21 receive input data DIN applied
`through the input terminal 55 to generate the corre-
`sponding intemal data (ordinarily, complementary data
`pair). The output buffer 22 receives the internal data
`transferred from the read/write control circuit 18, con-
`verts the same into the corresponding output data
`Douf and applies the converted data to the output ter-
`minal 56.
`
`A shared sense amplifier control signal generating
`circuit 8 and a sense amplifier control circuit 23 are
`provided in order to selectively connect the sense am-
`plifier bands 2a and 2b to the memory cell blocks to
`operate the sense amplifiers included therein. The
`shared sense amplifier control signal generating circuit
`8, in response to the row predecoded signal Xi from the
`row predecoder 13, generates selective connection con-
`trol signals (shared sense amplifier control signals) SA,
`SB, SC and SD for the sense amplifier bands 2a and 2b
`and the memory blocks 1a—1d. The shared sense ampli-
`fier control signal SA controls connection between the
`sense amplifier band 2a and the memory cell block la.
`The shared sense amplifier control signal SB controls
`connection between the sense amplifier band 2a and the
`memory cell block lb. The shared sense amplifier con-
`trol signal SC controls connection between the sense
`amplifier band 2b and the memory cell block 1c. The
`shared sense amplifier control signal SD controls con-
`nection between the sense amplifier band 2b and the
`memory cell block 1d.
`The sense amplifier control circuit 23 generating a
`control signal for selectively activating the sense ampli-
`fiers includes an SF (sense fast) signal generating circuit
`9 responsive to the word line driving master signal (bx
`from the (fox generating circuit 7 and the predecoded
`signal Xi from the row predecoder 13, for generating
`signals SFU (sense fast upper blocks) and SFL (sense
`fast lower blocks) for activating sense amplifier in either
`the sense amplifier band 2a or 2b, a first sense amplifier
`activating signal generating circuit 10 responsive to the
`control signal from the SF signal generating circuit 9
`for generating first sense amplifier activating signals SU
`and SL, and a second sense amplifier activating signal
`generating circuit 11 responsive to the activating signals
`from the first sense amplifier activating signal generat-
`ing circuit 10 for generating second sense amplifier
`activating signals ‘SW and S—L. The control signal SFU is
`applied to the sense amplifiers included in the sense
`amplifier band 2a. The control signal SFL is transmitted
`to the sense amplifiers included in the sense amplifier
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`band 217. The first sense amplifier activating signals SU
`and SL activate the sense amplifiers comprising the n
`channel MIS transistors, which will be described later
`in detail. The second sense amplifier activating signals
`ST} and E activate the sense amplifiers comprising the
`p channel MIS transistors.
`'
`FIG. 6 shows one example of an specific arrangement
`of the SF signal generating circuit 9. Referring to FIG.
`6, the SF signal generating circuit 9 has two circuit
`portions, a circuit for generating the control signal SFU
`and a circuit for generating the control signal SFL.
`' Since these circuit portions have the same arrangement,
`FIG. 6 shows the circuit incorporated into one. Refer-
`ring to FIG. 6, the SF signal generating circuit 9 in-
`cludes a Sdelay circuit 60 for delaying the word line
`driving master signal (bx by a predetermined time per-
`iod, an OR gate 61 receiving the row predecoded sig-
`nals X1 and X2, and an AND gate 62 receiving outputs
`of the delay circuit 60 and the OR gate 61. The AND
`gate 62 generates the control signal SFU. When the OR
`gate 61 receives the row predecoded signals X3 and X4,
`the control signal SFL is generated from the AND gate
`62.
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`activating signals SU and SL, respectively, in the same
`circuit arrangement, that for the sense amplifier activat-
`ing signal SL is shown in parenthesis.
`While the arrangement of the first activating signal
`generating circuit 10 is not shown which generates the
`first activating signals SU and SL in response to the
`activating signal SFU (SFL) from the SF signal gener-
`ating circuit 9, any circuit arrangement for simply buff-
`ering the control signal SFL and SFU may be em-
`ployed.
`FIG. 8 shows arrangements of two pairs of bit lines in
`each of the memory cell blocks la and lb and the re-
`lated sense amplifier band 2a in detail. The bit lines are
`of the folded bit line pair arrangement wherein the bit
`lines BL and Br are provided in pair. A memory cell
`MC is disposed at a crossing portion between one word
`line WL and a pair of bit lines. The memory cell MC
`comprises a memory capacitor C for storing informa-
`tion in the form of electric charges and a memory tran-
`sistor MT responsive to a signal potential on the word
`line WL for connecting the memory capacitor to the bit
`line BL (or Ff).
`In order to differentially sense and amplify a signal
`potential on a bit line pair, provided to each bit line pair
`are a p channel sense amplifier PSA comprising cross
`coupled p MIS transistors PT40 and PT4l, a gate of the
`former coupled to a drain of the latter and a drain of the
`former to a gate of the latter, and an n channel sense
`amplifier NSA comprising cross coupled n MIS transis-
`tors NT40 and NT41, a gate of the former coupled to a
`drain of the latter and a drain of the former to a gate of
`the latter. In order to activate the p channel sense ampli-
`fier PSA, a p MIS transistor PT45 is provided which
`becomes conductive in res onse to the second sense
`amplifier activating signal U and transmits the power
`supply potential Vcc to sources of the p MIS transistors
`PT40 and PT4l. In order to activate the 11 channel sense
`
`amplifier NSA, provided are an n MIS transistor NT45
`which becomes conductive in response to the control
`signal SFU and transmits a potential of the ground
`potential Vss level to sources of the n MIS transistors
`NT40 and NT41, and an n MIS transistor NT46 which
`becomes conductive in response to the sense amplifier
`activating signal SU and similarly transmits the poten-
`tial of the ground potential Vss level to the sources of
`the n MIS transistors NT4-0 and NT4l. The signal SFU
`activates the transistor NT45 of a relatively small size to
`cause initial precise, but slow, sensing operation. The
`signal SU activates the transistor NT46 of a relatively
`large size to cause main rapid sensing operation.
`A precharging/equalizing circuit EQ is provided for
`precharging and equalizing each bit line pair to a prede-
`termined potential V3L when the semiconductor mem-
`ory device is in the stand by state (when the signal RAS
`is at the
`The precharging/equalizing circuit EQ
`comprises an n channel MIS transistor T20 being ren-
`dered conductive in response to an equalization in-
`structing signal BLEQ to electrically short-circuit the
`bit lines BL and K and 11 channel MIS transistors T21
`and T22 being rendered conductive in response to the
`equalization instructing signal BLEQ to transmit the
`predetermined potential V3; to the bit lines BL and BL.
`Bit line selecting switches BSA and BSB are pro-
`vided to each bit line pair in order to selectively connect
`the bit line pairs to the sense amplifiers. The selecting
`switch BSA selectively connects the bit line pair of BL
`and B—L of the memory cell block la to the sense ampli-
`fier band 20 in response to a selection control signal SA.
`
`20
`
`As clearly seen from FIG. 6, when the block la or lb
`includes the selected memory cells, the sense amplifiers
`included in the sense amplifier band 2a are activated. In
`addition, when the block 1c or 1d includes the selected
`memory cells, the sense amplifiers included in the sense
`amplifier band 2b are activated.
`FIG. 7 shows one specific example of a circuit ar-
`rangement wherein the second sense amplifier activat-
`ing signal S—U (W) is generated in response to the first
`sense amplifier activating signal SU (SL). Referring to
`FIG. 7,
`the second sense amplifier activating signal
`generating circuit 11 includes a delay stage for delaying
`the fi