(12) United States Patent
`Hidaka
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,233,181 B1
`May 15, 2001
`
`US006233181B1
`
`(54) SEMICONDUCTOR MEMORY DEVICE
`WITH IMPROVED FLEXIBLE
`REDUNDANCY SCHEME
`
`(75)
`
`Inventor: Hideto Hidaka, Hyogo (JP)
`
`(73) Assignee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo (JP)
`
`*
`
`(
`
`Notice:
`
`Sub'ect to an disclaimer, the term of this
`J
`y
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`5,892,718 *
`
`4/1999 Yamada .............................. .. 366/200
`
`FOREIGN PATENT DOCUMENTS
`
`6—232348
`6—237164
`
`8/1994 (JP) ............................. .. H01L/27/04
`8/1994 (JP) ......................... .. H03K/19/0948
`
`OTHER PUBLICATIONS
`
`“A Flexible Redundancy Technique for High-Density
`DRAM’s”, by Horiguchi, et al., IEEE Journal of Solid State
`Circuits, vol. 26, No. 1, Jan. 1991, pp. 12-17.
`
`“Ultra LSI Memory”, Kiyoo ITO, Advanced Electronics
`Series I-9, published by Baifukan, pp. 350-371, Nov. 5,
`1994.
`
`Appl. No.: 09/251,352
`
`Filed:
`
`Feb. 17, 1999
`
`(21)
`
`(22)
`
`(30)
`
`Foreign Application Priority Data
`
`* cited by examiner
`
`Jun.9,1998
`Oct. 15, 1998
`
`(JP) ............................................... ..10—160466
`(JP) ............................................... .. 10—293421
`
`Primary Exami/1er—AndreW Q. Tran
`(74) Attorney, Agent, or Firm—McDermott, Will & Emery
`
`Int. Cl.7 ..................................................... .. G11C 7/00
`(51)
`(52) U.s. Cl.
`.................. .. 365/200; 365/230.03; 365/190;
`365/225.7
`
`(58) Field of Search ............................. .. 365/200, 230.03,
`365/190, 208, 225.7
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`(57)
`
`ABSTRACT
`
`A spare memory array having spare memory cells common
`to a plurality of normal sub-arrays having a plurality of
`normal memory cells is provided. A spare line in the spare
`array can replace a defective line in the plurality of normal
`sub-array. The defective line is efficiently repaired by
`replacement in an array divided into blocks or sub-arrays.
`
`5,761,138 *
`
`6/1998 Lee et al.
`
`........................... .. 365/200
`
`7 Claims, 31 Drawing Sheets
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`Apple — Ex. 1003
`Apple Inc., Petitioner
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`U.S. Patent
`
`May 15, 2001
`
`Sheet 2 of 31
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`US 6,233,181 B1
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`U.S. Patent
`
`May 15, 2001
`
`Sheet 3 of 31
`
`US 6,233,181 B1
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`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 4 of 31
`
`US 6,233,181 B1
`
`FIG. 4
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`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 5 of 31
`
`US 6,233,181 B1
`
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`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 6 of 31
`
`US 6,233,181 B1
`
`FIG. 7
`
`DEGENERATION OF
`
`ADDRESS SIGNAL BIT
`
`14
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`GENERATION or .1» si
`
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`
`7
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 7 of 31
`
`US 6,233,181 B1
`
`FIG. 8
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`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 8 of 31
`
`US 6,233,181 B1
`
`FIG. 10
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`MA#O
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`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 9 of 31
`
`US 6,233,181 B1
`
` NORMAL MEMORY SUB-ARRAY
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`FIG. 13
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`FIG. 14
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`10
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`
`10
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 10 of 31
`
`US 6,233,181 B1
`
`FIG.
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`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 12 of 31
`
`US 6,233,181 B1
`
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`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 14 of 31
`
`US 6,233,181 B1
`
`FIG. 21A
`
`MEMORY ARRAY MEMORY ARRAY
`
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`15
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`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 15 of 31
`
`US 6,233,181 B1
`
`FIG. 22
`
`(RA2, RA3) :
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`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 16 of 31
`
`US 6,233,181 B1
`
`
`
`DETECTION CKT
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`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 17 of 31
`
`US 6,233,181 B1
`
`FIG. 26
`
`FIG. 28
`
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`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 18 of 31
`
`US 6,233,181 B1
`
`FIG. 29
`
`
`
`ACT I VAT I ON
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`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 19 of 31
`
`US 6,233,181 B1
`
`FIG. 31
`
`d>WL
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`= Vpp
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`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 20 of 31
`
`US 6,233,181 B1
`
`F I" G. 3 3
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`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 21 of 31
`
`US 6,233,181 B1
`
`FIG. 36
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`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 22 of 31
`
`US 6,233,181 B1
`
`FIG. 38
`
`
`
`FIG. 39
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`‘¢CUp
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`GENERAT I NG CKT ¢ CUP
`
`23
`
`
`
`23
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 23 0131
`
`US 6,233,181 B1
`
`FIG. 41
`
`MAB5
`
`MAB6
`
`MAB7
`
`MAB8
`
`NORMAL
`MEMORY
`
`BLOCK
`
`NORMAL
`MEMORY
`
`BLOCK
`
`NORMAL
`MEMORY
`
`BLOCK
`
`NORMAL
`MEMORY
`
`BLOCK
`
`NMAB8 NORMAL :
`
`MEMORY }
`BLOCK
`n3"B
`
`NORMAL
`MEMORY
`BLOCK
`
`NORMAL
`MEMORY
`BLOCK
`
`NORMAL
`MEMORY
`BLOCK
`
`NMAB3
`
`NMAB4
`
`MAB1
`
`(RBx#)
`
`MAB2
`
`MAB3
`
`MAB4
`
`(1,1)
`
`(0,0,
`
`(RA2, RA3)
`
`24
`
` 7/
`
`swg
`
`A M
`
`MAB8
`
`:NORMAL MODE
`
`
`
`24
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 24 of 31
`
`US 6,233,181 B1
`
`FIG. 43
`
`mar
`
`:RA
`
`(1:31
`
`1
`
`SPARE HIT
`
`¢B2-8
`
`NWL
`
`11
`:§’,
`y—H|T
`' '1
`K MISS
`
`_-
`
`(QM QA3)
`:REFRESH MODE
`SPARE DETERMINATION —+ sw SELECTION
`
`25
`
`
`
`25
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 25 of 31
`
`US 6,233,181 B1
`
`FIG. 45
`
`SPARE HIT
`
`¢>B1-q5B8
`
`NWL
`
`SWL
`
`F I G. 4 6 A
`
`/0A1
`
`0A2
`
`0A3
`
`/RACT
`
`/HIT
`
`71
`
`F I G. 4 6 B
`
`72
`
`4:31
`
`NORMAL MoDE—+§e REFRESH MODE
`
`/RACT
`
`QACT
`
`03:31
`
`0A f
`
`
`
`/Hn /////////////////////////////////////Z
`
`OUTPUT OF
`NAND71
`
`26
`
`
`
`26
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 26 of 31
`
`US 6,233,181 B1
`
`FIG. 47A
`
`(/QACT)
`
`OA2,/OA2
`
`OA1./OA1
`
`QA3,/QA3
`
`FIG. 47B
`
`/RACT
`
`QACT
`
`NORMAL MODE-——e+e——-SELF-REFRESH MODE
`
`RA /////////,—"/////
`
`GA
`/HITI i E
`
`¢BJ' '
`
`FIG. 48
`
`d>RX
`
`
`
`WORD LINE DRIVE
`TIMING CONTROL OKT
`
`SR
`
`
`
`¢WL
`
`27
`
`
`
`27
`
`

`
`tnuCtaP3U
`
`May 15,2001
`
`Sheet 27 of 31
`
`US 6,233,181 B1
`
`8
`
`
`
`>._n_n=._mEgon.
`
`
`
`maoomav_oSm
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`5.0
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`8
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`gg
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`x:a3§
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`2
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`2o_._.<z__5mEa
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`xas
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`.55
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`mm_Eo<zmwfimm
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`8
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`55._<~m:n_:m_n_nm:<._m~T;S_o._.
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`Gin:Tl:1|>|llJ
`
`as:1.2
`
`82
`
`
`
`28
`
`
`
`
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 28 of 31
`
`US 6,233,181 B1
`
`FIG. 50A
`
`(0, 0)
`
`(1,0)
`
`:BEFORE SPARE DETERMINATION DEFINED
`NORMAL MODE
`
`(A2, A3)
`
`FIG. 50B
`
`
`
`:AFTER SPARE DETERMINATION DEFINED
`NORMAL MODE
`
`(RA2,RA3)
`
`29
`
`
`
`29
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 29 of 31
`
`US 6,233,181 B1
`
`
`
`QA3
`\
`
`(PRESENT CYCLE OR PREVIOUS CYCLE)
`92
`"L" m STAND-BY sme
`
`F I G . 5 1 B
`
`/RAGT
`
`0A
`
`/HIT
`
`¢>B1
`
`NORMAL WL usen
`__L/__
`
`"
`
`F I G . 5 2
`
`RA1,/RA1
`RA2,/RA2
`
`RA3. /RA3
`
`mm)
`
`75
`
`H”
`
`77
`
`
`
`OA1, /QA1
`
`QA2, /QA2
`
`QA3. /QA3
`
`74
`
`(PRESENT CYCLE OR PREVIOUS CYCLE)
`
`¢BJ
`
`j=2—8
`
`30
`
`
`
`30
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 30 of 31
`
`US 6,233,181 B1
`
`F I G. 53 PRIORART
`
`MAO
`
`SW01
`swoo
`
`SW11
`sw1o
`
`MA1
`
`MA2
`
`SW21
`swzo
`
`SW31
`swso
`
`MA3
`
`'
`I
`I
`
`I Yo
`I
`1
`Inn}
`wo
`j.__L
`X0
`'
`
`:
`I
`I
`,
`I
`
`1
`1
`.I———
`
`w2
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`I
`
`I
`1
`I
`I
`:
`.
`we
`—-—--l-
`
`Y1
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`I
`I
`1
`I
`1
`:
`I
`.
`
`2
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`‘I
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`I.
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`2
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`ao—an—3
`
`an-2, an-I 0
`
`"'2
`
`2
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`E
`l
`
`l
`
`E
`
`F I G. 54 PRIORART
`
`MBi
`
`I055
`
`DEFECT IVE
`SENSE AMPLIFIER
`
`-
`"BM
`
`DEFECTIVE
`
`SPARE COLUMN
`
`"""""""""’,F"“
`
`DEFECT IVE
`
`ys L | NE
`
`Y
`
`
`
`31
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 31 of 31
`
`US 6,233,181 B1
`
`FIG. 55 PRIORART
`
`Vcc
`
`HlGH—Vth
`
`HIGH-Vth
`
`¢>A0T—-I
`
`Vss
`
`F I G. 56 PRIORART
`
`902
`
`904
`
`906
`
`LOW-Vth
`
`2/
`
`q5ACT
`
`'
`
`
`
`904
`
`906
`
`"""""" "
`
`I """" " V°°
`
`------------ --
`
`; _________ -.\‘Vss
`
`STAND-BY CYCLE
`
`32
`
`
`
`32
`
`

`
`US 6,233,181 B1
`
`1
`SEMICONDUCTOR MEMORY DEVICE
`WITH IMPROVED FLEXIBLE
`REDUNDANCY SCHEME
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`
`The present invention relates generally to semiconductor
`memory devices, and more particularly, to a semiconductor
`memory device having a memory array divided into a
`plurality of memory blocks. More specifically, the present
`invention relates to a redundancy circuit for repairing a
`defective memory cell in a semiconductor memory device
`having such an array-divided arrangement and a power
`supply circuit provided corresponding to each block.
`2. Description of the Background Art
`In the semiconductor memory device, a defective memory
`cell
`is replaced with a spare memory cell
`in order to
`equivalently repair the defective memory cell to raise the
`yield of the products. A flexible redundancy scheme has
`been proposed in order to improve the use efficiencies of
`spare lines (word lines or bit lines) and spare decoders for
`selecting spare lines in a redundancy circuit configuration
`including spare memory cells (spare word lines and bit lines)
`for repairing such defective memory cells (see, for example,
`“A Flexible Redundancy Technique for High-Density
`DRAM’s”, Horiguchi et al., IEEE Journal of Solid-State
`Circuits, Vol. 26, No. 1, January 1991, pp. 12 to 17).
`FIG. 53 is a schematic diagram of the general configu-
`ration of a semiconductor memory device having a conven-
`tional flexible redundancy scheme. In FIG. 53, the semicon-
`ductor memory device includes four memory arrays MAO to
`MA3. In each of memory arrays MAO to MA3, a spare word
`line to repair a defective memory cell row is provided. In
`memory array MAO, spare word lines SW00 and SW01 are
`provided, and in memory array MA1, spare word lines
`SW11 and SW11 are provided. In memory array MA2, spare
`word line SW20 and SW21 are provided, and in memory
`array MA3, spare word lines SW30 and SW31 are provided.
`Row decoders X0 to X3 each for decoding an address
`signal to drive a normal word line provided corresponding to
`an addressed row into a selected state are provided corre-
`sponding to memory arrays MAO to MA3. A column
`decoder Y0 is provided between memory arrays MAO and
`MA1 to decode a column address signal
`to select an
`addressed column, and also a column decoder Y1 is pro-
`vided between memory arrays MA2 and MA3.
`The semiconductor memory device further includes spare
`decoders SDO to SD3 to store a row address at which a
`
`10
`
`15
`
`20
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`25
`
`30
`
`35
`
`40
`
`45
`
`is present, maintain a word line
`defective memory cell
`(defective normal word line) corresponding to this defective
`row address in a non-selected state when the defective row
`
`50
`
`is addressed and drive a corresponding spare word line into
`a selected state, an OR circuit G0 to receive output signals
`from spare decoders SDO and SD1, and an OR circuit G1 to
`receive output signals from spare decoders SD2 and SD3.
`The output signals of OR circuits G0 and G1 are provided
`in common to spare word line driving circuits included in
`row decoders X0 to X3. Spare decoders SDO to SD3 are
`commonly provided with array address signal bits an-2 and
`an-1 to address one of memory arrays MAO to MA3 and
`with intra-array address signals bits a0 to an-3 to address a
`row in the memory array. Row decoders X0 to X3 are
`provided with array address signal bits an-2 and an-1, and a
`row decoder is activated when a corresponding memory
`array is addressed. OR circuits G0 and G1 each correspond
`to two spare word lines provided for each of memory arrays
`MAO to MA3.
`
`55
`
`60
`
`65
`
`2
`Let us assume that normal word lines W0 and W1 are
`
`defective in memory array MAO, that a normal word line W2
`in memory array MA1 is defective, and that a normal word
`line W3 in memory array MA2 is defective. In this state, the
`address of word line W0 is programmed in spare decoder
`SDO, while the address of word line W1 is programmed in
`spare decoder SD2. The address of normal word line W2 is
`programmed in spare decoder SD3, and the address of
`normal word line W3 is programmed in spare decoder SD1.
`OR circuit G0 selects one of spare word lines SW00,
`SW10, SW20 and SW30, and the output signal of OR circuit
`G1 selects one of spare word lines SW01, SW11, SW21 and
`SW31.
`
`the output
`When normal word line W0 is addressed,
`signal of spare decoder SDO is driven into a selected state,
`and the output of OR circuit G0 is activated. In this state,
`array address signal bits an-2 and an-1 activate row decoder
`X0, and the remaining row decoders X1 to X3 are main-
`tained in a non-active state. Thus, a word line driving circuit
`included in row decoder X0 drives spare word line SW00
`into a selected state in response to the output signal of OR
`circuit G0. At this time, in row decoder X0, a decode circuit
`provided corresponding to normal word line W0 is main-
`tained in a non-active state. As a result, defective normal
`word line W0 is replaced with spare word line SW00.
`If defective normal word line W1 is addressed, the output
`signal of spare decoder SD2 attains an H level in a selected
`state, the output signal of OR circuit G1 attains an H level,
`and spare word line SW01 is selected. If defective normal
`word line W2 is addressed,
`the output signal of spare
`decoder SD3 attains an H level in a selected state, the output
`signal of OR circuit G1 attains an H level, and spare word
`line SW11 is selected. If defective normal word line W3 is
`
`addressed, the output signal of spare decoder SD1 attains an
`H level in a selected state, and spare word line SW20 is
`selected by OR circuit G0 accordingly. More specifically,
`defective normal word lines W0, W1, W2 and W3 are
`replaced with spare word lines SW00, SW01, SW11 and
`SW20, respectively.
`In this flexible redundancy scheme shown in FIG. 53, a
`single spare word line can be activated by any of a plurality
`of spare decoders. For example, spare word line SW20 can
`be driven into a selected state by spare decoder SDO or SD1.
`A single spare decoder can drive any of a plurality of spare
`word line into a selected state. For example, spare decoder
`SDO can drive any of spare word lines SW00, SW10, SW20
`and SW30 into a selected state. Thus, the spare word line and
`spare decoders do not correspond in one-to-one relation, and
`therefore the spare word lines and spare decoders can be
`more efficiently utilized. The number of spare word lines
`and the number of spare row decoders in a single memory
`array may be selected independently from each other as long
`as the numbers satisfy the following relation:
`L§R§M-L/m
`
`wherein M is the number of physical memory arrays, m the
`number of memory arrays whose defective normal word
`lines are replaced with spare word lines simultaneously, R
`the number of spare row decoders, and L the number of
`spare word lines in a single memory array. More specifically,
`M/m is the number of memory arrays which are logically
`independent from one another. As a result, M~L/m represents
`the number of spare word lines which are logically inde-
`pendent from one another for the entire memory. Herein, the
`logically independent spare word lines are spare word lines
`selected by different row addresses. For example, in FIG. 53,
`
`33
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`33
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`

`
`US 6,233,181 B1
`
`3
`if a normal word line is simultaneously selected in memory
`arrays MAO and MA2, memory arrays MAO and MA2 are
`not logically independent from each other. In the arrange-
`ment shown in FIG. 53, L=2, R=4, M=4 and m=1.
`By providing a spare row decoder common to memory
`arrays, a spare decoder does not have to be provided for each
`of spare word lines, which can restrain the chip area from
`increasing.
`The flexible redundancy scheme shown in FIG. 53 may be
`employed for repairing a defective column as well.
`In
`repairing a defective column, the previously mentioned prior
`art document describes a method of repairing a defective
`column where a memory array is divided into a plurality of
`sub-arrays. The document particularly describes the way of
`repairing a defective column in multi-divided bit lines in a
`shared-sense amplifier arrangement and in a shared I/O
`scheme.
`
`FIG. 54 is a schematic diagram of the configuration of an
`array portion in a semiconductor memory device according
`to a conventional flexible redundancy scheme. In FIG. 54,
`two memory blocks MBi and MBi+1 are shown. Memory
`blocks MBi and MBi+1 each include a normal bit line pair
`BL and /BL provided corresponding to each memory cell
`column and a spare bit line (spare column) for repairing a
`defective column. In FIG. 54, the spare bit line included in
`the spare column is not clearly shown.
`Normal bit lines BL and /BL at the same column address
`in memory blocks MBi and MBi+1 share a sense amplifier
`SA. Abit line isolation gate ILG is provided between sense
`amplifier SA and memory blocks MBi and MBi+1. Sense
`amplifier SA is connected to an internal data line pair I/O
`through an IO gate IOG which conducts in response to a
`column selecting signal YS from column decoder Y. A
`memory block including a selected memory cell (MBi, for
`example) is connected to sense amplifier SA and data is read
`out therefrom. In this case, a non-selected memory block
`(MBi+1) is disconnected from sense amplifier SA.
`In the above-described shared-sense amplifier
`arrangement, a defective column address must be pro-
`grammed for each of defects in normal bit lines, in a single
`memory block column selecting lines (YS lines) and sense
`amplifiers SA. For a normal bit line defect, the defective
`column address is programmed on a memory block basis.
`For a sense amplifier defect, the defective column address is
`so programmed as to use a spare column for each of memory
`blocks MBi and MBi+1 which share this defective sense
`
`amplifier. For a column selecting line (YS line) defect, the
`defective column address is programmed for each of the
`memory blocks connected to this column selecting line (YS
`line).
`At the time of programming, in order to use a single spare
`column decoder for a normal bit line defect, a sense ampli-
`fier defect and a column selecting line (YS line) defect,
`“Don’t care” is programmed at the time of programming a
`defective column address, an address to specify a memory
`block is invalidated, and spare columns are replaced simul-
`taneously in a plurality of memory blocks.
`In the previously mentioned document, a defective row is
`repaired by replacing the defective row with a spare word
`line provided within a memory array including that defective
`row. Thus, a spare word line must be provided for each of
`memory arrays, and the spare word lines are not efficiently
`utilized. If a defective normal word line in one memory
`array is replaced with a spare word line in another memory
`array, the control of the memory array related circuits will be
`complicated, and therefore such arrangement must be
`avoided and is not considered at all.
`
`4
`In repairing a defective column, a spare column is pro-
`vided for each of memory blocks, and spare columns are
`similarly not efficiently used. Although the shared I/O
`scheme has been considered for
`internal data line
`
`the way to repair a defective column in a
`arrangement,
`memory array having a local/global hierarchical data line
`arrangement used in a recent block-divided arrangement has
`never been considered.
`
`Meanwhile, in a conventional CMOS (Complimentary
`MOS) type semiconductor device, the size of components
`(MOS transistor: insulated gate type field effect transistor) is
`reduced to increase the integration density. In order to secure
`the reliability of the components thus miniaturized and to
`reduce the current consumed by the entire device, the power
`supply voltage is reduced. In order to allow the components
`to operate at a high speed, the threshold voltage of the MOS
`transistor must be lowered depending upon the power supply
`voltage. This is because if the ratio of the threshold voltage
`to the power supply voltage is large, the transition timing of
`the MOS transistor to the on state is delayed. If, however, the
`absolute value of the threshold voltage is lowered, sub-
`threshold leakage current to flow through the source-drain
`region when the MOS transistor is turned off increases. This
`is for the following reason. The threshold voltage is defined
`as the gate-source voltage to allow a prescribed drain current
`to flow. In an n-channel MOS transistor, if the threshold
`voltage is lowered, the drain current-gate voltage character-
`istic curve shifts toward the negative direction. The sub-
`threshold current is represented by the current value when
`gate voltage Vgs in the characteristic curve is 0V, and
`therefore the sub-threshold current increases as the threshold
`
`voltage is lowered.
`the ambient
`When the semiconductor device operates,
`temperature increases, and the absolute value of the thresh-
`old voltage of the MOS transistor is lowered, resulting in
`more serious sub-threshold current leakage. When this sub-
`threshold leakage current increases, the DC current of the
`entire large scale integrated circuit increases, and particu-
`larly in a dynamic type semiconductor memory device, the
`stand-by current (current consumed in a stand-by state)
`increases.
`
`In order to reduce the sub-threshold leakage current, a
`multi-threshold-voltage CMOS arrangement is employed.
`FIG. 55 is a diagram showing a conventional multi-
`threshold-voltage CMOS arrangement by way of illustra-
`tion. In FIG. 55, there are provided a main power supply line
`902 transmitting a power supply voltage Vcc, a sub-power
`supply line 904 coupled to main power supply line 902
`through a p-channel MOS transistor 903, a main ground line
`906 transmitting a ground voltage Vss, and a sub-ground
`line 908 coupled to main ground line 906 through an
`n-channel MOS transistor 907. MOS transistor 903 conducts
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`when an activation signal /<|)ACT is at an L level, while MOS
`transistor 907 conducts when an activation signal <|)ACT is
`at an H level. MOS transistors 903 and 907 each have a
`
`55
`
`relatively high threshold voltage (high-Vth). The internal
`circuit operates, with a voltage from one of power supply
`lines 902 and 904 and a voltage from one of ground lines 906
`and 908 used as both operation power supply voltages. In
`FIG. 55, as the internal circuit, three-stage, cascaded inverter
`circuits 914a, 914b and 914C are shown. Inverter circuit
`914a includes a p-channel MOS transistor PQ having a
`source coupled to main power supply line 902, and an
`n-channel MOS transistor NQ having a source coupled to
`ground line 908. An input signal IN is provided in common
`to the gates of MOS transistors PO and NQ. Input signal IN
`is set to an L level in a stand-by cycle.
`
`60
`
`65
`
`34
`
`
`
`34
`
`

`
`US 6,233,181 B1
`
`5
`Inverter circuit 914b operates using voltages on sub-
`power supply line 904 and main ground line 906 as both
`operation power supply voltages. Inverter circuit 914C oper-
`ates with voltages on main power supply line 902 and
`sub-ground line 908 as both operation power supply volt-
`ages. MOS transistors PQ and NQ in each of these inverter
`circuits 914a to 914C have the absolute values of the
`
`threshold voltages set sufficiently small (low-Vth). The
`operation of the circuit shown in FIG. 55 will be now
`described with reference to FIG. 56.
`
`10
`
`In a stand-by cycle, input signal IN is set to an L level.
`Control signal <|)ACT is at an L level, and control signal
`/(|)ACT is at an H level (Vcc level). In inverter circuit 914b,
`MOS transistor PQ turns on, the source and drain thereof are
`at the same voltage level, and therefore no current is allowed
`to flow. Meanwhile, MOS transistor NQ is provided with
`input signal IN at the ground voltage level at its gate and is
`in an off state. However, the sub threshold leakage current
`allowed to flow through MOS transistor 907 in an off state
`is sufficiently reduced, because the threshold voltage of the
`transistor 907 is high. As a result, the sub-threshold current
`is reduced even if the threshold voltage of MOS transistor
`NQ is small. The sub-threshold current allowed to flow
`through MOS transistor 907 causes the voltage level on
`sub-ground line 908 to be higher than the ground voltage
`level, so that the gate-source region of MOS transistor NQ
`in inverter circuit 914a is set to a reverse bias state, and its
`sub-threshold current is further reduced.
`
`In inverter circuit 914b, the input signal is at an H level,
`and MOS transistor NQ is turned on, the source and drain
`thereof are at the same voltage level and therefore no sub
`threshold leakage current
`is generated. Meanwhile,
`p-channel MOS transistor PO is provided with a signal at
`power supply voltage Vcc level at its gate to allow sub-
`threshold leakage current
`to flow. However, since MOS
`transistor 903 is in an off state and MOS transistor 903 is a
`
`is
`the sub-threshold leakage current
`high-Vth transistor,
`sufficiently restrained. Thus, the sub-threshold leakage cur-
`rent in inverter circuit 914b is restrained. The sub-threshold
`
`leakage current of MOS transistor 903 causes the voltage
`level of sub-power supply line 904 to be lower than power
`supply voltage Vcc, and the gate-source region of MOS
`transistor PO is reversedly biased in inverter circuit 914b,
`the sub-threshold leakage current of which is further
`restrained. Similarly to inverter circuit 914a,
`the sub-
`threshold leakage current is restrained in inverter circuit
`914c.
`
`When an active cycle is started, control signal <|)ACT
`attains an H level, control signal /<|)ACT attains an L level,
`MOS transistors 903 and 907 are turned on, sub-power
`supply line 904 is coupled to main power supply line 902,
`and sub-ground line 908 is coupled to main ground line 906.
`Thus, these inverter circuits 914a to 914C are supplied with
`a current from a corresponding power supply line/ground
`line, their low-Vth transistors operate at a high speed, and
`their output signals are changed according to change in input
`signal IN.
`In the power supply circuit arrangement as shown in FIG.
`55, since the logical level of an input signal in a stand-by
`cycle is previously known, a connection path to a power
`source line is determined accordingly. If the logical state of
`input signal IN in a stand-by cycle is not predetermined, the
`logic gate is coupled to sub-power supply line 904 and
`sub-ground line 908.
`As disclosed in Japanese Patent Laying-Open No.
`6-232348, in a DRAM (Dynamic Random Access Memory),
`circuits having the same circuit configuration such as decode
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`circuits and word line drive circuits are provided. As the
`storage capacity increases,
`the number of such circuits
`significantly increases. In repeating circuitry having repeat-
`edly provided decode circuits and word line drive circuits, a
`prescribed number of particular circuits (addressed circuits)
`are selectively driven among the circuits having the same
`configuration in response to an address signal. If these
`circuits are formed by low-Vth transistors, the power supply
`circuit arrangement as shown in FIG. 55 (hierarchical power
`supply arrangement: sub-threshold leakage current reducing
`circuit) may be employed. In this case, as shown in FIG. 53,
`activation/inactivation of a power supply to a decoder or a
`word line driver must be controlled for each of the blocks
`
`(because a word line is selected on a block basis.) Control
`signals <|)ACT and /<|)ACT are activated when an active cycle
`is started. As a result, the number of circuits connected to
`sub-power supply line 904 or sub-ground line 908 increases,
`and as the parasitic capacitance increases, it takes longer
`time until sub-power supply line 904 and sub-ground line
`908 are driven to prescribed voltage (Vcc and ground
`voltage Vss) levels and therefore the operation starting
`timings of the internal circuits should be delayed until these
`voltages becomes stable, which impedes high-speed access-
`ing operations.
`As previously described, when a defective row/column is
`repaired using a spare decoder, a row/column to be selected
`is determined after determining if a spare is to be used/not
`used. In this case, as shown in FIG. 53,
`if redundancy
`replacement is performed within the same block, a corre-
`sponding power supply circuit (a circuit transmitting any of
`the power supply voltage and ground voltage) can be
`selected in response to an address signal to control the
`connection. If, however, a spare row/column is used for
`repairing a defective cell in another memory block in the
`flexible redundancy arrangement, a memory bl