UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC,
`Patent Owner.
`____________________
`
`Case IPR2016-01561
`U.S. Patent No. 6,233,181
`____________________
`
`
`
`DECLARATION OF DR. PINAKI MAZUMDER IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW
`
`Apple – Ex. 1001
`Apple Inc., Petitioner
`1
`
`

`
`TABLE OF CONTENTS
`
`I.
`INTRODUCTION .......................................................................................... 5
`II. BACKGROUND AND QUALIFICATIONS ...................................................... 5
`III. ASSIGNMENT AND MATERIALS REVIEWED ............................................. 13
`IV. UNDERSTANDING OF THE LAW ............................................................... 14
`A. Anticipation .............................................................................. 14
`B.
`Obviousness ............................................................................. 14
`C.
`Claim Construction .................................................................. 16
`V. LEVEL OF ORDINARY SKILL IN THE ART ................................................. 17
`VI. TECHNOLOGY BACKGROUND .................................................................. 19
`A. DRAM Memory Cell ............................................................... 19
`B.
`Basics of DRAM Architecture ................................................. 20
`C.
`An Architectural Snapshot of a Multi-Bank
`DRAM Chip ............................................................................. 21
`D. DRAM Chip Size Growth and Yield ....................................... 29
`E.
`Using Spare Memory Cells to Replace Defective
`Cells .......................................................................................... 31
`Redundancy Techniques for Word Lines................................. 35
`Redundancy Technique for Bit Lines ...................................... 39
`Redundancy Techniques in Commercial DRAM
`Devices ..................................................................................... 40
`VII. DESCRIPTION OF PRIOR ART .................................................................... 43
`A. Disclosure of Sukegawa ........................................................... 43
`B.
`Disclosure of Fujishima ........................................................... 46
`C.
`Disclosure of Walck ................................................................. 51
`VIII. THE ’181 PATENT ................................................................................ 53
`IX. THE CHALLENGED CLAIMS ..................................................................... 59
`X. PRIOR PROSECUTION ............................................................................... 61
`A. Original Prosecution ................................................................. 61
`Inter Partes Review ................................................................. 62
`B.
`
`F.
`G.
`H.
`
`
`
`2
`
`

`
`XI. PATENTABILITY ANALYSIS ....................................................................... 65
`A.
`Claim 3 is Obvious under § 103(a) over Sukegawa
`in view of Fujishima ................................................................. 65
`1.
`Sukegawa and Fujishima disclose and
`render obvious every limitation of
`dependent Claim 3 ......................................................... 65
`2. Motivation to combine the teachings of
`Sukegawa and Fujishima ............................................... 83
`Claim 5 is Obvious under § 103(a) over Sukegawa
`in view of Fujishima and Walck .............................................. 87
`1.
`Sukegawa, Fujishima, and Walck disclose
`and render obvious every limitation of
`dependent Claim 5 ......................................................... 87
`A person of ordinary skill in the art would
`have been motivated to combine the
`teachings of Sukegawa, Fujishima, and
`Walck, thereby rendering Claim 5 obvious ................... 92
`Claim Chart Showing Obviousness of Claims 3
`and 5 ......................................................................................... 95
`
`2.
`
`B.
`
`C.
`
`
`
`
`
`3
`
`

`
`Exhibit #
`
`EXHIBITS
`
`Exhibit Description
`
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`Declaration of Dr. Pinaki Mazumder
`
`Curriculum Vitae of Dr. Pinaki Mazumder
`
`U.S. Patent No. 6,233,181
`
`File History for U.S. Patent No. 6,233,181
`
`U.S. Patent No. 5,487,040 to Sukegawa
`
`U.S. Patent No. 5,267,214 to Fujishima
`
`U.S. Patent No. 4,967,397 to Walck
`
`U.S. Patent No. 5,956,285 to Watanabe
`
`Masashi Horiguchi et al., A Flexible Redundancy Technique for High-
`Density DRAM’s, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.
`26, NO. 1, Jan. 1991, at 12-17
`
`Kazutami Arimoto et al., A 60-ns 3.3-V-Only 16 Mbit DRAM with
`Multipurpose Register, IEEE JOURNAL OF SOLID-STATE CIRCUITS,
`VOL. 24, NO. 5, Oct. 1989, at 1184-90
`
`U.S. Patent No. 5,687,123 to Hidaka
`
`U.S. Patent No. 5,726,946 to Yamagata
`
`U.S. Patent No. 6,003,148 to Yamauchi
`
`U.S. Patent No. 6,075,743 to Barth
`
`Inter Partes Review No. IPR2016-00096, Decision Granting
`Institution filed April 21, 2016
`
`Inter Partes Review No. IPR2016-00096, Judgment Granting
`Request for Adverse Judgment filed August 3, 2016
`
`
`
`4
`
`

`
`I, Pinaki Mazumder, hereby declare:
`
`I.
`
`INTRODUCTION
`
`1.
`
`I have been retained by Apple Inc. (hereinafter “Apple”) to serve as a
`
`technical expert and provide expert opinions relating to U.S. Patent No.
`
`6,233,181 (hereinafter “’181 Patent”) (Ex. 1003), including opinions on the
`
`validity of the ’181 Patent in support of Apple’s petition for inter partes review.
`
`2.
`
`I am being compensated for my time at a rate of $350 per hour. My
`
`compensation is in no way dependent on the substance of the opinions I have
`
`offered below, or upon the outcome of Apple’s petition for inter partes review
`
`(or the outcome of the inter partes review, if trial is instituted).
`
`II. BACKGROUND AND QUALIFICATIONS
`
`3.
`
`I received my PhD in Electrical and Computer Engineering from the
`
`University of Illinois at Urbana-Champaign in 1988. Prior to that, I received my
`
`MS degree in Computer Science from University of Alberta in Canada, BS
`
`degree in Electrical Engineering from Indian Institute of Science at Bangalore,
`
`and BSc Physics Honors degree from Guwahati University in India.
`
`4. Currently, I am a Professor of Electrical Engineering and Computer Science
`
`at the University of Michigan where I have been teaching for the past 25 years. I
`
`spent 3 years at National Science Foundation serving as the lead Program
`
`Director of Emerging Models and Technologies Program in the CISE Directorate
`
`
`
`5
`
`

`
`as well as a Program Director in the Engineering Directorate. I had worked for 6
`
`years in industrial R&D laboratories that included AT&T Bell Laboratories in
`
`USA and Bharat Electronics Ltd. in India. I spent my sabbatical at Stanford
`
`University, University of California at Berkeley, and NTT Center Research
`
`Laboratory in Japan.
`
`5.
`
`In 1985, when I joined the University of Illinois for my PhD, I was recruited
`
`to work in a Semiconductor Research Corporation (SRC) research project to
`
`develop new testing methodologies for semiconductor memory chips. At that
`
`time, commercial test equipment used simple functional testing methods to detect
`
`rudimentary manufacturing defects, and the university research was primarily
`
`confined in refinement of functional test algorithms. Since I had worked six
`
`years in industrial R&D laboratories after my BS degree, I had recognized the
`
`need for new way of accelerated memory chip testing with the aggressive
`
`increase in density of integration.
`
`6.
`
`I studied the DRAM architecture while doing my PhD and proposed the
`
`concept of internal testing by introducing a new method called “in-line” testable
`
`design, where a single word-line address was asserted to access up to 50% of
`
`memory cells on a word line to write the same data on those cells. To read the
`
`contents of those memory cells in one memory cycle, an internal “parallel 0/1
`
`detector” was invented to verify whether all the cells that were written in one
`
`
`
`6
`
`

`
`memory write cycle, preserves the same data bit after several other READ and
`
`WRITE operations performed on other memory cells. While the row decoder
`
`was retained unaltered to access one word line at a time, the “column address
`
`decoder” was modified in order to allow the access to 100’s of bit lines in the test
`
`mode. This design for testability technique was utilized to accelerate the test
`
`procedures and reduce memory testing cost significantly. I combined the
`
`concepts of VLSI process technology, memory layout, circuit design, and
`
`mathematical techniques like graph theory and Markov chain modeling to
`
`develop comprehensive accelerated test procedures for the testable memory.
`
`This is explained in the synopsis of my doctoral thesis, which is included in my
`
`Curriculum Vitae (“CV”) attached as Exhibit 1002.
`
`7. After I joined the University of Michigan in 1987, I continued working on
`
`testing and fault-tolerance of high-density semiconductor random-access
`
`memories that resulted in numerous publications of archival journal papers and
`
`two books on testing and reliability of high-density semiconductor memories
`
`(“Testing and Testable Design of Random-Access Memories,” Kluwer Academic
`
`Publishers, 1996, 428 pages, and “Fault Tolerance and Reliability Aspects of
`
`Random-Access Memories,” Prentice Hall, 2002, 440 pages). These two books
`
`are widely used by VLSI practicing engineers as well as academic researchers
`
`even several years after their publication. Amongst several new research ideas
`
`
`
`7
`
`

`
`my students and I proposed during the period from 1987 to 1997 include efficient
`
`memory test algorithms, built-in self-testing of memories, on-chip error
`
`correction of semiconductor memory, self-healing techniques for memories, self-
`
`repairable RAM compiler that generates memory layout automatically, and ultra-
`
`low power CMOS memories for wearable products (see Publications: 10-21, 23-
`
`26, 46, 47, 62, 77, 94, 96-100, 126, 128, 130, 131, 133, 135-137, 142, 146, 155,
`
`166, 179-182, 185, 219, 226, 237, 279, 301-303 in my CV).
`
`8. Besides working on conventional CMOS static random-access memory
`
`(SRAM) and dynamic random-access memory (DRAM) technologies, my
`
`research group has also performed extensive research in emerging memory
`
`technologies such as nonvolatile resistive random-access memory (Publications:
`
`82 and 279 in my CV), magnetoresistive random-access memory (Publications:
`
`94, 96-100 in my CV), and resonant tunneling memory (Publications: 36, 80,
`
`208, 237 and 239 in my CV). My research group had conducted extensive
`
`research in quantum tunneling technologies and we had designed new type of
`
`storage devices to improve speed and reduce power consumption.
`
`9.
`
`I have published over 280 technical papers and 4 books on various aspects of
`
`VLSI technology and systems. My research interest includes CMOS VLSI
`
`design, semiconductor memory systems, CAD tools and circuit designs for
`
`
`
`8
`
`

`
`emerging technologies including quantum MOS, spintronics, plasmonics, and
`
`resonant tunneling devices.
`
`10. I was a recipient of Digital’s Incentives for Excellence Award, BF Goodrich
`
`National Collegiate Invention Award, and DARPA Research Excellence Award.
`
`11. I am a 2007 Fellow of American Association for the Advancement in
`
`Science (AAAS) for my “distinguished contributions to the field of very large
`
`scale integrated (VLSI) systems.” The honor of being elected a Fellow of AAAS
`
`is given to those whose “efforts on behalf of the advancement of science or its
`
`applications are scientifically or socially distinguished.”
`
`12. I am also a 1999 Fellow of IEEE for my “contributions to the field of VLSI
`
`Design.”
`
`13. Over the course of the past 29 years, I have secured 51 research contracts
`
`from National Science Foundation, Air Force Office of Scientific Research,
`
`Office of Naval Research, Army Research Office, Defense Advanced Research
`
`Projects Agency, State of Michigan, and several private sources. The aggregated
`
`amount of these grants exceeds $11 Million for my individual share and about
`
`$40 Million for co-investigators work on these grants.
`
`14. For the past 29 years, I have been teaching at the Department of Electrical
`
`Engineering and Computer Science of the University of Michigan, Ann Arbor,
`
`Michigan, where I taught the following courses more frequently: 1) VLSI System
`
`
`
`9
`
`

`
`Design, 2) Optimization and Synthesis of VLSI Layout, 3) Introduction to Digital
`
`Logic Design, and 4) Digital Integrated Circuit Design. Besides these courses, I
`
`introduced three advanced level graduate courses: 5) Circuits and Architectures
`
`for Nanodevices, 6) Ultra-Low-Power Subthreshold CMOS Circuits, and 7)
`
`Terahertz Technology and Applications.
`
`15. The IEEE Electron Devices Society recognized me as an IEEE
`
`Distinguished Lecturer. I presented over 70 invited talks at universities and
`
`companies around the world.
`
`16. Below is an exemplary list of inventions of mine that have either been
`
`awarded as US patents or are currently under review by the USPTO (a full list is
`
`in my CV):
`
` US Patent on Adaptive Reading and Writing of a Resistive Memory, US
`
`Patent No. 9,111,613, awarded on Aug. 18, 2015, (Inventors: P. Mazumder
`
`and E. Idong; Patent Assigned to Regents of University of Michigan).
`
` US Patent on High-Speed, Compact, Edge-Triggered Flip-Flop Circuit
`
`Topologies Using NDR Diodes and FET’s, US Patent No. 6,323,709,
`
`awarded on Nov. 21, 2001, (Inventors: S. Kulkarni and P. Mazumder; Patent
`
`Assigned to Regents of University of Michigan).
`
` US and International Patents on Method and Apparatus to Improve Noise
`
`Tolerance of Dynamic Circuits, US Patent No. 7,088,143, awarded on Aug.
`
`
`
`10
`
`

`
`8, 2006, (Inventors: L. Ding and P. Mazumder; Patent Assigned to Regents
`
`of University of Michigan).
`
` US Patent Provisional Application filed on Memristor Crossbar Memory for
`
`Hybrid Ultra Low Power Hearing Aid Speech Processor, (Inventors: J. Shah,
`
`P. Mazumder and M. Barangi).
`
` US Patent on Static Random Access Memory Cell having Improved Write
`
`Margin for use in Ultra-Low Power Application, International application
`
`number: PG/US 13/78262, (Inventors: P. Mazumder, Z. Nan and J. Kim).
`
` Invention disclosure for Yield Improvement of VLSI Chips by Using
`
`Electronic Neural Networks for Built-in Self-Repair, Feb. 15, 1990,
`
`(Inventor: P. Mazumder).
`
` Invention disclosure for A Zero-Delay Overhead Circuit Technique for
`
`Built-in Self-Repair of Random-Access Memories, Oct. 17, 1996,
`
`(Inventors: K. Chakraborty and P. Mazumder).
`
`17. A few papers on relevant subject areas authored or co-authored by me are
`
`listed below. Notably, the first three publications are pertaining to redundancy
`
`and repair of DRAM chips, which is the main goal of the ’181 Patent. A
`
`complete list of my publications are in my CV.
`
` A New Built-In Self-Repair Approach to VLSI Memory Yield Enhancement
`
`by Using Neural-Type Circuits, IEEE Transactions on Computer Aided
`
`
`
`11
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`

`
`Design of Integrated Circuits and Systems, Vol. 12, No. 1, January 1993, pp.
`
`124-136.1
`
` Analysis and Design of Hopfield-type Network for Built-in Self-Repair of
`
`Memories, IEEE Transactions on Computers, Vol. 45, No. 1, Jan. 1996, pp.
`
`109-115.2
`
` BISRAMGEN: A Built-In Self-Repairable SRAM and DRAM Compiler,
`
`IEEE Transactions on VLSI Systems, Vol. 9, No. 2, Apr. 2001, pp. 352-
`
`364.3
`
` Parallel Testing of Parametric Faults in a Three-Dimensional Dynamic
`
`Random-Access Memory, IEEE Journal of Solid-State Circuits, Vol. 23, No.
`
`4, August 1988, pp. 933-942.
`
` Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access
`
`Memory with On-Chip Error-Correcting Circuit, IEEE Transactions on
`
`Computers, Vol. 42, No. 12, December 1993, pp. 1453-1468.
`
`
`1
`In this paper, I have described an efficient redundancy technique that allows
`a DRAM chip with multiple scattered defective cells to be reconfigured in order to
`improve the yield to nearly 100% from below 30% if there is no redundancy
`incorporated in the DRAM chip.
`2
`In this paper, I have shown how the reconfiguration technique described in
`the above paper can be implemented very efficiently inside a DRAM chip using
`digital circuits so that the chip can self-heal in the presence of manufacturing
`defects as well as failures occurring during to the operation of the chip.
`3
`In this paper, I have shown how redundancy circuits can be automatically
`incorporated in a memory compiler by using the address remapping technique in
`the form of a table look-aside buffer (TLB). This is a soft repair technique.
`
`
`
`12
`
`

`
` Design and Analysis of Resonant-Tunneling-Diode (RTD) Based High
`
`Performance Memory System, IEICE Trans. Electronic, Vol. E82-C, No. 9,
`
`September 1999, pp. 1630-1637.
`
` Performance Modeling of Resonant Tunneling-Based Random-Access
`
`Memories, IEEE Transactions on Nanotechnology, Vol. 4, No. 4, July 2005,
`
`pp. 472-480.
`
`III. ASSIGNMENT AND MATERIALS REVIEWED
`
`18. I have been asked to provide opinions regarding the patentability of Claims
`
`3 and 5 of the ’181 Patent. Specifically, I have been asked to provide an opinion
`
`as to whether every limitation of Claims 3 and 5 is disclosed to one of ordinary
`
`skill in the art by, or in the alternative, whether Claims 3 and 5 would have been
`
`obvious in view of U.S. Patent No. 5,487,040 (“Sukegawa”) (Ex. 1005), U.S.
`
`Patent No. 5,267,214 (“Fujishima”) (Ex. 1006) and/or U.S. Patent No. 4,967,397
`
`(“Walck”) (Ex. 1007).
`
`19. The opinions expressed in this declaration are not exhaustive of my opinions
`
`on the patentability of Claims 3 and 5 of the ’181 Patent. Therefore, the fact that
`
`I do not address a particular point should not be understood to indicate any
`
`opinion on my part that any claim otherwise complies with the patentability
`
`requirements.
`
`
`
`13
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`

`
`20. In forming my opinions, I have reviewed the ’181 Patent, the prosecution
`
`history of the ’181 Patent (Ex. 1004), and the inter partes review history relating
`
`to the ’181 Patent (Ex. 1015-1017).
`
`21. I am familiar with the prior art and the knowledge of one of ordinary skill in
`
`the art at the relevant time. I specifically have analyzed Sukegawa, Fujishima
`
`and Walck, and have reviewed the various references cited in this declaration.
`
`IV. UNDERSTANDING OF THE LAW
`
`A. Anticipation
`
`22. I have been informed that under 35 U.S.C. § 102, for a claim to be invalid as
`
`“anticipated,” every limitation of the claim must be found in a single prior art
`
`reference, either expressly or inherently.
`
`B. Obviousness
`
`23. I also have been informed that under 35 U.S.C. § 103, where each and every
`
`element is not present in a single reference, a claim may still be invalid as
`
`“obvious” if the differences between the subject matter sought to be patented and
`
`the prior art are such that the subject matter as a whole would have been obvious
`
`at the time the invention was made to a person having ordinary skill in the art to
`
`which said subject matter pertains. I understand that the following factors must
`
`be evaluated to determine whether the claimed subject matter is obvious: (1) the
`
`scope and content of the prior art; (2) the difference or differences, if any,
`
`
`
`14
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`

`
`between each claim of the patent and the prior art; and (3) the level of ordinary
`
`skill in the art at the time the patent was filed.
`
`24. I understand that obviousness may be shown by considering more than one
`
`item of prior art and by considering the knowledge of a person having ordinary
`
`skill in the art and that obviousness may be based on various rationales,
`
`including:
`
` Combining prior art elements according to known methods to yield
`
`predictable results;
`
` Simple substitution of one known element for another to obtain predictable
`
`results;
`
` Use of known techniques to improve similar devices (methods, or products)
`
`in the same way;
`
` Applying a known technique to a known device (method, or product) ready
`
`for improvement to yield predictable results;
`
` “Obvious to try” – choosing from a finite number of identified, predictable
`
`solutions, with a reasonable expectation of success;
`
` Known work in one field of endeavor may prompt variations of it for use in
`
`either the same field or a different one based on design incentives or other
`
`market forces if the variations are predictable to one of ordinary skill in the
`
`art; and
`
`
`
`15
`
`

`
` Some teaching, suggestion, or motivation in the prior art that would have led
`
`one of ordinary skill to modify the prior art reference or to combine prior art
`
`reference teachings to arrive at the claimed invention.
`
`25. I also have been informed and I understand that when present, so-called
`
`“objective indicia” of non-obviousness, also known as “secondary
`
`considerations,” like the following are also to be considered when assessing
`
`obviousness: (1) commercial success; (2) long-felt but unresolved needs; (3)
`
`copying of the invention by others in the field; (4) initial expressions of disbelief
`
`by experts in the field; (5) failure of others to solve the problem that the inventor
`
`solved; and (6) unexpected results. I also understand that there must be a nexus
`
`between the claimed subject matter and the evidence of objective indicia of non-
`
`obviousness, and that the evidence of objective indicia of non-obviousness must
`
`be commensurate in scope with the claimed subject matter.
`
`C. Claim Construction
`
`26. I have been informed that the claims of a patent subject to inter partes
`
`review are given their “broadest reasonable construction in light of the
`
`specification.” I also have been informed that the words of the patent claims are
`
`to be given their plain meaning in view of the specification as interpreted by one
`
`of ordinary skill in the art.
`
`
`
`16
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`

`
`27. Consistent with these guidelines, I believe that the ’181 patent terms should
`
`be construed to have their plain and ordinary meaning in view of the
`
`specification.
`
`V. LEVEL OF ORDINARY SKILL IN THE ART
`
`28. A person of ordinary skill in the art of the ’181 patent at the time of
`
`invention in 1997 would have had a Bachelor of Science and Master’s degree in
`
`electrical engineering or computer engineering (or an equivalent subject) and
`
`three to four years of post-graduate experience working with dynamic random
`
`access memory systems, or a PhD in electrical engineering or computer
`
`engineering (or an equivalent subject) and at least 1-2 years of post-graduate
`
`experience working with such dynamic random access memory systems, or an
`
`equivalent amount of work experience.4
`
`29. The subject matter of the ’181 patent relates to DRAM architecture, and the
`
`ordinarily skilled artisan would have an understanding of DRAM yield modeling,
`
`
`4
`I understand that in the previous IPR of the ’181 patent, i.e., IPR2016-
`00096, Petitioner MTI proposed that a person having ordinary skill in the art would
`be a person with a Bachelor of Science in electrical engineering, computer
`engineering, computer science or a closely related field, along with at least 2-3
`years of experience in the design of memory devices. In my experience, a person
`of ordinary skill would have a Bachelor of Science and a Master’s in electrical
`engineering (or an equivalent subject) or a PhD in electrical engineering (or an
`equivalent subject). Nonetheless, even if the person of ordinary skill had a
`Bachelor of Science in electrical engineering (or an equivalent subject) and at least
`2-3 years of experience in the design of memory devices, my conclusion regarding
`the patentability of Claims 3 and 5 of the ’181 patent would not change.
`
`
`
`17
`
`

`
`reconfiguration techniques deployed in DRAM for improving chip yield,
`
`tradeoffs between reconfiguration overhead and yield improvement, and DRAM
`
`array architecture. Based on my experience and education, I consider myself (as
`
`of no later than 1988, and since) to be a person of at least ordinary skill in the art
`
`with respect to the field of technology implicated by the ’181 patent. To be clear,
`
`my conclusions of obviousness relate to whether Claims 3 and 5 as a whole
`
`would have been obvious at the time of invention to a person of ordinary skill in
`
`the art.
`
`30. In 1997, a person of ordinary skill in the art, as defined above, would have
`
`been aware of and able to review and implement the teachings of the prior art like
`
`(i) Sukegawa (U.S. Patent No. 5,487,040) (Ex. 1005), with a priority date of July
`
`10, 1992 and an issue date of January 23, 1996, (ii) Fujishima (U.S. Patent No.
`
`5,267,214) (Ex. 1006), with a priority date of February 16, 1990 and an issue date
`
`of November 30, 1993 and (iii) Walck (U.S. Patent No. 4,967,397) (Ex. 1007),
`
`with a priority date of May 15, 1989 and an issue date of October 30, 1990,
`
`which render obvious Claims 3 and 5 of the ’181 patent.
`
`
`
`18
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`

`
`VI. TECHNOLOGY BACKGROUND
`
`A. DRAM Memory Cell
`
`31. A Dynamic Random Access Memory (“DRAM”) cell is a compact memory
`
`cell comprising one transistor and one capacitor (“1T1C”) (see diagram of
`
`DRAM Basic Cell in Fig. 1 below).
`
`DRAM Basic Cell
`WL
`
`Hold State (WL=0)
`WL=0
`
`Data
`
`Q
`
`Data
`
`Write (Data is an input)
`WL=1 Q
`
`Data
`
`Q=1
`
`++++++
`
`−−−−−−
`
`WL=0
`
`Q=0
`
`Data
`
`Read (Data is an output)
`WL=1 Q
`
`Data
`
`
`Fig. 1. DRAM cell showing the storage of Logic 1 and Logic 0.
`
`32. The DRAM cell is said to contain a logic value of “1” when the capacitor
`
`contains a charge (Q=1), and “0” when the capacitor contains no charge (Q=0).
`
`As denoted in Fig. 1, a logic value can be written to the cell by enabling the gate
`
`WL (i.e., WL=1) of the access transistor. Conversely, while WL is held low
`
`(WL=0), the cell holds its charge. A READ operation is performed by asserting
`
`WL (i.e., WL=1) to enable data to be read out through a sense amplifier. The
`
`WL terminal is referred to as a “word line” or “row”, while the data terminal is
`
`connected to a column, and is referred to as a “bit line.”
`
`
`
`19
`
`

`
`B.
`
`Basics of DRAM Architecture
`
`33. Fig. 2 below shows an exemplary 4x4 memory cell array along with its
`
`peripheral components. The row (word line) addresses 0-3 and column (bit line)
`
`addresses 0-3 are marked for each distinct row and column.
`
`
`Fig. 2. Basic DRAM Architecture with 4x4 Memory Array.
`
`34. To read the value stored in an arbitrary cell, for example the cell located at
`
`the intersection of row 2 and column 3, a Row Address Strobe (“/RAS”) signal is
`
`first asserted while the row address bits A0 and A1 are provided to an Address
`
`Input Buffer, which then transfers them to a Row Decoder. If A0 = 0 and A1 = 1,
`
`for instance, the Row Decoder will activate Row Address Line 2. When this row
`
`(word line) is activated by the Row Decoder, all the access transistors connected
`
`to it will turn ON, while all other access transistors on other word lines will
`
`remain turned OFF. Therefore, all the memory cells on the word line will
`
`
`
`20
`
`

`
`propagate their charges via their respective Column Address Lines (or Column
`
`Select Lines) (bit lines).
`
`35. The associated Sense Amplifiers will be activated simultaneously to
`
`determine the logic state of DRAM cells connected to Row Address Line 2.
`
`Once the sense amplifiers are activated, a Column Address Strobe (“/CAS”)
`
`signal is asserted and the Write Enable (“/WE”) is asserted to perform a READ
`
`operation. At the same time, the column address is provided on address bits, A0
`
`and A1 to the Address Input Buffer, which then transfers them to the Column
`
`Decoder. If A0 = 1 and A1 = 1, for instance, the Column Decoder will activate
`
`Column Address Line 3. The logic state of the Sense Amplifier connected to this
`
`Column Address Line will then be transferred to a data output buffer completing
`
`the read operation.
`
`C. An Architectural Snapshot of a Multi-Bank DRAM Chip
`
`36. While the operation of a single memory cell is described above with
`
`reference to Fig. 1, a modern Giga-bit DRAM chip with multiple memory banks
`
`and memory array blocks is capable of higher-speed READ and WRITE
`
`operations by incorporating fast pipeline interfaces, low power consumption,
`
`good noise immunity, and redundancy circuits that help improve chip yield.
`
`
`
`21
`
`

`
`37. A snapshot of an exemplary DRAM chip shows the architecture of a multi-
`
`bank memory device having shared sense amplifier bands. In Fig. 35 below from
`
`a patent claiming priority to 1996, schematics are shown of the overall
`
`architecture of a multi-bank DRAM chip that comprises N+1 Memory Blocks
`
`(MB#0-MB#N), each having a plurality of memory cells arranged in a matrix of
`
`rows and columns, and N+2 Sense Amplifier Bands (SA#0-SA#N+1), of which
`
`SA#0 and SA#N+1 are located at the extreme edge of the memory blocks, MB#0
`
`and MB#N, while N other Sense Amplifier Bands are shared by two adjacent
`
`memory blocks for READ and WRITE operations. Ex. 1008, 6:64-7:12. There
`
`are N+1 Array Driving Circuits (DR#0-DR#N) that comprises Row Address
`
`Decoders for each Memory Block (MB), while the Column Decoder is common
`
`to all memory blocks and a single Column Select Line runs orthogonally
`
`(upward) from Column Decoder through all memory blocks. Id. at 7:13-25; and
`
`Fig. 1.
`
`
`5
`U.S. Patent No. 5,956,285, “Synchronous Semiconductor Memory Device
`with Multi-Bank Configuration,” priority date of April 22, 1996. Ex. 1008, Fig. 1.
`
`
`
`22
`
`

`
`
`Fig. 3. An exemplary design of a large DRAM chip having shared sense amplifier
`band.
`
`38. The sense amplifier bands (SA#1-SA#N) are shared by adjacent pairs of
`
`memory blocks. Id. at 1008, 7:6-8. During a READ or WRITE operation, a
`
`selected memory block is connected to its corresponding adjacent sense amplifier
`
`bands, which are isolated from any non-selected memory blocks. Id. at 1008,
`
`7:8-12.
`
`39. To perform a READ or WRITE operation, a set of Command (CM) signals
`
`comprising /RAS, /CAS, /WE, etc. are provided to the Command Latch which is
`
`then decoded by Command Decoder to set up appropriate timing signals for the
`
`intended memory operation. Along with the CM signals, row address, AD is
`
`provided to Row Address Latch in order to select a word-line of the selected
`
`
`
`23
`
`

`
`memory block (MB). AD is also provided to the Bank Address Latch and Bank
`
`Decoder. Modern Giga bit and multi-Mega bit DRAM chips are organized into
`
`multiple (from 2 to 8) Memory Banks. Generally, for normal READ/WRITE
`
`operations, depending upon the location of the memory to be accessed, a
`
`particular bank will be activated for that particular READ/WRITE operation, but
`
`the memory banks can be effectively addressed6 to overlap the activities within
`
`
`6
`In the mid-1990’s, DRAM memories supported early issuing of the READ
`command by asserting /CAS (in JEDEC DDR2, this mode of operation was later
`named as Posted CAS) that allowed interleaving of memory READ operations
`between different banks to improve the overall data bus and command bus
`throughput. Normally, when an ACT command is issued by asserting /RAS, the
`DRAM has to wait until all sense amplifiers assume the logic state of different
`memory cells located on the selected word-line. This time period is generally
`known as RAS-to-CAS delay (tRCD) and is typically comparable to the CAS latency
`of a DRAM chip. Only after tRCD time interval, a /CAS is asserted to perform a
`READ operation. This means that during nearly 2tRCD time interval, a single data
`can be read out in regular mode of operation from a memory bank. During this
`time interval, other memory banks, which have separate internal latches and
`counters also remain inactive since the main processor (CPU) issues command for
`one READ (WRITE) operation at a time in normal mode of DRAM operation..
`
`However, CPU can issue more ACT (by asserting /RAS) commands by providing
`Row Addresses to other memory banks if the current memory bank can be released
`by issuing an early READ command (i.e., by asserting /CAS) along with the
`Column Address of the memory cell. In this case, the READ command and
`address of the