Apple – Ex. 1020
`Apple Inc., Petitioner
`1
`
`EuropSlsches Patentamt
`European Patent Office
`Office europ6en des brevets
`W Publication number:
`0499 131 A1
`EUROPEAN PATENT APPLICATION
`© Application number: 92101917.0
`@ Date of filing: 05. 02.92
`int. Cis: G11C 29/00, G06F 11/20
`Priority: 12. 02. 91 US 654431
`@ Date of publication of application:
`19. 08. 92 Bulletin 92/34
`@ Applicant: TEXAS INSTRUMENTS
`INCORPORATED
`13500 North Central Expressway
`Dallas Texas 75265(US)
`® Designated Contracting States:
`DE FR GB IT Nt
`@ Inventor: Sukegawa, Shunlchl
`6909 Ouster Road, Apt No. 2905
`Dallas, Texas 75023(US)
`High efficiency row redundancy for dynamic ram.
`Representative: Schwepflnger, Karl-Helnz,
`Dipl. -lng. et al
`Prinz, Lelser, Bun he & Partner Manzingerweg
`7
`W-8000 MUnchen 60(DE)
`<
`m
`G>
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`0-
`iu
`® A row redundancy scheme is disclosed which
`allows the enablement of a redundant array (4-
`RED.WARDS) of memory before the disablement of
`a defective and usual array (0-31) of memory. Each
`redundant array is capable of serving numberous
`usual arrays in the function of replacing rows of
`usual memory arrays. Consequently, considerable
`space saving and memory operating speed are re-
`alized by the row redundancy scheme.
`I
`cu
`in
`S/A
`i!
`i§
`.s
`r
`.
`4-REDUNDANT WORD LINES.
`(REDUNDANT ARRAY)
`S/A
`S/A
`S/A
`I
`s
`I
`I!
`QC
`S/A
`I
`-f
`256 WORDS LINES-/
`256 WORDS LINES* 4-RED. WORDS LINES
`FIG. 5b
`h-
`Rank Xerox <UK) Business Senrices
`o 7
`7/5? ~l
`

`

`Apple – Ex. 1020
`Apple Inc., Petitioner
`2
`
`EP 0 499 131 A1
`Held of the Invention
`The invention is in the field of integrated cir-
`cults and more specifically, in the field of inte-
`grated circuit memory devices.
`Background of the Invention
`Electronic devices and systems such as print-
`ers,
`copiers,
`electronic
`storage
`devices
`(memories), high definition television, enhanced
`definition television and computational devices (e. g.
`calculators and computers including personal com-
`puters, minicomputers, personal work stations and
`microcomputers) requiring electronic storage de-
`vices, often provide data storage on a semiconduc-
`tor integrated circuit chip. Because these devices
`often require large amounts of storage space for
`many applications, these storage devices are em-
`bodied in a dynamic random access memory.
`As the demand has grown for increased mem-
`ory space, the density of dynamic random access
`memories, DRAMs, has correspondingly increased.
`However, with increased memory density, in-
`creased memory operating speed is also demand-
`ed. Consequently, the complexity of the DRAM has
`likewise increased with these demands.
`Defects in fabrication discovered in earlier gen-
`erations of DFlAMs resulted
`in disposal of the
`DRAM. This practice became too expensive and
`wasteful. Therefore, conventional memories often
`provide redundant structures (i. e. redundant word
`lines along with associated redundant memory
`cells) on the memory chip to act in place of the
`word line and its associated memory with which a
`defect is attributable. As a consequence of the
`redundancy, an integrated memory chip can be
`salvageable regardless of the defect.
`Goals of increased density and speed in the
`development of DRAMS has resulted in the addi-
`tional criterion of optimized use of chip real estate
`within Ihe constraints of the desired memory den-
`sity.
`Prior art DRAMS have been developed for
`memory densities up to 16 megabits. Memories,
`such as the 16 megabit memory are often or-
`ganized as a plurality of memory arrays with each
`array having a predetermined density. Such memo-
`ries place a predetermined number, i.e. 4, of re-
`dundant word lines and their associated memory
`cells within each memory array. Generally, there
`are as many redundant word lines (and associated
`redundant memory cells) as there are memory
`arrays. Along with the redundant word lines and
`cells, row decoders for decoding word lines and
`the rows of redundant memory are required. Con-
`ceivably, with an increasing memory density, this
`redundancy scheme can result in many unused
`and therefore wasted redundancy word lines and
`associated redundancy memory cells since the
`number and decoding capacity of the row redun-
`dancy decoders is much smaller than the number
`5
`of redundant word lines. An additional drawback of
`conventional redundancy schemes is that even
`ttiough a large number of redundant word lines
`exist on a memory chip, only defects associated
`with a word line or a memory cell up to the number
`»o of redundant word lines in an array can be cor-
`reeled in an array. For instance, if the redundancy
`scheme for the 16 megabit DRAM were incor-
`porated for use in a 64 megabit memory, perhaps
`it could be arranged su<Sh that there are 128 arrays
`is of approximately 512,000 (512k) rows of memory- If
`4 redundant word lines exist in each array, then
`approximately 512 total redundant word lines (and
`associated circuitry) would exist on the 64 megabit
`chip. Thus, even though there are 512 redundant
`ao word lines on the chip, only four defective word
`lines are replaceable in each array. The average
`number of defects in conventionally sized DRAMs
`is 10. However, the average number of defects in a
`64 megabit DRAM will probably be close to 50.
`25 Since the 16 megabit DRAM redundancy scheme
`requires the same number of redundant word lines
`as the number of memory arrays, the 16 megabit
`redundancy scheme incorporated into a 64 megabit
`memory would occupy a large amount of chip real
`30
`estate.
`A further drawback of conventional redundancy
`schemes such as a redundancy scheme for 16
`megabit DRAMs is that since the defect is replaced
`by a redundant word line (and associated circuitry)
`as
`in the same array in which the defect exists, the
`defective word line must be disabled before the
`redundant word line can be activated, otherwise a
`bit error may result. Consequently, this requirement
`slows the speed of the memory.
`40
`Until now a need has existed for a new and
`improved memory since conventional schemes are
`unacceptable, as explained above, for memory
`densities of 64 megabits and greater.
`45 OBJECTS OF THE INVENTION
`It is an object of the invention to provide a new
`and improved redundancy scheme for a memory.
`It is another object of the invention to provide
`50
`anew and improved row redundancy scheme for a
`memory.
`It is a further object of the invention to provide
`a row redundancy scheme for a memory which
`dose not requirs the disablement of a usual array
`5S
`before activation of an associated redundant array.
`These and other objects of the invention, to-
`gether with the features and advantages thereof,
`will become apparent from the following detailed
`

`

`Apple – Ex. 1020
`Apple Inc., Petitioner
`3
`
`EP 0 499 131 A1
`specification when read together with the accom-
`panying drawings in which applicable reference
`numerals, letters, and symbols have been carried
`forward.
`SUMMARY OF THE INVENTION
`The foregoing objects of the invention are ac-
`comptished by a row redundancy scheme which
`activates a redundant array prior to disabling an
`associated usual array.
`The scheme can be implemented in a memory
`architecture comprising a plurality of memory ar-
`rays in which a predetermined number of arrays
`each include a redundancy array. Each time a row
`of memory from a redundant array is chosen to
`replace a defective row of memory cells in a mem-
`ory array, the redundant array lies outside of the
`array in which the defective row exists.
`BRIEF DESCRIPTION OF THE DRAWINGS
`Figure 1a illustrates a plan view of the architec-
`ture of the hierarchical multi-data lines memory.
`Rgure 1b illustrates a block diagram illustrating
`the flow of data to the wide data path circuit.
`Figures 1c through 1e illustrate logic diagrams
`of possible logic accomplished in the wide data
`path.
`Rgure 2 illustrates a read/write data bus
`scheme which includes a schematic drawing of a
`wide data path circuit.
`Figure 3a illustrates a plan view of another
`embodiment of the memory architecture.
`Figure 3b illustrates a plan view of the pre-
`ferred embodiment of the memory architecture.
`Rgure 4 illustrates one 512,00 bit memory cell
`array and its associated circuitry.
`Figure 5a illustrates a plan view of one quad-
`rant of the invention's memory architecture.
`Figure 5b illustrates a more detailed plan view
`of the invention's memory architecfaire.
`Figure 6 illustrates a logic diagram relating to
`the activation or disablement of a redundant array.
`Figure 7 illustrates a schematic drawing of the
`invention's row redundancy decoder circuit.
`Figure 8a illustrates a schematic drawing of a
`usual memory array and its associated sense
`amps.
`Figure Sb illustrates a timing diagram for the
`operation of that illustrated in figure 8a.
`Figure 8c illustrates a schematic drawing of a
`usual memory array, an associated redundant ar-
`ray, and associated circuitry.
`Figure 8d illustrates a timing diagram for the
`operation of that illustrated in figure 8c.
`Figure 9 illustrates a plan view of on quadrant
`of an alternative embodiment of the memory ar-
`chitecture.
`Figure 10 illustrates an alternative embodiment
`of the invention's row redundancy decoder circuit
`for use in the memory architecture shown in figure
`s
`8.
`ADVANTAGES OF THE INVENTION
`A primary advantage of the invention is its
`»o
`ability to allow selection of redundant memory be-
`fore disablement of the usual memory, thereby
`resutfing in increased memory operation.
`Another primary advantage of the invention lies
`its versatility in the replacement of a defective word
`15
`line by redundant word lines.
`Still another primary advantage of the invention
`is its compact size which results in part by its not
`having to provide dedicated redundant word lines
`for each memory array.
`so
`Detailed Description of the Invention
`The Invention provides a new and improved
`redundancy scheme suitable for high density
`25 memories, i. e. memories of the size 16 megabit, 64
`megabit and greater.
`The invention's redundancy scheme is most
`adaptable for DRAM architectures which have local
`input/output (I/O) lines generally running in the
`30
`same direction as the memory bit lines. Such a
`memory architecture shall be explained below with
`regard to a memory size of about 64 megabits.
`Figure 1a illustrates a plan view of the architec-
`ture of the hierarchical multi-data lines memory.
`35 Such a memory is ideally suited for memory sizes
`of 64 megabits and greater, As shown, two col-
`umns of a plurality of 512k memory arrays (for
`ease of illustration only one 512k array is specifi-
`cally labeled) are shown with the memory arrays
`40 divided into sets of 8. Each set of eight 512k
`memory arrays comprise a 4 megabit block. Note
`that the terms 512k and 4 megabit as used herein
`throughout in many instances only approximate the
`number of memory cells. Each column of memory
`45
`arrays is spaced apart from one another along a
`line interposed between the columns of arrays.
`Bond pads substantially line up along this line. A Y
`decoder is substantially centered in the middle of a
`column of memory arrays. Wide data path circuits
`so which can operate on multiple data simultaneously
`are interspersed in a column between memory
`arrays after every eighth 512k memory array.
`Physically data travels on the path of local
`inpuVoutput lines which are shared by arrays on
`55
`each side of the wide data circuit. The wide data
`path comprises the local input/autput lines between
`memory arrays and the physical space there-
`between. As shown in figure 1b (a block diagram
`

`

`Apple – Ex. 1020
`Apple Inc., Petitioner
`4
`
`EP 0 499 131 A1
`illustrating the flow of data to the wide data path
`circuit) and figures 1c through 1e (logic diagrams
`illustrating possible logic accomplished in the wide
`data path) data travelling on said wide data path
`which originates from either of two memory arrays
`or a location external the arrays is operated upon
`by logic connected to the local input/output lines in
`the wide data path. The logic operation may com-
`prise ANDing, ORing, SHIFTING, complements of
`the foregoing and combinations thereof.
`An explanation of the wide data path circuit
`follows with reference to figure 2. Figure 2 illus-
`(rates a read/write data bus scheme which includes
`a schematic drawing of a wide data path circuit. A
`wide data path circuit is a circuit for implementing
`a read/write data bus scheme for a high speed
`DRAM such as a 64 megabit DRAM. Main
`input/output (I/O) lines are interposed between cell
`arrays. Each cell array 20 (note that only one cell
`array is shown in detail) contains a plurality of
`sense amps S/A. Selection of a sense amplifier S/A
`is governed by a signal from a sense amp select
`line S/A SEL. Line S/A SEL selects a particular
`sense amp S/A by delivering a high signal to the
`gate of a n-channel transistor 122 (Note that tor
`illustrative purposes, only two transistors 122 are
`shown for one sense amplifier even though others
`are present). A logic high signal on section select
`line SEC SEL turns on transistor 21 to allow the
`delivery of information to and from sense amps
`through local differential amplifier 124 comprised
`on n-channel transistors 28 and 30 arranged in the
`symmetrical fashion shown and connected to p-
`channel load transistors 34. READ operations are
`accomplished by sending a signal form column
`decoder YDEC along line YREAD. Local I/O line
`and (a line carrying its complement) line local 1/0_
`are precharged high by circuitry not shown. A high
`S/A signal allows passage of data form a memory
`cell (not specifically shown) through a selected
`sense amp and onto a sub I/O line pair, one line
`carrying a true signal and the other carrying its
`complement signal. A differential signal from the
`sub I/O pair output on the gates of each transistor
`28 of local differential amplifier 124 in connection
`with n-channel transistor 19 turning on as a result
`of a logic high voltage level on line YREAD creates
`a differential signal on a pair of local I/O lines, line
`I/O carrying a true signal and line 1/0_ carrying its
`complement. Differential signals on the local I/O
`lines are transferred to a pair of main I/O lines
`through transistors 32. In connection with a WRITE
`operation on a memory cell, column decoder YDEC
`places a high signal on the gates of transistors 30
`after energizing line YWRITE. Data is transferred in
`through n-channel transistors 46 through a pair of
`main I/O lines onto local lines I/O and 1/0_. A
`drain/source connecUon of transistors 230 to a local
`line (I/O or 1/0_) allows differential amplifier 124 to
`place data on a selected memory cell (not shown)
`through transistors 122 after selection by S/A SEL
`from a chossn sense amplifier.
`s
`With reference back to figure 1a, row decoders
`generally indicated at 40, lie alongside the columns
`of memory arrays and lie on an inner edge next to
`bond pads which provide bonds to the outside
`environment for functions such as address, control,
`?o
`and inpuVoutput. A row decoder is provided for
`each tow 4 megabit blocks of memory as shown. In
`connection with a signal from a Y decoder, informa-
`tion fromAo a sense amplifier (not shown) goes
`from/to the wide data path circuits which connect to
`»s main input/output lines of the memory chip. A
`channel for placement of the main input/output
`lines is shown along an edge of the row decoders.
`The provision of a plurality of wide data path cir-
`cuits to the extent of 8 per set of 512K memory
`20
`arrays allows parallel processing and thus in-
`creased speed.
`Figure 3a illustrates a plan view of another
`embodiment of the memory architecture. This em-
`bodiment is similar to the embodiment shown in
`25
`figure 1a except that the wide data path circuits,
`now shown associated with four 4 megabit memory
`blocks, are located at each end of the columns of
`memory. A signal traveling from a Y decoder for
`sense amp selection allows selection of a sense
`so amp and the import or export of data without back
`travel across the chip.
`Rgure 3b illustrates a plan view of the pre-
`fsrred embodiment of the memory architecture. In
`this embodiment note that two wide data path
`as
`circuits are centered substantially between a Y
`decoder and an edge of the memory chip. Signals
`coming from the Y decoder travelling to the farthest
`most sense amp only require the sense amp to
`send or receive a signal half the distance as com-
`-»o pared with the previous memory architecture em-
`bodiment since the wide data path circuit is at mid
`point between the Y decoder and the farthest most
`sense amp. Consequently, signals travelling be-
`tween the Y decoder and the wide data path circuit
`45
`provide service faster in the architecture shown in
`figure 3b than that of the embodiment shown in
`figure
`3a.
`Further,
`the
`memory
`architecfaj
`re
`of
`fig-
`ure 3b is less complex than that shown in figure 1a
`since half as many wide data path circuits are
`so needed in the architecture of figure 3b as com-
`pared with the architecture of figure 1a.
`Rgure 4a illustrates one 512, 00 bit memory
`cell array and its associated circuitry being gen-
`erally referenced at 2. One section of the array,
`55 being generally referenced at 4, is shown enlarged
`to facilitate discussion. The 512k array is asso-
`dated with a pair of 1024 sense amplifiers grouped
`in sets of 4 sense amplifiers each or rather 256-
`

`

`Apple – Ex. 1020
`Apple Inc., Petitioner
`5
`
`EP 0 499 131 A1
`pair sets of 4 sense amplifiers. One set of a pair of
`sense amplifiers is included within enlarged section
`4 with each sense amplifier (also called sense
`amp) being labeled S/A. The remaining pairs of
`1020 sense amplifiers are generally labeled 1k S/A.
`Each vertical row (indicated along the directions of
`arrows v) of sense amplifiers can service two 512k
`arrays of memory. Bit lines, generally indicated at
`S, are of te twisted type and connect to two sense
`amplifiers form each 512k array. Therefore, each
`sense amplifier is connected to 4 bit lines. How-
`ever, note that since only one 512k array is shown,
`a pair of bit line connections for each sense am-
`plifier is truncated along an outer edge for the other
`512k arrays. For operation upon a momory cell, Y
`decoder 8, the column decoder, selects the column
`of memory cells and row decoder 10 selects the
`row of memory cells. The transmission media from
`row decoder 10 are word lines. As shown, one
`extended arrow labeled word line and representing
`the same indicates word lines selection by row
`decoder 10. An extended arrow labeled Y select
`represents a column and indicates column selec-
`tion by Y decoder 8. Note that ths vicinity of the
`Intersection of a word line and a column can be
`equated to the location of a memory cell in the
`512k array. Thus, extended arrow Y SELECT could
`have been shown at other locations along Y de-
`coder 8 and likewise extended arrow WORD LINE
`could have been shown at other locations along
`row decoder 10. In conjunction with row decoder
`10 of the 512k array shown and Y decoder 8,
`sense amplifier selection is accomplished such that
`access to the sense amplifier is determined by
`sense amp selection circuitry 12 which selects the
`proper sense amp pair corresponding to the se-
`lected column. Sense amp selection circuitry 12
`comprises transistor pairs 14, one of the transistors
`form pair 14 acting as a pass transistor to carry a
`true signal and the other transistor from the pair
`serving as a pass transistor to carry the com-
`plement of the tme signal. Note, however, that a
`single transistor 14 symbol represents a pair of
`transistors, shown here as n-type, although p-type
`and bipolar transistors of the n-p-n or p-n-p variety
`could be used. Transistor pairs 14 are connected
`to an associated sub input/output line of a sub
`input/output pair 16. The transistor for passing the
`true signal is therefore connected to a sub
`input/output line for transmission of the true signal
`and the transistor for passing the complement of
`the true signal is connected to the other sub
`input/output line from the pair which serves to
`transmit the complement of the true signal. Note
`that a pair of the sense amp circuitry 12 can
`service an entire 512k array. A pair of pass transis-
`tors 18 are associated with each of the 256 sets of
`4 sense amplifier pairs. As with transistor pair 14,
`transistor symbol 18 represents a pair of transis-
`tors, shown here as n-type transistors. Note, how-
`ever, that p-type or bipolar transistors of the n-p-n
`or p-n-p variety could have been used. In connec-
`5
`tion with the selection of a particular sense am-
`plifier S/A, determination thereof dictated in part by
`sense amplifier selection circuitry 12 and row de-
`coder 10, a selected transistor pair 14 turns on.
`Pass transistor pair 18, associated with one of the
`»o
`256 sets of sense amplifiers turns on so as to
`provide access to a local input/output pair 20 of
`lines. Like the sub input/output pair 16 and transis-
`tor pair 14 relationship, a pas3 transistor from pair
`18 for passing a true signal connects to a local
`TS
`inpuVoutput line from pair 20, for transmission of a
`true signal. Similarly, a pass transistor from pair 18
`for passing a complemented signal connects to the
`other local input/output line from local inpul/output
`pair 20. A local input/output pair 20 for each set of
`so
`the 256 sets of sense amplifier pairs is coupled to
`wide data path circuitry 22. Selection determined
`by decoder 8 places data from selected pairs of
`the 256 local input/output pairs onto pairs of main
`inpuVoutput lines 24, the pairs comprising the true
`25 and complemented signals of the selected signals.
`For the particular case shown in figure 3a, 8 pairs
`of local input/output pair 20 are chosen from the
`256 pairs of local input/output lines for placement
`of data onto or from the main input/outpirt pair 24.
`30 However, fewer or more main input/output lines and
`consequently fewer or more local input/output pairs
`could have been chosen for selection and opera-
`tion thereupon. 128 of the 512k memory arrays
`described above are used to create the 64 megabit
`35 memory. Y decoder 8 turns on selected transistors
`18 for coupling data from a sub input/output line to
`a local input/output line. Selected transistors are
`located along arrow z. Sense amplifier select cir-
`cuitry 12 determines which group of sense amplifi-
`40
`ers and consequently, data from which 512k array
`gets placed on a sub inplrt/output pair. For in-
`stance, if 127 512k arrays and their associated
`circuitry were located along arrow z, then a signal
`form Y decoder 8 would turn on transistors 18 for
`45
`the same set of sense amplifiers in each 512k
`array. The same signal determines the column of a
`selected memory cell. Sense amplifier selection
`circuitry 12 exists for each 512k array in the z
`direction as does a row decoder 10 for each 512k
`50 array. Therefore, sense amplifier select circuitry
`determines which set of sense amplifiers are coup-
`led to a sub inpuVoutput pair of lines. Note that the
`sense amplifier selection circuitry would couple the
`same sense amplifiers to sub input/output pairs in
`55
`each of the 256 sets of sense amplifiers that exist
`along arrows v. However, Y decoder 8 determines
`which set out of the 256 sets gets selected so that
`through a transistor 18 a sub input/output pair is
`

`

`Apple – Ex. 1020
`Apple Inc., Petitioner
`6
`
`EP 0 498 131 A1
`10
`coupled to a local input/output pair. (The same
`local inpuVoutput pair is used for each array posi-
`tioned along the z direction, there being 256 local
`input/output pairs per 512k array.) Y decoder 8 also
`controls multiplex selection of wide data path cir-
`cuitry 22 for placement of data from the local
`inpuVoutput pairs to the main input/output pairs and
`vice versa.
`Figure 4b illustrates a schematic drawing of the
`sense amp circuitry for the invention. More specifi-
`cally, figure 4b illustrates one sense amp in a
`sense amp bank (column of sense amps). P-chan-
`nel transistor 308 and n-channel transistor 310 form
`an inverter cross-coupled (input connected to out-
`put and vice versa) to another inverter formed by
`p-channel transistor 310 and n-channel transistor
`314. Transistors PG act as pass gates or n-channel
`pass transistors for connection of the bit tines to
`the sense amp comprising transistors 308, 310,
`312, and 314. Lines TG provide electrical connec-
`tion to the gates of tr, ansistors PG. Equalization
`circuitry for the sense amplifier is provided by n-
`channel transistors 316, 318, and 320. When equal-
`ization signal EQ is received by the gates of these
`transistors, the voltage on bit lines BIT and BIT^ is
`equalized at around voltage Vdd/2. Note that the
`Vdd/2 voltage is provided at a node between tran-
`sistors 316 and 318. Activation of the sense amp
`occurs in connection with opposite voltage states
`appearing on lines PC and NC. Une PC switches
`between low state voltage of Vdd/2 and high state
`voltage Vdd while line NC switches between high
`state voltage of Vdd/2 and low state voltage Yss
`(as indicated by the drawings).
`Figure 5a illustrates a plan view of one quad-
`rant (for instance the upper left quadrant) of the
`invention's memory architecture. The 32 512k
`memory arrays are illustrated as blocks numbered
`from 0 to 31 with a wide data path circuit posi-
`tioned between array block 15 and 16 and a Y
`decoder (for decoding the columns of memory
`cells) situated near the array block numbered 31,
`consistent with the architecture shown in figure 3b.
`An array of four redundant word lines (4-RED.
`WORDS) are placed in array block 6 and an array
`of four redundant word lines are placed in array
`block 9. As shown, these redundant word lines are
`decoded by a row redundancy decoder (ROW
`RED. DECODER). A similar arrangement exists in
`blocks 22 and 25: namely, a set of 4 redundant
`word lines each exists in blocks 22 and 25 that are
`decoded by a row redundancy decoder. Note that
`the row redundancy decoder is contemplated as
`also being usuabte with a greater number of sets of
`redundant word lines, i.e. 3, 4, 5, 6, 7, 8, 9, 10, and
`etc. Also, the sets of redundant word lines are
`contemplated as each being made of a larger or
`smaller number than 4 redundant word lines.
`A more detailed plan view of the invention's
`memory architecture is illustrated in figure 5b. As
`shown, in each 512k array there are approximately
`256 word lines. Additionally illustrated are two ar-
`5
`rays each containing a redundancy array of 4 word
`lines. Note, that the foregoing is only one example
`embodying a concept of the invention. Conse-
`quently fewer or more word lines could form a
`redundant array.
`70
`Figure 6 illustrates a logic diagram relating to
`the activation (enablement) or disablement of a
`redundant array. OR gate 210 receives address
`bits LO to L3. OR gate 212 receives address bits
`RO to R3. The output of OR gate 210 is received
`is
`by the input of inverter 214 and the output of OR
`gate 212 is received by the input of inverter 216.
`The output of inverter 214 is received by the inputs
`of a pair of AND gates 218. One AND gate 218
`from the pair of AND gates receives as an input, bit
`20 A12, while the other AND gate 218 from the pair
`receives the complement of the signal at bit A12,
`the signal at bit A_12. The output of inverter 216
`is received by the inputs of a pair of AND gates
`219. One AND gats 219 receives as an input, the
`25
`signal at bit A12, while the other AND gate 219
`from the pair receives the signal at bit A_12. One
`AND gate 220 receives as input, output RARUI of
`AND gate 218 and output LUI of AND gate 219.
`Another AND gate 220 receives as input, output
`so RAROI of AND gate 218 and output LOI of AND
`gate 219. When either RARUI or mutually exclu-
`sively LUI are logic high a redundant array of
`memory cells is activated. When output RRNUI or
`RRNOI of one of the AND gates 220 is high, a
`35
`redundant array is disabled.
`Figure 7 illustrates a schematic drawing of the
`invention's
`row redundancy decoder circuit, of
`which two exist in the drawing of figure 5a. The
`decoder comprises a series of sub-circuits each
`40
`comprising an associated transistor array 224.
`Each field effect transistor in transistor array 224 is
`connected to a fuse (although a fuse symbol is
`used, for ease of illustration, all fuses are not
`labeled). All the fuses connect to the input of an
`45
`associated inverter 230. The input to inverter 230
`can be precharged high by precharge field effect
`transistor 226
`(which
`receives an enabling
`precharge signal P/C) in connection with a logic
`high signal received at the gate of transistor 226.
`50 As shown, field effect transistor 228 has its source
`connected to the input of inverter 230 and its gate
`connected to the ou4)ut of inverter 230. The output
`of inverter 230 is also connected to the input of
`inverter 232. Voltage Vcc represents the circuit
`55
`supply voltage. The transistors in array 224 com-
`prise pairs of transistors which receive at their
`gates an address signal and its complement. For
`instance, one transistor in a pair is shown receiving
`

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`Apple – Ex. 1020
`Apple Inc., Petitioner
`7
`
`11
`EP 0 499 131 A1
`12
`address input AO while the other transistor in the
`same pair is receiving address input A_0. Each
`sub-circuit outputs an associated address LO to L3
`and RO to R3, the inputs to OR gates 210 and 212
`discussed with respect to figure 6. Addresses LO to
`L3 and RO to R3 are input into array 250 and array
`252. Arrays 250 and 252 each comprises a series
`of AND gates with the outputs of the AND gates
`connected to the input of an associated inverter.
`Consequently, in physical realization of the circuit,
`NAND gates are substituted for the schematic re-
`presentation of an AND gate connected to the Input
`of an inverter. Note that each AND gate in array
`250 receives bit A12 and a unique address LO to
`L3 or RO to R3. Each AND gate in array 252
`receives bit A12 and a unique address bit LO to L3
`or RO to R3. Each AND gate-inverter combination
`previously discussed with respect to arrays 250
`and 252 has an output from which a signal is
`generated that is capable of enabling a redundant
`row of memory locations. These outputs are bits
`labeled from LWO to LW7 in array 250 and from
`RWO to RW7 in array 252. Applying figure 7 to the
`row redundancy decoder for redundant arrays in
`arrays 7 and 8, bits LWO through LW7 are capable
`of enabling the redundant array in array 7 while
`bits RWO through RW7 are capable of enabling the
`redundant array in array 8. Applying figure 7 to the
`row redundancy decoder for redundant arrays in
`arrays 23 and 24, bits LWO through LW7 are ca-
`pable of enabling the redundant array in array 23
`while bits RWO through RW7 are capable of en-
`abling the redundant array in array 24. Should
`there exist a defect associated wKh a word line,
`this defect is noted by purposely blowing the fuses
`in a sub-circuit in figure 7 which correspond to a
`logic one true (non-complementing,
`i. e. excluding
`A 0, A_1, A_2, and etc. ) bit address. Bits A_0
`through A11 of the sub-circuits shown in figure 7
`correspond to memory location addresses. Bits
`A 12 and A12, in large part, determine which
`redundant array is selected by the decoder. For
`instance, bit A_12 must be logic high before a
`redundant word line can be selected by outputs
`LWO through LW7, and bit A12 must be logic high
`before a redundant word line can be selected by
`outputs RWO through RW7. Consequently, redun-
`dant word tine selection is determined by selection
`of fuses that are to be blown and selection of bits
`A 12 and thus A12 logic level. In connection with
`the fuse blowing scheme discussed above with
`respect to figure 7, when a known defective mem-
`ory location is addressed, the appropriate fuses
`shall have already been blown in a particular sub-
`circuit, resulting in a logic high input to an inverter
`230. With reference, still to figure 7, inverter 232 of
`the same sub-circuit wilt consequently output a
`logic high signal to the input of a AND gate from
`either array 250 or 252, If a logic low signal serves
`as the other input to this same AND gate (either
`from a delayed signal from bit A_12 or A12 as
`shown), a logic high output will result at one of the
`s
`AND gate-lnverter combinations, LWO to LW7 In
`array 250 or RWO to RW7 in array 252. For in-
`stance, if there exists a defective word line in the
`array numbered 4 as illustrated in figure 5a, one of
`the sub-circuits shown in figure 7 will output a logic
`70 high at the output of Inverter 232, or rather at one
`of address bits LO to L3 or RO to R3. Suppose a
`logic high is output at address bit RO and that the
`signal at bit A12 is at a logic high level. A logic
`high signal will result at LW4 which activates an
`7S
`associated redundant word line. With reference to
`the logic diagram of figure 6, a logic high signal at
`RO and in connection with logic low signals at bits
`R1 through R3 and the logic high signal at bit
`A__\2, produces a logic high output at AND gate
`20 219's output LUI. As indicate