Trials@uspto.gov
`571–272–7822
`
`
`
`Paper 11
`Entered: February 7, 2017
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC,
`Patent Owner.
`____________
`
`Case IPR2016-01561
`Patent 6,233,181 B1
`____________
`
`Before BART A. GERSTENBLITH, BARBARA A. PARVIS, and
`ROBERT J. WEINSCHENK, Administrative Patent Judges.
`
`WEINSCHENK, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`571–272–7822
`
`
`
`Paper 11
`Entered: February 7, 2017
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC,
`Patent Owner.
`____________
`
`Case IPR2016-01561
`Patent 6,233,181 B1
`____________
`
`Before BART A. GERSTENBLITH, BARBARA A. PARVIS, and
`ROBERT J. WEINSCHENK, Administrative Patent Judges.
`
`WEINSCHENK, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`IPR2016-01561
`Patent 6,233,181 B1
`
`
`INTRODUCTION
`I.
`Apple Inc. (“Petitioner”) filed a Petition (Paper 1, “Pet.”) requesting
`an inter partes review of claims 3 and 5 of U.S. Patent No. 6,233,181 B1
`(Ex. 1003, “the ’181 patent”). Limestone Memory Systems LLC (“Patent
`Owner”) filed a Preliminary Response (Paper 10, “Prelim. Resp.”) to the
`Petition. An inter partes review may not be instituted “unless . . . there is a
`reasonable likelihood that the petitioner would prevail with respect to at least
`1 of the claims challenged in the petition.” 35 U.S.C. § 314(a).
`For the reasons set forth below, Petitioner demonstrates a reasonable
`likelihood of prevailing in showing the unpatentability of claims 3 and 5 of
`the ’181 patent. Accordingly, we institute an inter partes review as to
`claims 3 and 5 of the ’181 patent on the grounds specified below.
`Related Proceedings
`A.
`The parties indicate that the ’181 patent is the subject of several cases
`in the United States District Court for the Central District of California.
`Pet. 1–2; Paper 4, 4–6. The parties also indicate that the following petitions
`for inter partes review may be related to this case:
`Case No.
`Involved U.S. Patent No.
`IPR2016-00093
`U.S. Patent No. 5,805,504
`IPR2016-00094
`U.S. Patent No. 5,894,441
`IPR2016-00095
`U.S. Patent No. 5,943,260
`IPR2016-00096
`U.S. Patent No. 6,233,181
`IPR2016-00097
`U.S. Patent No. 6,697,296
`IPR2016-01567
`U.S. Patent No. 5,894,441
`Pet. 2; Paper 4, 2–3.
`The ’181 Patent
`B.
`The ’181 patent relates to repairing defective memory cells in a
`semiconductor memory device. Ex. 1003, col. 1, ll. 9–13. The ’181 patent
`
`2
`
`
`
`IPR2016-01561
`Patent 6,233,181 B1
`
`explains that, when a memory cell becomes defective, it can be replaced
`with a spare memory cell. Id. at col. 1, ll. 15–18. According to the
`’181 patent, prior semiconductor memory devices contained an array of
`spare memory cells for each memory block in the device, and, as a result, the
`spare memory cells were not used efficiently. Id. at col. 3, l. 58–col. 4, l. 8.
`To address this problem, the ’181 patent describes a semiconductor memory
`device with an array of spare memory cells that can be shared among a
`plurality of memory blocks. Id. at col. 16, ll. 31–39.
`Illustrative Claim
`C.
`Claim 3 depends from claims 1 and 2. Claims 1, 2, and 3 are
`
`reproduced below.
`1. A semiconductor memory device, comprising:
`a plurality of first memory blocks each having a plurality
`of first normal memory cells arranged in a matrix of rows and
`columns, each of said plurality of first memory blocks
`including word lines provided corresponding to said rows,
`respectively, and the first memory blocks aligned in the column
`direction; and
`a plurality of first spare memory cells arranged in a
`matrix of rows and columns in a particular one of said plurality
`of first memory blocks, each row of said plurality of first spare
`memory cells being capable of replacing a defective row
`including a defective first normal memory cell in said plurality
`of first memory blocks.
`
`2. The semiconductor memory device as recited in claim 1,
`further comprising:
`a plurality of second memory blocks arranged alternatively
`with said plurality of first memory blocks along the column
`direction, the second memory blocks each having a plurality of
`second normal memory cells arranged in a matrix of rows and
`columns; and
`
`3
`
`
`
`a plurality of second spare memory cells arranged in a
`matrix of rows and columns in a particular one of said plurality of
`second memory blocks, each row of said plurality of second spare
`memory cells being capable of replacing a defective row
`including a defective second normal memory cell in said plurality
`of second memory blocks.
`
`3. The semiconductor memory device as recited in claim 2,
`further comprising a plurality of sense amplifier bands provided
`between each of said plurality of first memory blocks and each of
`said second memory blocks, and shared by adjacent memory
`blocks in the column direction for sensing and amplifying data in
`each column of the adjacent memory block including a selected
`memory cell when activated.
`Ex. 1003, col. 45, l. 55–col. 46, l. 31.
`Evidence of Record
`D.
`Petitioner relies on the following references and declaration (Pet. 4):
`Reference or Declaration
`Exhibit No.
`Ex. 1001
`Declaration of Dr. Pinaki Mazumder (“Mazumder
`Declaration”)
`Sukegawa et al., U.S. Patent No. 5,487,040 (issued Jan. 23,
`1996) (“Sukegawa”)
`Fujishima et al., U.S. Patent No. 5,267,214 (issued Nov. 30,
`1993) (“Fujishima”)
`Walck, U.S. Patent No. 4,967,397 (issued Oct. 30, 1990)
`(“Walck”)
`Asserted Grounds of Unpatentability
`E.
`Petitioner asserts that the challenged claims are unpatentable on the
`following grounds (Pet. 5):
`Claim
`Basis
`3
`35 U.S.C. § 103(a)
`5
`35 U.S.C. § 103(a)
`
`References
`Sukegawa and Fujishima
`Sukegawa, Fujishima, and
`Walck
`
`IPR2016-01561
`Patent 6,233,181 B1
`
`
`4
`
`Ex. 1005
`
`Ex. 1006
`
`Ex. 1007
`
`
`
`IPR2016-01561
`Patent 6,233,181 B1
`
`
`II. ANALYSIS
`A. Claim Construction
`The claims of an unexpired patent are interpreted using the broadest
`reasonable interpretation in light of the specification of the patent in which
`they appear. 37 C.F.R. § 42.100(b); Cuozzo Speed Techs., LLC v. Lee, 136
`S. Ct. 2131, 2144–46 (2016). The parties agree that no claim construction is
`necessary at this stage of the proceeding. Pet. 6; Prelim. Resp. 18–19.
`Therefore, on this record and for purposes of this decision, we determine
`that no claim terms require express construction. See Vivid Techs., Inc. v.
`Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999) (“[O]nly those
`terms need be construed that are in controversy, and only to the extent
`necessary to resolve the controversy.”).
`Asserted Grounds of Unpatentability
`B.
`Obviousness of Claim 3 over Sukegawa and Fujishima
`1.
`Petitioner argues that claim 3 would have been obvious over
`Sukegawa and Fujishima. Pet. 5. We have reviewed the parties’ assertions
`and supporting evidence. For the reasons discussed below, Petitioner
`demonstrates a reasonable likelihood of prevailing in showing that claim 3
`would have been obvious over Sukegawa and Fujishima.
`Claim 3 depends from claims 1 and 2. Ex. 1003, col. 45, l. 55–
`col. 46, l. 31. Petitioner identifies evidence indicating that Sukegawa
`teaches the limitations in claims 1 and 2. Pet. 39–52. Patent Owner does
`not raise any specific disputes with respect to the limitations in claims 1 and
`
`5
`
`
`
`IPR2016-01561
`Patent 6,233,181 B1
`
`2.1 On this record, Petitioner has shown sufficiently that the combination of
`Sukegawa and Fujishima teaches the limitations in claims 1 and 2.
`Claim 3 recites
`a plurality of sense amplifier bands provided between each of
`said plurality of first memory blocks and each of said second
`memory blocks, and shared by adjacent memory blocks in the
`column direction for sensing and amplifying data in each
`column of the adjacent memory block including a selected
`memory cell when activated.
`Ex. 1003, col. 46, ll. 24–31. Petitioner identifies evidence indicating that
`Fujishima teaches a plurality of sense amplifier bands provided between
`each of a plurality of first memory blocks and each of a plurality of second
`memory blocks. Pet. 53–55 (citing Ex. 1006, Abstract, col. 1, ll. 11–14,
`col. 15, ll. 24–28, col. 24, ll. 26–39, col. 25, ll. 34–47, Fig. 14). Petitioner
`also identifies evidence indicating that the sense amplifier bands in
`Fujishima are shared by adjacent memory blocks in the column direction for
`sensing and amplifying data in each column of the adjacent memory block
`including a selected memory cell when activated. Id. at 55–59 (citing
`Ex. 1006, col. 2, ll. 11–17, col. 24, ll. 35–58, col. 25, ll. 3–15, Figs. 8, 14).
`Patent Owner responds that neither Sukegawa nor Fujishima teaches a
`memory that shares sense amplifier bands and spare memory cells between
`different memory blocks. Prelim. Resp. 23–27. Patent Owner’s argument is
`not persuasive because it addresses the teachings in Sukegawa and
`Fujishima individually, not the combination proposed by Petitioner. See In
`
`
`1 In IPR2016-00096, we granted Patent Owner’s request for adverse
`judgment with respect to claims 1, 2, 4, 6, and 7 of the ’181 patent. Micron
`Tech., Inc. v. Limestone Memory Sys. LLC, Case IPR2016-00096, slip op. at
`2 (PTAB Aug. 3, 2016) (Paper 11).
`
`6
`
`
`
`IPR2016-01561
`Patent 6,233,181 B1
`
`re Keller, 642 F.2d 413, 426 (CCPA 1981) (“[O]ne cannot show non-
`obviousness by attacking references individually where, as here, the
`rejections are based on combinations of references.”). Specifically,
`Petitioner argues that Sukegawa teaches replacing defective memory cells in
`one memory block with spare memory cells from another memory block
`(Pet. 46–47), and Fujishima teaches sharing sense amplifier bands between
`adjacent memory blocks (id. at 53–59). Thus, on this record, Petitioner has
`shown sufficiently that the combination of Sukegawa and Fujishima teaches
`the limitations in claim 3.
`Petitioner argues that it would have been obvious to combine the cited
`teachings in Sukegawa and Fujishima. Pet. 59–63. Specifically, Petitioner
`argues that Sukegawa and Fujishima relate to the same field of endeavor,
`namely the design and architecture of dynamic random access memory
`(“DRAM”). Id. at 59 (citing Ex. 1005; Ex. 1006). Further, according to
`Petitioner, Fujishima teaches that there are several benefits to using shared
`sense amplifier bands, such as providing accurate sensing of small memory
`cells, reducing parasitic capacitance of bit lines associated with memory
`cells, reducing power consumption, and increasing production yield. Id. at
`61 (citing Ex. 1006, col. 1, ll. 27–42, col. 1, ll. 47–50, col. 2, ll. 4–9, col. 13,
`ll. 24–26). Petitioner identifies evidence indicating that a person of ordinary
`skill in the art would have recognized that the benefits of the shared sense
`amplifier bands in Fujishima would improve the memory in Sukegawa. Id.
`(citing Ex. 1001 ¶¶ 46, 141). Petitioner also identifies evidence indicating
`that “there would have been no undue obstacle” to combining the cited
`teachings in Sukegawa and Fujishima. Id. at 62 (citing Ex. 1001 ¶ 143).
`
`7
`
`
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`IPR2016-01561
`Patent 6,233,181 B1
`
`
`Patent Owner responds that Petitioner has not shown sufficiently that
`it would have been obvious to combine the cited teachings in Sukegawa and
`Fujishima. Prelim. Resp. 27–44. First, Patent Owner argues that the
`additional references mentioned in the Petition teach away from the
`proposed combination of Sukegawa and Fujishima. Id. at 28–35. Patent
`Owner specifically points out that none of the additional references
`mentioned in the Petition teach a memory that shares sense amplifier bands
`and spare memory cells between different memory blocks. Id. We are not
`persuaded, though, that a person of ordinary skill in the art would have been
`discouraged from combining the cited teachings in Sukegawa and Fujishima
`simply because Petitioner does not identify a single reference that discloses
`each of the limitations of claim 3.
`Patent Owner also points out that the Horiguchi reference (Ex. 1009)
`mentioned in the Petition states “that inter-subarray replacement (to replace
`a defective normal line in a subarray by a spare line in another subarray)
`should be avoided in DRAM redundancy, because of the cumbersome
`control of memory-array associated circuitry, especially the sense circuit.”
`Prelim. Resp. 30 (quoting Ex. 1009, 1–2) (emphasis omitted); id. at 40. In
`other words, Horiguchi indicates that replacing a defective memory cell in
`one memory block with a spare memory cell from another block can be
`cumbersome. Ex. 1009, 1–2. In contrast, though, Sukegawa expressly
`encourages using this type of memory cell replacement. Pet. 46; Ex. 1005,
`col. 2, ll. 21–59. Thus, on this record, we are not persuaded that Horiguchi
`would have discouraged a person of ordinary skill in the art from using the
`memory cell replacement in Sukegawa or from combining it with the shared
`sense amplifier bands in Fujishima.
`
`8
`
`
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`IPR2016-01561
`Patent 6,233,181 B1
`
`
`Second, Patent Owner argues that “the Petition makes no showing that
`Sukegawa could tolerate the complication added by implementing the shared
`sense amplifier design from Fujishima.” Prelim. Resp. 36 (citing Ex. 1006,
`col. 24, l. 65–col. 25, l. 14, Fig. 14); id. at 27–28. In particular, Patent
`Owner contends that “the bit line selecting switches BS would have to be
`reconfigured to enable sense amplifiers associated with the spare wordlines,
`which might, as disclosed in Sukegawa, reside in separate memory blocks.”
`Id. at 36. On this record, Patent Owner’s argument is not persuasive. As
`discussed above, Petitioner identifies evidence indicating that “there would
`have been no undue obstacle” to combining the cited teachings in Sukegawa
`and Fujishima. Pet. 62 (citing Ex. 1001 ¶ 143). Further, even assuming, as
`Patent Owner contends, that the bit line selecting switches in Sukegawa
`would have to be reconfigured to accommodate the shared sense amplifier
`bands in Fujishima, Patent Owner does not identify specific evidence
`indicating that doing so would have been beyond the level of ordinary skill
`in the art. See Prelim. Resp. 36–37.
`Third, Patent Owner argues that “[e]ach of the motivations offered by
`the Petition is premised on the argument that the concepts taught both in
`Sukegawa and Fujishima were well-known,” but “[j]ust because elements
`are well known does not establish that such elements would be obviously
`combined by one of ordinary skill in the art.” Prelim. Resp. 37. On this
`record, Patent Owner’s argument is not persuasive. Petitioner does more
`than just argue that the concepts in Sukegawa and Fujishima were well
`known. As discussed above, Petitioner identifies evidence indicating that
`there are benefits to using the shared sense amplifier bands in Fujishima, and
`that a person of ordinary skill in the art would have recognized that the
`
`9
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`IPR2016-01561
`Patent 6,233,181 B1
`
`benefits of the shared sense amplifier bands in Fujishima would improve the
`memory in Sukegawa. Pet. 61 (citing Ex. 1001 ¶¶ 46, 141; Ex. 1006, col. 1,
`ll. 27–42, col. 1, ll. 47–50, col. 2, ll. 4–9, col. 13, ll. 24–26).
`Fourth, Patent Owner argues that “[t]he Petition cites several general
`benefits of the shared sense amplifier design but does not explain how these
`general benefits would relate ‘particularly’ to the memory disclosed by
`Sukegawa.” Prelim. Resp. 41. On this record, Patent Owner’s argument is
`not persuasive. Petitioner identifies evidence indicating that the specific
`benefits provided by the shared sense amplifier bands in Fujishima would
`have been “particularly useful” to the memory in Sukegawa. Pet. 61–62
`(citing Ex. 1001 ¶ 142; Ex. 1005, col. 3, ll. 4–15, col. 3, ll. 25–32,
`col. 3, ll. 51–53).
`Lastly, Patent Owner argues that Petitioner does not address the
`objective indicia of nonobviousness. Prelim. Resp. 43. Specifically, Patent
`Owner argues that the earliest possible filing date of the ’181 patent is six
`years after the earliest possible filing date of Sukegawa. Id. Thus,
`according to Patent Owner, “there existed a long felt need that had not been
`accommodated by the ordinary skill in the art.” Id. On this record, Patent
`Owner’s argument is not persuasive. Patent Owner does not identify
`specifically what need had not been accommodated, and Patent Owner does
`not identify specific evidence indicating that any such need had been
`recognized by those of ordinary skill in the art. See id.
`For the reasons discussed above, Petitioner demonstrates a reasonable
`likelihood of prevailing in showing that claim 3 would have been obvious
`over Sukegawa and Fujishima.
`
`10
`
`
`
`IPR2016-01561
`Patent 6,233,181 B1
`
`
`2.
`
`Obviousness of Claim 5 over Sukegawa, Fujishima, and
`Walck
`Petitioner argues that claim 5 would have been obvious over
`Sukegawa, Fujishima, and Walck. Pet. 5. We have reviewed the parties’
`assertions and supporting evidence. For the reasons discussed below,
`Petitioner demonstrates a reasonable likelihood of prevailing in showing that
`claim 5 would have been obvious over Sukegawa, Fujishima, and Walck.
`Claim 5 depends from claim 3, and recites “wherein said plurality of
`first memory blocks, said plurality of second memory blocks and said
`plurality of sense amplifier bands form a first memory array, and said
`semiconductor memory device further comprises: a second memory array
`having a same arrangement as the first memory array.” Ex. 1003, col. 46,
`ll. 36–43. Petitioner identifies evidence indicating that the combination of
`Sukegawa and Fujishima teaches several memory arrays, each of which
`includes a plurality of first memory blocks, a plurality of second memory
`blocks, and a plurality of sense amplifier bands. Pet. 64–65 (citing
`Ex. 1005, col. 1, ll. 39–43, Fig. 1; Ex. 1006, col. 24, ll. 35–36). On this
`record, Petitioner has shown sufficiently that the combination of Sukegawa,
`Fujishima, and Walck teaches the above limitation of claim 5.
`Claim 5 further recites wherein said semiconductor memory device
`further comprises
`control circuitry for driving one memory block from the first
`and second memory arrays into a selected state in a normal
`operation mode, and for simultaneously driving a prescribed
`number of memory blocks from each of said first and second
`memory arrays into a selected state in a particular operation
`mode.
`
`11
`
`
`
`IPR2016-01561
`Patent 6,233,181 B1
`
`Ex. 1003, col. 46, ll. 44–50. Petitioner identifies evidence indicating that
`Walck teaches control circuitry that drives a particular memory block during
`a normal operating mode, such as a READ/WRITE operation. Pet. 67–68
`(citing Ex. 1007, col. 1, ll. 44–46, col. 1, ll. 57–67, col. 2, ll. 8–10, col. 8,
`ll. 18–26). Petitioner also identifies evidence indicating that the control
`circuitry in Walck simultaneously drives the memory blocks in all the
`memory arrays during a memory refresh mode. Id. at 69 (citing Ex. 1007,
`col. 1, ll. 47–48, col. 1, ll. 57–67, col. 2, ll. 10–13, col. 8, ll. 26–29). On this
`record, Petitioner has shown sufficiently that the combination of Sukegawa,
`Fujishima, and Walck teaches the above limitation of claim 5.
`Petitioner argues that it would have been obvious to combine the cited
`teachings in Walck with the cited teachings in Sukegawa and Fujishima. Id.
`at 70–71. Specifically, Petitioner argues that, like Sukegawa and Fujishima,
`Walck relates to the design and architecture of DRAM. Id. at 70 (citing
`Ex. 1007, col. 1, l. 11–col. 2, l. 32). Petitioner identifies evidence indicating
`that a person of ordinary skill in the art would have recognized that the
`control circuitry in Walck would be useful for a memory that has multiple
`banks, such as the memory in Sukegawa. Id. at 70 (citing Ex. 1001 ¶ 154;
`Ex. 1007, col. 7, l. 45–col. 8, l. 9). Petitioner also identifies evidence
`indicating that “there would have been no undue obstacle” to combining the
`control circuitry in Walck with the cited teachings in Sukegawa and
`Fujishima. Id. at 70–71 (citing Ex. 1001 ¶ 154). On this record, Petitioner
`has shown sufficiently that it would have been obvious to combine the cited
`teachings in Walck with the cited teachings in Sukegawa and Fujishima.
`Patent Owner relies on the same arguments discussed above with
`respect to claim 3. Prelim. Resp. 44. For the reasons discussed above, on
`
`12
`
`
`
`IPR2016-01561
`Patent 6,233,181 B1
`
`this record, Patent Owner’s arguments are not persuasive. See supra
`Section II.B.1. Therefore, Petitioner demonstrates a reasonable likelihood of
`prevailing in showing that claim 5 would have been obvious over Sukegawa,
`Fujishima, and Walck.
`
`III. CONCLUSION
`Petitioner demonstrates a reasonable likelihood of prevailing in
`showing the unpatentability of claims 3 and 5 of the ’181 patent. At this
`stage in the proceeding, we have not made a final determination with respect
`to the patentability of any of the challenged claims.
`
`IV. ORDER
`In consideration of the foregoing, it is hereby:
`ORDERED that, pursuant to 35 U.S.C. § 314(a), an inter partes
`
`review is hereby instituted as to claims 3 and 5 of the ’181 patent on the
`following grounds:
`A. Claim 3 as obvious over Sukegawa and Fujishima under 35
`U.S.C. § 103(a); and
`Claim 5 as obvious over Sukegawa, Fujishima, and Walck
`B.
`under 35 U.S.C. § 103(a);
`FURTHER ORDERED that, pursuant to 35 U.S.C. § 314(a), an inter
`partes review of the ʼ181 patent is hereby instituted commencing on the
`entry date of this Order, and, pursuant to 35 U.S.C. § 314(c) and 37 C.F.R.
`§ 42.4, notice is hereby given of the institution of a trial; and
`
`FURTHER ORDERED that the trial is limited to the grounds
`identified, and no other grounds are authorized.
`
`
`
`13
`
`
`
`IPR2016-01561
`Patent 6,233,181 B1
`
`PETITIONER:
`
`John R. Hutchins
`Rose Cordero Prey
`Michael N. Zachary
`ANDREWS KURTH KENYON LLP
`jhutchins@kenyon.com
`roseprey@andrewskurthkenyon.com
`michaelzachary@andrewskurthkenyon.com
`
`
`
`PATENT OWNER:
`
`Nicholas T. Peters
`Paul B. Henkelmann
`FITCH EVEN TABIN & FLANNERY LLP
`ntpete@fitcheven.com
`phenkelmann@fitcheven.com
`
`14
`
`
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