Page 1 of 32
`
`Samsung Exhibit 10(cid:20)(cid:19)
`Samsung Electronics Co., Ltd. v. Daniel L. Flamm
`
`

`
`0 272 140
`
`is
`
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`'gers (20) which collectively remove the wafer (15)
`from a robot
`transfer blade (24) and position the
`wafer with variable, controlled, close parallel spacing
`between the wafer and the chamber gas inlet mani-
`fold (26) then return the wafer to the blade. A com-
`bined RF/gas
`feed-through device (36) protects
`against process gas leaks and applies RF energy to
`the gas inlet manifold without internal breakdown or
`deposition of the gas. The gas inlet manifold (26) is
`adapted for providing uniform gas flow over the
`wafer. Temperature-controlled internal and external
`manifold surfaces suppress condensation, premature
`reactions and decomposition and deposition on the
`external surfaces. The reactor also incorporates a
`uniform radial pumping gas system which enables
`uniform reactant gas flow across the wafer and
`directs purge gas flow downwardly and upwardly
`toward the periphery of the water for sweeping ex-
`haust fases radially away from the wafer to prevent
`deposition outside the wafer and keep the chamber
`clean. The reactor provides uniform processing over
`a wide range of pressure including very high pres-
`sures. A low temperature CVD process for forming a
`highly conformal layer of silicon dioxide is also dis-
`closed. The process" uses very high chamber pres-
`sure and low temperature, and TEOS and ozone
`reactants. The low temperature CVD silicon dioxide E I
`de osition ste
`is
`articularl
`useful for
`Ianarizin
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`ungerlying stegpedpdielectricylayers, either alone 03
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`A‘
`
`in conjunction with a subsequent isotropic etch. A
`preferred in-situ multiple-step process for forming a
`planarized silicon dioxide layer uses (1) high rate
`silicon dioxide deposition at a low temperature and
`.
`..
`high pressure followed by (2) the deposition of the
`conformal silicon dioxide layer also at high pressure
`and low temperature, followed by (3) a high rate
`isotropic etch. preferably at
`low temperature and
`high pressure in the same reactor used for the two
`oxide deposition steps. Various combinations of the
`steps are disclosed for different applications, as is a
`preferred reactor self-cleaning step.
`
`Page 2 of 32
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`

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`0 272 140
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`THERMAL CVD/PECVD REACTOR AND USE FOR THERMAL CHEMICAL VAPOR DEPOSITION OF SILICON
`
`Background 9_f me invention
`
`The present invention relates to a reactor and
`methods for performing single and in-situ multiple
`integrated circuit processing steps,
`including ther-
`mal CVD, plasma-enhanced chemical vapor depo-
`sition (PECVD), reactor self-cleaning, film etchback,
`and modification of profile or other film property by
`sputtering. The present invention also relates to a
`process for forming conformal, planar dielectric lay-
`ers on integrated circuit wafers and to an in-situ
`multi-step process for forming conformal. planar
`dielectric layers that are suitable for use as inter-
`level dielectrics for multi-layer metallization inter-
`connects.
`
`10
`
`l. Reactor
`
`I
`
`The early gas chemistry deposition reactors
`that were applied to semiconductor integrated cir-
`cuit fabrication used relatively high temperature.
`thermally-activated chemistry to deposit from a gas
`onto a heated substrate. Such chemical vapor de-
`position of a solid onto a surface involves a het-
`erogeneous surface reaction of gaseous species
`that adsorb onto the surface. The rate of
`film
`
`growth and the film quality depend on the wafer
`surface temperature and on the gaseous species
`available.
`
`low temperature plasma-en-
`recently,
`More
`hanced deposition and etching techniques have
`been developed for forming diverse materials,
`in-
`cluding metals such as aluminum and tungsten,
`dielectric films such as silicon nitride and silicon
`dioxide, and semiconductor films such as silicon.
`The plasma used in the available plasma-en-
`hanced chemical vapor deposition processes is a
`low pressure reactant gas discharge which is de-
`veloped in an RF field. The plasma is. by definition,
`an electrically neutral
`ionized gas in which there
`are equal number densities of electrons and ions.
`At the relatively low pressures used in PECVD. the
`discharge is in the "glow" region and the electron
`energies can be quite high relative to heavy par-
`ticle energies. The very high electron temperatures
`increase the density of disassociated species with-
`in the plasma which are available for deposition on
`nearby surfaces (such as substrates). The en-
`hanced supply of
`reactive free radicals in the
`PECVD processes makes possible the deposition
`of dense, good quality films at lower temperatures
`and at faster deposition rates (300-400 Angstroms
`
`per minute) than are typically possible using purely
`thermally-activated CVD processes (100-200 Ang-
`stroms per minute). However, the deposition rates
`available using conventional plasma-enhanced pro-
`cesses are still relatively low.
`Presently, batch-type reactors are used in most
`commercial PECVD applications. The batch reac-
`tors process a relatively large number of wafers at
`once and, thus, provide relatively high throughput
`despite the low deposition rates. However, single-
`wafer reactors have certain advantages. such as
`the lack of within-batch uniformity problems. which
`make such reactors attractive, particularly for large,
`expensive wafers such as 5-8 inch diameter wafers.
`In addition, and quite obviously. increasing the de-
`position rate and throughput of such single wafer
`reactors and further increase their range of useful
`applications.
`
`ll. Thermal CVD of SE02; Planarization Process
`
`Recently integrated circuit (IC) technology has
`advanced from large scale integration (LSl) to very
`large scale integration (VLSI) and is projected to
`grow the ultra-large integration (ULSl) over the next
`several years. This advancement in monolithic cir-
`cuit
`integration has been made possible by im-
`provements in the manufacturing equipment as well
`as in the materials and methods used in process-
`ing semiconductor wafers into lC chips. However,
`the incorporation into IC chips of, first, increasingly
`complex devices and circuits and. second. greater
`device densities
`and smaller minimum feature
`
`imposes increas-
`sizes and smaller separations,
`ingly stringent requirements on the basic integrated
`circuit fabrication steps of masking, film formation,
`doping and etching.
`it
`As an example of the increasing complexity,
`is projected that. shortly. typical MOS (metal oxide
`semiconductor) memory circuits will contain two
`levels of metal interconnect layers, while MOS log-
`ic circuits may well use two to three metal intercon-
`nect layers and bipolar digital circuits may require
`three to four such layers. The increasing complex-
`lty. thickness/depth and small size of such multiple
`interconnect levels make it increasingly difficult to
`fabricate the required conformal, planar interlevel
`dielectric layers materials such as silicon dioxide
`that support and electrically isolate such metal in-
`terconnect layers.
`The difficulty in forming planarized conformal
`coatings on small stepped surface topographies is
`illustrated in FlG. 16. There, a first film such as a
`
`Page 3 of 32
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`

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`0 272 140
`
`4
`
`layer 171 has been formed over the
`conductor
`existing stepped topography of a partially com-
`pleted integrated circuit (not shown) and is under-
`going the deposition of an interlayer dielectric layer
`172 such as silicon dioxide. This is done prepara-
`tory to the formation of a second level conductor
`layer (not shown). Typically. where the mean-free
`path of the depositing active species is long com-
`pared to the step dimensions and where there is no
`rapid surface migration, the deposition rates at the
`bottom 173. the sides 174 and the top 175 of the
`stepped topography are proportional
`to the asso-
`ciated arrival angles. The bottom and side arrival
`angles are a function of and are limited by the
`depth and small width of the trench. Thus, for very
`narrow and/or deep geometries the thickness of the
`bottom layer 173 tends to be deposited to a lesser
`thickness than is the side layer 174 which.
`in turn.
`is less than the thickness of top layer 175.
`increasing the pressure used in the deposition
`process typically will increase the collision rate of
`the active species and decrease the mean-free
`path. This would increase the arrival angles and.
`thus. increase the deposition rate at the sidewalls
`714 and bottom 173 of the trench or step. How-
`ever, and referring to FIG. 17A, this also increases
`the arrival angle and associated deposition rate at
`stepped corners 176.
`the
`For steps separated by a wide trench,
`resulting inwardly sloping film configuration forms
`cusps 177-177 at the sidewall-bottom interface. It is
`difficult
`to form conformal metal and/or dielectric
`layers over such topographies. As a consequence,
`it
`is necessary to separately planarize the topog-
`raphy.
`in addition, and referring to FIG. 17B, where
`the steps are separated by a narrow trench, for
`example,
`in dense 256 kilobit VLSl structures, the
`increased deposition rate at
`the corner 178 en-
`closes a void 178. Such voids are exposed by
`subsequent planarization procedures and may al-
`low the second level conductor to penetrate and
`run along the void and short the conductors and
`devices along the void.
`
`Summary o_f me Invention
`
`Obiects
`
`In view of the above discussion, it is one object
`to provide a semiconductor processing reactor
`which provides uniform deposition over a wide-
`range of pressures, including very high pressures.
`It is another related object to provide a versa-
`tile single wafer semiconductor processing reactor
`which can be used for a multiplicity of processes
`including
`thermal
`chemical
`vapor
`deposition.
`
`deposition.
`vapor
`chemical
`plasma-enhanced
`self-cleaning
`plasma-assisted etchback, plasma
`and sputter topography modification, either alone
`or in-situ in a multiple process sequence.
`It is a related object to provide such a reactor
`which accomplishes the above objectives and also
`is adapted for using unstable gases such as TEOS
`and ozone.
`It is another object of the present invention to
`provide a process for
`forming highly conformal
`silicon dioxide layers, even over small dimension
`stepped topographies in VLSI and ULSl devices.
`using ozone and TEOS gas chemistry and thermal
`CVD.
`it is also an object of the present invention to
`provide a planarization process which provides ex-
`cellent conformal coverage and eliminates cusps
`and voids.
`it is still another object of the present invention
`to provide a planarization process which can be
`performed in-situ using a multiple number of steps.
`in the same plasma reactor chamber. by simply
`changing the associated reactant gas chemistry
`and operation conditions.
`it is yet another object of the present invention
`to provide an in-situ multiple step process including
`plasma deposition and isotropic etching of a wafer
`for the purpose of optimizing coating conformality
`and planarization, along with process throughput
`and wafer characteristics such as low particulates.
`Another object
`is
`to provide the above-de-
`scribed versatile process characteristics along with
`the ability to vary the process sequence and the
`number of steps.
`including but not limited to the
`addition of reactor self-cleaning.
`
`Summary
`
`in one specific aspect, our invention relates to
`a semiconductor processing reactor defining a
`chamber for mounting a wafer therein and an inlet
`gas manifold for supplying reactant gases to the
`wafer. The chamber also incorporates a uniform
`radial pumping system which includes vacuum ex-
`haust pump means; a gas distributor plate mounted
`peripherally about
`the wafer mounting position
`within the chamber and including a circular array of
`exhaust holes therein; and a circular channel be-
`neath and communicating with the hole array and
`having at
`least a single point connection to the
`vacuum exhaust pump for flowing gases radially
`from the inlet manifold across
`the wafer and
`
`through the exhaust port. The channel is of suffi-
`ciently large volume and conductance relative to
`the holes to enable controlled uniform radial gas
`flow across the wafer to the exhaust holes, thereby
`promoting uniform flow and processing (etching
`
`Page 4 of 32
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`0 272 140
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`and-deposition) over a wide range of pressures,
`including very high pressures up to about one
`atmosphere.
`In" another aspect, the present invention is di-
`rected to a semiconductor processing reactor
`which comprises a housing forming a chamber for
`mounting a wafer horizontally, a vacuum exhaust
`pumping system communicating with the chamber,
`and an inlet gas manifold oriented horizontally over
`the wafer mounting position. The manifold has a
`central array of process gas apertures configured
`for dispensing reactant gas uniformly over the wa-
`far and a second peripheral array of purging gas
`apertures configured for directing purging gas
`downward to the periphery of the wafer. The hole
`arrays are also arranged to eliminate radial align-
`ment of holes.
`
`the reactor incorporates a
`in another aspect.
`system for circulating fluid of controlled tempera-
`ture within the manifold for maintaining the internal
`surfaces within a selected temperature range to
`prevent condensation and reactions within the
`manifold and for maintaining the external manifold
`surfaces above a selected temperature range for
`eliminating unwanted deposition thereon.
`the
`in
`still another aspect.
`the reactor of
`present
`invention comprises a thin susceptor for
`supporting a wafer, susceptor support means for
`mounting the susceptor in a horizontal position
`precisely parallel
`to the gas inlet manifold and
`means for selectively moving the wafer support
`means vertically to position the susceptor and sup-
`port parallel
`to the gas manifold at
`selected
`variable-distance positions closely adjacent the gas
`manifold.
`in particular,
`the variable parallel close
`spacing can be 0.5 centimeter and smaller.
`In still another aspect, the semiconductor pro-
`cessing reactor of the present invention comprises
`a housing defining a chamber therein adapted for
`the gas chemistry processing of a wafer positioned
`within the chamber. A transparent window forms
`the bottom of the chamber. A thin high emissivity
`susceptor is used for supporting a water within the
`chamber. A radiant heating module comprising a
`circular array of lamps mounted in a reflector mod-
`ule is mounted outside the housing for directing a"
`substantially collimated beam of near-infrared ra-
`diant energy through the window onto the suscep-
`tor with an incident power density substantially
`higher at
`the edge of the susceptor than at the
`center thereof, to heat the wafer uniformly.
`Preferably. a second, purge gas manifold is
`positioned beneath the wafer processing area for
`providing purging gas flow across the window and
`upward and across the bottom of the wafer. The
`combination of the high pressure,
`the purge flow
`from the inlet gas manifold and that from the purge
`gas manifold substantially eliminates deposition on
`
`chamber surfaces.
`
`the
`the reactor of
`still another aspect,
`In
`present invention comprises a deposition gas feed-
`through device connected "to the gas inlet manifold
`which comprises tube means adapted for providing
`co-axial flow of deposition gas on the inside of the
`tube and purge gas on the outside thereof into the
`gas inlet manifold. The tube is adapted for connec-
`tion to ground at the inlet end and to an RF power
`supply at the outlet or manifold end to provide RF
`power to the manifold, and has a controlled elec-
`trical impedance along its length from the inlet to
`the outlet end for establishing a constant voltage
`gradient to prevent breakdown of the gas even at
`high RF frequencies and voltages.
`These and other features discussed below per-
`mit reactor operation over a wide pressure regime.
`that
`is, ‘over a wide of pressures including high
`pressures up to approximately one atmosphere.
`The features also provide uniform susceptor and
`wafer temperatures,
`including both absolute tem-
`perature uniformity and spatial uniformity across
`the susceptor/wafer; uniform gas flow distribution
`across the wafer; and effective purging. The vari-
`able parallel close spacing between the electrodes
`adapts the reactor to various processes. These
`features and the temperature control of the internal
`and external gas manifold temperatures enable the
`advantageous use of very sensitive unstable gases
`such as ozone and TEOS in processes such as the
`following.
`That is, the present invention also relates to a
`method for depositing a conformal
`layer of silicon
`dioxide onto a substrate by exposing the substrate
`to a reactive species formed from ozone, oxygen,
`tetraethylorthosilicate, and a carrier gas within a
`vacuum chamber. using a total gas pressure within
`the chamber 10 torr to 200 torr and a substrate
`
`temperature within the range of about 200°C to
`500°C. Preferably, a
`substrate temperature of
`about 375°C 120°C is used to obtain maximum
`deposition rates and the chamber pressure is about
`40 torr to 120 torr.
`
`In still another aspect, the present invention is
`embodied in a method for depositing silicon diox-
`ide onto a film or substrate by exposing the sub-
`strate to the plasma formed from tetraethylor-
`thosilicate, oxygen and a carrier gas in a chamber
`using a total gas pressure within the range of about
`1
`to 50 torr, and a substrate temperature in the
`range of about 200°C to 500°C. Preferably.
`the
`chamber pressure is 8-12 torr and the substrate
`temperature is about 375°C 120°C.
`in still another aspect, the invention is directed
`to a method for isotropically etching a silicon diox-
`ide surface comprising the step of exposing a
`silicon dioxide surface to a plasma formed from
`fluorinate gas such as NF3, CFA and C2Fs
`in a
`
`Page 5 of 32
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`

`
`O 272 140
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`carrier gas in a chamber using a water temperature
`in the range of from about 200°C to 500°C. Prefer-
`ably, the chamber pressure is within the range of
`about 200 mT to 20 torr, and 500 mT to 10 torr.
`The invention is also embodied in a method for
`
`planarizing a non-planar dielectric coating or com-
`posite within a vacuum chamber by depositing a
`conformal
`layer of silicon dioxide onto the coating
`by exposing the coating to a reactive species
`formed from ozone, oxygen, tetraethylorthosilicate
`and a carrier gas, the total chamber gas pressure
`being within the approximate range 10 torr to 200
`torr and the substrate temperature being within the
`approximate range 200°C to 500°C,
`to thereby
`form a composite of the conformal
`layer on the
`‘substrate; and lsotropically etching the outer sur-
`face of the resulting composite layer. Preferably,
`this planarizing process uses the plasma oxide
`deposition to first form a layer of silicon oxide and
`also uses the isotropic etch described above.
`
`Brief Description Q‘ mg Drawings
`
`The above and other aspects and advantages
`of the present invention are described in conjunc-
`tion with the following drawing figures, in which:
`FIG.
`1
`is a top plan view of a preferred
`embodiment of the combined CVD/PECVD reactor
`of
`the present
`invention, shown with the cover
`pivoted open;
`FIG. 2 is a vertical cross-section, partly in -
`schematic, taken along line 2-2 in FIG. 1, with the
`reactor cover closed;
`FIG. 3 is a vertical cross-section through the
`wafer elevator mechanism, taken along line 3-3 in
`FIG. 1;
`
`FIGS. 4-8 are sequential, highly schematized
`representations of the operation of the wafer trans-
`port system in positioning wafers within, and re-
`moving wafers from the reactor susceptor;
`FIG. 9 is a reduced scale, horizontal cross-
`section through the circular-array,
`radiant
`lamp
`heating assembly, taken along line 9-9 in FIG. 2;
`FIG. 10 is an enlarged, partial depiction of
`FIG. 2 showing the process gas and purge distribu-
`tion systems in greater detail;
`FIG. 11 is a partial, enlarged bottom plan
`view of the gas distribution head or manifold;
`FIG. 12 depicts an enlarged, vertical cross-
`section of the RF/gas feed-through system shown
`in FIG. 2;
`-
`FIGS. 13A-13C schematically depict various
`alternative embodiments of the gas feed-through;
`FIG. 14 illustrates breakdown voltage as a
`function of pressure for
`low frequency and high
`frequency RF power without a constant voltage
`gradient device;
`
`FIG. 15 illustrates breakdown voltage as a
`function of pressure with and without a constant
`voltage gradient device;
`FIG. 16 is a schematic cross-sectional repre-
`sentation of an integrated circuit which illustrates
`the arrival angles associated with the deposition of
`a layer of material such as dielectric onto a surface
`of stepped topography;
`FIGS. 17A and 17B are schematic cross-
`sections, similar to FIG. 16, which illustrate the
`effect of french width on planarization;
`FIGS. 18 and 19 are cross-sections of the
`
`in the
`surface topology of an integrated circuit,
`manner of FIG. 16, illustrating the conformal, planar
`qualities of oxide films resulting from the applica-
`tion of our planarization process; and
`FIGS. 20 and 21 depict the deposition rate
`as a function of temperature and pressure, respec-
`tively, for our present oxide deposition process.
`
`Detailed Description gf E Invention
`
`I. CVD/PECVD Reactor
`
`A. Overview gt CVD/PECVD Reactor
`
`FIGS. 1 and 2 are, respectively, a top plan view
`of the preferred embodiment of the single wafer,
`reactor 10 of our present invention, shown with the
`cover pivoted open, and a vertical cross-section of
`the reactor 10.
`
`Referring primarily to these two figures and to
`others indicated parenthetically, the reactor system
`10
`comprises
`a housing
`12
`(also termed a
`"chamber"),
`typically made of aluminum, which
`defines an inner vacuum chamber 13 that has a
`
`plasma processing region 14 (FIG. 6). The reactor
`system 10 also includes a wafer-holding susceptor
`16 and a unique wafer transport system 18 (FIG.
`1)
`that
`includes vertically movable wafer support
`fingers 20 and susceptor support fingers 22. These
`fingers cooperate with an external robotic blade 24
`(FIG. 1) for introducing wafers 15 into the process
`region or chamber 14 and depositing the wafers 15
`on the susceptor 16 for processing, then removing
`the wafers 15 from the susceptor 16 and the cham-
`ber 12. The reactor system 10 further comprises a
`process/purge gas manifold or "box" 26 that ap-
`plies process gas and purging gas to the chamber
`13, an RF power supply and matching network 28
`for creating and sustaining a process plasma from
`the inlet gas and a lamp heating system 30 for
`heating the susceptor 16 and wafer 15 positioned
`on the susceptor to effect deposition onto the wa-
`fer. Preferably. high frequency RF power of 13.56
`MHz is used, but low frequencies can be used.
`The gas manifold 26 is part of a unique pro-
`
`Page 6 of 32
`
`

`
`0272140
`
`10
`
`cess and purge gas distribution system 32 (FIGS. 2
`and 10) that is designed to flow the process gas
`evenly radially outwardly across the wafer 15 to
`promote even deposition across the wafer and to
`purge the spent gas and entrained products radi-
`ally outwardly from the edge of the wafer 15 at
`both the top and bottom thereof to substantially
`eliminate deposition on (and within) the gas mani-
`fold or box 26 and the chamber 12.
`
`A liquid cooling system 34 controls the tem-
`perature of
`the components of
`the chamber 12
`including,
`in particular, the temperature of the gas
`manifold or box 26. The temperature of the gas
`box components is selected to eliminate premature
`deposition within the gas box/manifold 26 upstream
`from the process chamber 14.
`The reactor system 10 includes a unique,
`RF/gas feed-through device 36 (FIGS. 2 and 12)
`that supplies process and purge gas to the RF-
`driven gas manifold 26 from an electrically ground
`supply. Applying the RF energy to the gas box or
`manifold 26 has the advantage of the wafer resid-
`ing on the grounded counter electrode or susceptor
`16, which makes possible a high degree of plasma
`confinement that would not be achievable if the RF
`
`energy were applied to the water and the gas box
`were grounded. Additionally, the hardware is me-
`chanically and electrically simpler since electrical
`isolation between wafer/susceptor and chamber is
`not required (or permitted). Temperature measure-
`ment and control of
`the susceptor/wafer
`in the
`presence of high frequency electric and magnetic
`fields is greatly simplified with the susceptor 16
`grounded. Also, the feed-through 36 is rigid. elimi-
`nating flexible gas connections and the purge gas
`flow path safely carries any leaking process gas
`into the chamber to the chamber exhaust. The
`
`capability to apply RF power to the gas manifold is
`made possible (despite the inherent tendency of
`high potential RF operation to form a deposition
`plasma within the feed-through) by the unique de-
`sign of the feed-through, which drops the RF po-
`tential evenly along the length of the feed-through,
`thus preventing a plasma discharge within.
`
`B. Wafer Transport System Q
`
`system is designed to
`this
`As mentioned.
`transfer individual wafers 15 between the external
`
`blade, FIG. 2, and the susceptor 16 and to position
`the susceptor 16 and wafer 15 for processing.
`Referring further
`to FIG. 1,
`the wafer transport
`system 18 comprises a plurality of radially-extend-
`ing wafer-support fingers 20 which are aligned with
`and spaced about the periphery of susceptor 16
`and are mounted to a semi-circular mounting bar or
`bracket 38. Similarly, an array of radially-extending
`
`susceptor-support fingers 22 are spaced circum-
`ferentially about
`the susceptor 16,
`interdigitated
`with the wafer support fingers 20. and are mounted
`to a semi-circular bar 40 positioned just outside bar
`38. The arcuate mounting bars 38 and 40 are
`mounted within a generally semi-circular groove 42
`formed in the housing, and are actuated respec-
`tively, by vertically movable elevator assemblies 44
`and 46.
`
`the susceptor elevator
`As shown in FIG. 3,
`mechanism 44 includes a vertically movable shaft
`48 that mounts the bar 38 at the upper end thereof.
`The shaft can be moved vertically up and down by
`various moving means 56,
`including a pneumatic
`cylinder, or, preferably, a stepper motor operating
`via suitable gear drive. Wafer elevator mechanism
`46 is similar to the elevator 44.
`
`The operation of the wafer transport system 18
`summarized
`by
`the
`sequence depicted
`-
`is
`schematically in FIGS. 4-8.
`In FlG. 4, the external
`blade 24 (with the wafer 15 to be processed sup-
`ported thereon)
`is
`inserted via opening 56 into
`chamber 13 to a position over the susceptor 16.
`One example of a suitable blade 24 and associated
`robot wafer handling system (and door 25, FIG. 6)
`is described in European patent application No.
`(31501000/EA2799),-entitled "Multiple Chamber In-
`tegrated Process System",
`which application is hereby incorporated by
`reference in its entirety. In this starting position, the
`wafer
`fingers 20-20 are positioned between the
`susceptor 16 and the blade 24.
`Next as shown in FIG. 5, the wafer elevator mecha-
`nism 44 raises the wafer-support
`fingers 20-20
`above the blade 24 to pick up the wafer 15. The
`blade 24 is then withdrawn from the chamber 13.
`As shown in FIG. 6, after retraction of the blade
`24. a pneumatic cylinder closes door 25 over the
`blade access slot 56 to seal chamber 13. The
`
`susceptor elevator mechanism 46 is actuated to
`raise the susceptor-support fingers 22 and suscep-
`tor 16 so that the susceptor 16 lifts the wafer 15
`from the fingers 20-20 into position for processing
`in the area 14 immediately adjacent the gas dis-
`tribution manifold 26. The spacing, d. between the
`wafer 15 and manifold 26 is readily selected by
`adjusting the travel of the elevator 46. At the same
`time. the susceptor fingers 22 and elevator mount-
`ing 46 maintains the horizontal orientation of the
`susceptor 16 and wafer 15 and parallelism between
`the wafer 15 and manifold 26 independent of the
`spacing, d.
`the
`After processing, and referring to FIG. 7,
`the
`susceptor
`elevator mechanism 46
`lowers
`susceptor fingers 22 and the susceptor 16 to de-
`posit the wafer 15 on the wafer support fingers 20-
`20. The door 25 is then opened and blade 24 is
`again inserted into the chamber 13. Next. as shown
`
`Page 7 of 32
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`in FIG. 8, elevator mechanism 44 lowers the wafer-
`support fingers 20-20 to deposit the wafer 15 on
`the blade 24. After the downwardly moving fingers
`20-20 clear the blade‘ 24,
`the blade is retracted.
`leaving the fingers 20 and 22 in the position shown
`in FlG. 4 preparatory to another wafer insertion,
`processing and withdrawal cycle.
`
`0. Near-IR Radiant Heating System Q
`
`The radiant heating system shown in FIGS. 2
`and 9 provides a reliable, efficient and inexpensive
`means for heating the circular susceptor 16 and
`wafer 15 (e.g., silicon) in a manner that provides
`uniform water temperature. accurate absolute water
`temperature and rapid thermal
`response at
`low
`temperatures, preferably S 600°C.
`in achieving
`these objectives. a number of requirements must
`be met. First, achieving uniform wafer temperature
`requires compensating the radiation losses at the
`edge of the wafer. Secondly, high efficiency at low
`water temperatures (5 600°C) requires a high em-
`issivity, high thermal conductivity susceptor 16 be-
`cause silicon wafers have low emissivity at
`low
`temperatures in the near-infrared spectrum.
`In ad-
`dition, near-infrared radiation is used to obtain fast
`heating response and for transmission through the
`inexpensive materials such as quartz window 70.
`The circular thin susceptor 16 is low thermal ca-
`pacitance for fast heating and cooling response.
`These and other objectives discussed below are
`achieved by the radiation heating system 30 shown
`in FIGS. 2 and 9.
`
`The heating system 30 preferably comprises
`an annular array of small. inexpensive, single-end-
`ed vertlcally oriented lamps 58-58 which provide
`radiation in the near-infrared portion of the elec-
`tromagnetic spectrum. The lamps 58-58 are moun-
`ted within an annular circular reflector module 60.
`
`preferably of aluminum. The module base 60 is
`formed from a block of aluminum, and has a pol-
`ished annular
`reflecting channel 62 machined
`therein. The channel 62 has an arcuate. generally
`semi-circular reflecting base 64. The module 60
`and lamps 58-58 are cooled by an annular cooling
`passage 66 that is formed within the collimatlng
`annular reflector 62. Connections are provided for
`the inlet and outlet of cooling liquid which,
`typi-
`cally,
`is chilled water from a pressurized supply.
`Power
`is supplied to the lamp sockets 63 and
`associated lamps 58 by an electrical supply cable
`68,
`typically from a variable power supply which
`automatically varies the lamp power based upon a
`predetermined program setting that is adapted to
`the requirements of the particular deposition pro-
`cess.
`
`The annularly-collimated light from the vertical
`
`oriented lamps 58-58 is admitted into the chamber
`via a quartz’ window 70. Quartz is transparent to
`near-lFl radiation. The transparent quartz window
`70 is mounted to the housing 13 at the bottom of
`
`the process chamber 13 using annular seals 72-72
`to provide a vacuum-tight
`interface between the
`window 70 and the housing. This mounting ar-
`rangement positions the radiant energy heating
`source 30 outside the chamber 13 at atmospheric
`pressure and isolates the vacuum of the processing
`chamber and the particulate-sensitive processing
`therein from the lamps. A bracket 74 can be joined
`to the lamp mounting base 60 and pivotally moun-
`ted by pivot pin 76 to a mating bracket 78, which is
`joined to the housing 12. (Alternatively, the lamp
`module can be bolted in place). As a consequence
`of this pivotal mounting of the lamp assembly 30
`external to and isolated from the process chamber
`13,
`the lamp assembly is readily accessible for
`maintenance,
`lamp replacement, etc., by simply
`disengaging a clamp 79 to allow the assembly to
`pivot downwardly about pin 76.
`As mentioned,
`the lamps 58-58 are small
`single-ended
`commercially
`available
`quartz-
`tungsten-halogen lamps which provide the required
`near-infrared radiation. One suitable lamp is the
`Ansi type "FEL" supplied by Sylvania, G.E., Ushio
`or Phillips. Presently,
`fourteen 0.5 to 1 kilowatt
`quartz-tungsten-halogen
`lamps
`that
`provide
`a
`wavelength of about 0.9 to 1.5 micron provide an
`annularly-collimated power density of up to about
`94 W/cm2 at
`the top of
`the lamp module. The
`maximum power
`density
`at
`the
`susceptor
`(substantially directed to the outer ~ 1.5 in. radius
`of a 6 in. diameter susceptor) is ~ 17 W/cm? taking
`all efficiency into account (~ 15-16% efficiency).
`More generally, lamps concentrating their radiation
`in the range of about 0.7 to 2.5 microns wavelength
`would be particularly useful. The aluminum base 60
`and concave-bottom, annular groove 62 provide a
`high collect