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`Paper No.
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`_____________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_____________________
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`CISCO SYSTEMS, INC.,
`Petitioner
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`v.
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`TQ DELTA LLC,
`Patent Owner
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`_____________________
`
`
`Case IPR2016-01466
`Patent No. 8,611,404
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`_____________________
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`PETITIONER’S REPLY
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`1
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`TABLE OF CONTENTS
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`I. 
`
`II. 
`
`Introduction ...................................................................................................... 5 
`
`Claim Construction .......................................................................................... 5 
`
`A. 
`
`B. 
`
`Petitioner’s construction of “synchronization signal” is
`the broadest reasonable interpretation. .................................................. 5 
`
`No construction is needed for “parameters associated
`with the full power mode operation.” ................................................... 7 
`
`the ANSI
`III.  The combination of Bowie, Yamano, and
`specification renders the claims obvious. ........................................................ 8 
`
`A. 
`
`The combination of Bowie and the ANSI specification
`renders obvious “store, in the low power mode, at least
`one parameter associated with the full power mode
`operation wherein the at least one parameter comprises
`at least one of a fine gain parameter and a bit allocation
`parameter.” ............................................................................................ 8 
`
`1. 
`
`2. 
`
`3. 
`
`Bowie’s loop characteristics include more than just
`attributes of the wire loop. .......................................................... 9 
`
`the ANSI
`The combination of Bowie and
`specification teaches storing loop transmission
`characteristics that include bit allocation and fine
`gain parameters. ........................................................................ 10 
`
`the ANSI
`teachings of Bowie and
`The
`specification do not undermine a determination
`that it would be obvious to combine them. ............................... 12 
`
`B. 
`
`C. 
`
`The combination of Bowie and the ANSI specification
`renders obvious “exit[ing] from the low power mode …
`without needing to reinitialize the transceiver.” ................................. 13 
`
`The combination of Bowie and the ANSI specification
`renders obvious “receive/transmitting, in full power
`mode, a synchronization signal.” ........................................................ 14 
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`2
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`D. 
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`The combination of Bowie, Yamano, and the ANSI
`specification renders obvious “transmit/receiving, in low
`power mode, a synchronization signal.” ............................................. 15 
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`1. 
`
`2. 
`
`3. 
`
`4. 
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`Yamano’s timing signal is a synchronization signal
`under the Board’s construction. ................................................ 16 
`
`Yamano’s timing signal is a synchronization signal
`under the Petitioner’s construction. .......................................... 16 
`
`Yamano’s timing signal is a synchronization signal
`under Patent Owner’s new construction. .................................. 17 
`
`Yamano’s timing signal is received in the low
`power mode. .............................................................................. 19 
`
`IV.  A POSITA would have combined Bowie, Yamano, and the
`ANSI specification. ........................................................................................ 21 
`
`A. 
`
`B. 
`
`C. 
`
`D. 
`
`E. 
`
`Bowie and the ’404 Patent teach similar systems and
`methods. .............................................................................................. 21 
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`A POSITA would have modified Bowie to transmit or
`receive a synchronization signal in low power mode. ........................ 22 
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`Yamano’s burst mode protocol is compatible with the
`ADSL standard. ................................................................................... 24 
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`The obviousness analysis in the Petition is based on the
`teachings in the prior art, not hindsight. .............................................. 26 
`
`The reasons for combing Bowie, Yamano, and the ANSI
`specification are consistent with the understanding of a
`POSITA. .............................................................................................. 27 
`
`V. 
`
`Patent Owner’s attack on Dr. Kiaei’s testimony is baseless. ........................ 28 
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`VI.  Conclusion ..................................................................................................... 30 
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`VII.  Certificate of Word Count ............................................................................. 31 
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`3
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`Ex. 1001
`Ex. 1002
`Ex. 1003
`Ex. 1004
`Ex. 1005
`Ex. 1006
`Ex. 1007
`Ex. 1008
`Ex. 1009
`Ex. 1010
`Ex. 1011
`Ex. 1012
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`Ex. 1013
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`Ex. 1014
`Ex. 1015
`Ex. 1016
`Ex. 1017
`Ex. 1018
`Ex. 1019
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`Ex. 1020
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`Ex. 1021
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`PETITIONER’S UPDATED EXHIBIT LIST
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`August 23, 2017
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`U.S. Patent No. 8,611,404 to Greszczuk et al.
`Prosecution File History of U.S. Patent No. 8,611,404
`Declaration of Sayfe Kiaei under 37 C.F.R. § 1.68
`Curriculum Vitae of Dr. Sayfe Kiaei
`U.S. Patent No. 5,956,323 to Bowie
`U.S. Patent No. 6,075,814 to Yamano et al.
`ANSI T1.413-1995
`Declaration of David Bader
`U.S. Patent No. 6,084,881 to Fosmark et al.
`Declaration of Dr. Chrissan in IPR2016-01160
`Deposition Transcript of Dr. Chrissan
`Second Declaration of Dr. Sayfe Kiaei
`Standard Dictionary of Computer and Information Processing
`(1977)
`Reserved
`Reserved
`Reserved
`Reserved
`Reserved
`District Court Claim Construction Order
`Tina Rathbone, MORE MODEMS FOR DUMMIES (1996) (selected
`pages)
`Copyright registration for Ex.1020
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`4
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`
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`Introduction
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`I.
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`Patent Owner argues that the combination set forth in the Petition does not
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`teach: (1) storing fine gain and bit allocation parameters in low power mode; (2)
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`exiting low power mode without the need for retraining; (3) transmitting/receiving
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`a synchronization signal in full power mode; and (4) transmitting/receiving a
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`synchronization signal in the low power mode. Patent Owner also argues that there
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`is no motivation to combine Bowie, Yamano, and the ANSI specification. These
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`arguments rely on narrow claim constructions and a mischaracterization of the
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`references. As shown below, Patent Owner’s arguments do not refute the
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`obviousness of the challenged claims.
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`II. Claim Construction
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`A.
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`Petitioner’s construction of “synchronization signal” is the
`broadest reasonable interpretation.
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`Petitioner, Patent Owner, and the Board each propose distinct constructions
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`for this term. The Board’s construction is “a signal allowing frame synchronization
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`between the transmitter of the signal and the receiver of the signal.” Institution
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`Decision, 6. Patent Owner argues that this construction is incorrect because it
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`“seems to implicate the wrong kind of synchronization.” Response, 18. Petitioner
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`agrees that by referring to only frame synchronization, the Board’s construction
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`incorrectly limits “synchronization signal” to just frame synchronization.
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`There is no dispute that the ’404 patent describes both frame synchronization
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`5
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`and timing synchronization. See id., 18-19; Ex.1012, ¶7. Frame synchronization is
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`performed in full power mode when a transceiver “receives … a plurality of
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`superframes” that comprise “a plurality of data frames followed by a
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`synchronization frame.” Ex.1001, 10:30-32. Frame synchronization also provides
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`for timing synchronization. Ex.1007, 62 (sections 6.9.1.2 & 6.9.3). Timing
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`synchronization, however, can be performed in either full power mode or low
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`power mode by reception of a “synchronization signal.” See Ex.1001, 10:33, 39-
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`40. Consequently, each “synchronization signal” in the claims must include timing
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`synchronization rather than just frame synchronization. Ex.1012, ¶7. Thus, the
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`Board’s construction is not the broadest reasonable interpretation.
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`Patent Owner proposes two constructions in this proceeding. Patent Owner
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`and its expert initially proposed “an indication used to establish or maintain a
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`timing relationship between transceivers.” Preliminary Response, 7; Ex.1010, ¶55.
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`The Response, however, proposes a new version with additional requirements
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`(underlined); “a signal used to maintain a timing relationship between transceivers
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`by correcting errors or differences between a timing reference of the transmitter of
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`the signal and a timing reference of the receiver of the signal.” Response, 17-18.
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`Patent Owner’s first construction is consistent with both Petitioner’s
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`construction (i.e., “a signal used to maintain timing between transceivers”
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`(Petition, 12)) and the construction adopted by the district court in the co-pending
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`6
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`litigation proceedings. Ex.1019, 4 (“signal used to establish or maintain a timing
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`relationship between transceivers”). Patent Owner’s second construction is not the
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`broadest reasonable interpretation. First, it was proposed specifically in response to
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`the analysis in Dr. Kiaei’s declaration. Ex.1011, 85:12-15 (“One reason that I
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`added clarifying language was because Dr. Kiaei utilized an example of an
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`asynchronous poll as a synchronization signal.”). Second, it relies on a dictionary
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`definition of a different term and fails to refer to anything in the specification. See
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`Response, 20; Ex.2008 (providing a definition for “synchronous transmission”).
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`Thus, a POSITA would not understand the term “synchronization signal” to
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`require “correcting errors or differences between” timing references of a
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`transmitter and receiver. Ex.1012, ¶4.
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`Accordingly, Petitioner’s proposed construction should be adopted because
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`it is the only construction supported by the specification and broad enough to
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`encompass both types of synchronization. See, e.g., Ex.1001, 5:41-45 (the signal
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`may be “a pure tone of fixed frequency and phase which is synchronized with the
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`Master Clock in the transmitter,” though “[o]ther forms of timing signal may, of
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`course, be used.”); Ex.1012, ¶5-6.
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`B. No construction is needed for “parameters associated with the full
`power mode operation.”
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`Patent Owner asserts that this term should be construed to mean a
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`7
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`“parameter associated with the transmission and/or reception of data during
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`normal operation.” Response, 21. Petitioner, however, believes that this term does
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`not require construction in this case because the claims provide sufficient meaning.
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`In particular, the claims recite “at least one parameter associated with the full
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`power mode operation wherein the at least one parameter comprises at least
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`one of a fine gain parameter and a bit allocation parameter.” Ex.1001, 10:35-
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`38, 10:64-67 (emphasis added). Patent Owner’s proposed construction only
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`focuses on the first part of the limitation but ignores the further limitations
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`regarding “a fine gain and a bit allocation parameter.” Thus, this term should be
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`construed in its entirety according to its plain and ordinary meaning to include bit
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`allocation and fine gain parameters.
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`III. The combination of Bowie, Yamano, and the ANSI specification renders
`the claims obvious.
`
`A. The combination of Bowie and the ANSI specification renders
`obvious “store, in the low power mode, at least one parameter
`associated with the full power mode operation wherein the at least
`one parameter comprises at least one of a fine gain parameter and a
`bit allocation parameter.”
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`Patent Owner argues that neither Bowie nor the ANSI specification renders
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`this limitation obvious and provides numerous reasons explaining why Bowie’s
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`loop transmission characteristics are not “parameters” that include fine gain and bit
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`allocation. See Response, 23. Each argument fails.
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`8
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`1.
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`Bowie’s loop characteristics include more than just
`attributes of the wire loop.
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`
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`Patent Owner argues that Bowie’s loop transmission characteristics “are
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`associated with physical attributes of the loop and which are independent of, and
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`exist without regard to, any operating mode, any protocol, or the transmission of
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`data.” Response, 23. Patent Owner also argues that Bowie’s “[l]oop characteristics
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`… are intrinsic attributes of a loop and include attenuation, background noise, loop
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`length, wire gauge, wire composition, resistance, inductance, capacitance, etc.” See
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`id., 26. Patent Owner misunderstands what Bowie’s transceiver actually stores in
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`low power mode.
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`Bowie teaches not just intrinsic attributes of the loop, but “loop
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`transmission characteristics.” See Ex.1005, 5:62-66. These loop transmission
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`characteristics include values such as loop loss characteristics and other
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`information determined through transceiver handshaking. Id., 4:64-5:5. This is
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`what Bowie stores in the low power mode. Id., 5:17-19 (“the COT unit 232
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`optionally stores in memory 117 characteristics of the loop 220 that were
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`determined by CPE to COT handshaking.”). In fact, a purpose of Bowie storing
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`these characteristics is “to enable data transmission to resume quickly by reducing
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`the time needed to determine loop transmission characteristics.” Id., 5:64-66
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`(emphasis added).
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`9
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`Patent Owner’s argument fails because it relies on the misunderstanding that
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`Bowie only stores “intrinsic attributes of a loop and include attenuation,
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`background noise, loop length, wire gauge, wire composition, resistance,
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`inductance, capacitance, etc.” See Response, 25-26. But, as shown above, Bowie
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`actually stores transmission characteristics that are “determined by CPE to COT
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`handshaking.” Ex.1005, 5:17-19, 5:64-66. These transmission characteristics are
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`not just the physical aspects of the wire loop, but are a “function of” the physical
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`aspects of the wire loop. Id., 5:1-3. Thus, this argument fails.
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`2.
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`The combination of Bowie and the ANSI specification
`teaches storing loop transmission characteristics that
`include bit allocation and fine gain parameters.
`
`Patent Owner argues that the combination of Bowie and the ANSI
`
`specification “misleadingly conflates loop characteristics with fine gain and bit
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`allocation parameters as if they were the same thing.” Response, 25-26. This is
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`merely an extension of Patent Owner’s flawed argument that Bowie’s loop
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`transmission characteristics are limited to “intrinsic attributes of a loop” that
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`cannot include “protocol specific transmission parameters that are determined
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`based on a number of criteria, including loop characteristics.” Id., 26.
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`The Petition, however, showed that the combination of Bowie and the ANSI
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`specification renders obvious storing fine gain and bit allocation parameters.
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`Petition, 39-41. As discussed above, Bowie teaches storing loop transmission
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`10
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`characteristics determined from handshaking. Ex.1005, 5:17-19. A POSITA would
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`understand these transmission characteristics to include fine gain and bit allocation
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`parameters, as discussed in the ANSI specification. See Petition, 39-41; Ex.1007,
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`p.103 (“Specifically, each receiver communicates to its far-end transmitter the
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`number of bits and relative power levels to be used on each DMT sub-carrier
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`….”). Patent Owner and Dr. Chrissan agree that derived transmission
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`characteristics would include bit allocation and fine gain parameters. See
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`Response, 26 (“… fine gain and bit allocation parameters are not attributes of the
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`loop but rather are protocol specific transmission parameters that are determined
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`based on a number of criteria, including loop characteristics ….”); see also
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`Ex.1011, 61:11-62:2 (“[P]art of establishing the communication between two
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`modems is determining bits and gains.”).
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`Further, contrary to Patent Owner’s assertions, Dr. Kiaei has consistently
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`established that it would have been obvious for Bowie’s loop transmission
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`characteristics to include bit allocation and fine gain parameters. See Ex.1003,
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`p.51-54; Ex.2004, 23:21-26:20. Patent Owner attempts to manufacture a conflict
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`between Dr. Kiaei’s declaration and deposition (see Response, 29-30) that does not
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`exist because it is entirely based on Patent Owner’s own misunderstanding of
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`Bowie.
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`11
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`3.
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`The teachings of Bowie and the ANSI specification do not
`undermine a determination that it would be obvious to
`combine them.
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`
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`Patent Owner argues that “it would not make sense to use stored bit
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`allocation or fine gain parameters with the Bowie unit in view of the teachings of
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`the 1995 ADSL Standard.” Id., 31-32. Patent Owner also argues that “storing bit
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`allocation or fine gain parameters in the Bowie device … would have been of no
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`value because those parameters would have to be re-calculated as well when the
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`unit comes out of low power mode.” Id., 33. These arguments fail for the same
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`reasons discussed above—Patent Owner’s mistaken belief about Bowie.
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`First, Bowie teaches that when entering low power mode, “the COT unit 232
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`optionally stores in memory 117 characteristics of the loop 220 that were
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`determined by CPE to COT handshaking.” Ex.1005 at 5:17-19. These
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`characteristics determined through handshaking include bit allocation and fine gain
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`parameters. Ex.1007, p.103 (“Specifically, each receiver communicates to its far-
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`end transmitter the number of bits and relative power levels to be used on
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`each DMT sub-carrier ….”). “Upon receipt of the resume signal,” the transceiver
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`returns to full power mode. Id., 5:60-62. “If loop transmission characteristics had
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`been stored, these parameters are retrieved from memory 117 and used to enable
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`data transmission to resume quickly by reducing the time needed to determine
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`loop transmission characteristics.” Ex.1005 at 5:62-67 (emphasis added).
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`12
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`Recalculating these transmission characteristics is only needed when “loop
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`
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`characteristics have changed due, for example, to temperature-dependent
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`changes in loop resistance.” Id., 6:39-40 (emphasis added). Even then, Dr.
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`Chrissan confirmed that transmission parameters may not even change when loop
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`parameters change. Ex.1011, 26:20-23.
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`The ‘404 patent contemplates the same thing: “[o]n resuming
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`communication,” the transceiver “verif[ies] that system conditions have not
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`changed so significantly as to require renewed initialization.” Ex.1001, 8:24-29.
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`Thus, Bowie and the ’404 patent are similar in that neither requires retraining since
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`the stored loop transmission characteristics/parameters provide for returning to
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`normal operation without needing to reinitialize.
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`Second, the portions of Dr. Kiaei’s deposition that Patent Owner relies on
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`(see Response, 31) discuss initial training of the transceiver, not retraining as
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`Patent Owner alleges. See Ex.2004, 52:24–53:12. In fact, nowhere does Dr. Kiaei
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`take the position that retraining is required when Bowie returns from its low power
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`mode. Thus, this argument fails.
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`B.
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`The combination of Bowie and the ANSI specification renders
`obvious “exit[ing] from the low power mode … without needing to
`reinitialize the transceiver.”
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`Patent Owner argues that the combination of Bowie and the ANSI
`
`specification fails to render this limitation obvious. Response, 34. As discussed
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`13
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
`
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`above, however, Patent Owner’s reading of Bowie is simply incorrect as Bowie
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`
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`explicitly states that retraining is only needed when loop transmission
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`characteristics change: “Hand-shaking information may be required where, for
`
`example, loop characteristics have changed due, for example, to temperature-
`
`dependent changes in loop resistance.” Ex.1005, 6:37-40. And even then,
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`transmission parameters may not change when loop parameters change. Ex.1011,
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`26:20-23.
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`Patent Owner also argues that even if the combination “teaches that loop
`
`characteristics and fine gain and bit allocation parameters are not re-determined
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`upon coming out of low power mode, Bowie still does not teach exiting the low
`
`power mode without needing to reinitialize.” Response, 36. For this, Patent Owner
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`relies on “the ADSL initialization process” that “includes several other additional
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`steps besides determining loop characteristics and fine gain and bit allocation
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`parameters.” See id. This argument is nothing more than a straw man. In fact, the
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`’404 Patent, as discussed above, that contemplates reinitialization in similar
`
`situations, also fails to list these other additional steps that Patent Owner deems to
`
`be missing from Bowie. See Ex.1001, 8:24-35.
`
`C. The combination of Bowie and the ANSI specification renders
`obvious “receive/transmitting, in full power mode, a
`synchronization signal.”
`
`Patent Owner argues that “[t]he Petition does not explain how or why the
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`14
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`

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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
`
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`ANSI T1.413 synchronization symbol qualifies as the ‘synchronization signal.’”
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`
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`Response, 37. The Petition, though, establishes that a POSITA would understand
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`that a synchronization symbol in the ANSI specification is a type of
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`synchronization signal because it is used to maintain timing synchronization with a
`
`remote transceiver. See Petition, 34-36. Specifically, the Petition and Dr. Kiaei’s
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`declaration refer to sections 6.9.1.2 and 6.9.3 of the ANSI specification which
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`show that a “pilot allows resolution of sample timing in a receiver” and a
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`synchronization symbol “permits recovery of the frame boundary after micro-
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`interruptions that might otherwise force retraining” by “correction of [] timing
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`errors.” Ex.1007, 62; Ex. 1003, p.46-49. Thus, a POSITA would understand the
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`synchronization symbol to be a synchronization signal because it maintains a
`
`timing synchronization with a remote transceiver. See Ex.1003, p.48-49.
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`D. The combination of Bowie, Yamano, and the ANSI specification
`renders obvious “transmit/receiving, in low power mode, a
`synchronization signal.”
`
`Patent Owner argues that “Yamano’s periodic poll or timing signal is not the
`
`claimed synchronization signal” under any of the claim constructions in this case.
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`See Response, 39-43. Patent Owner also argues that based on an archaic definition
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`of the term “poll,” the timing signal disclosed in Yamano is not received in a low
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`power mode. See id., 39, 45-47. These arguments fail as discussed below.
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`15
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`
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`1.
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
`
`Yamano’s timing signal is a synchronization signal under
`the Board’s construction.
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`
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`Yamano’s timing signal is a synchronization signal under the Board’s
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`construction of “a signal allowing frame synchronization between the transmitter
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`of the signal and the receiver of the signal.” See Institution Decision, 6, 13-14.
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`Yamano’s timing signal is used to “maintain synchronization of [] time intervals
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`between” receiver and transmitter circuits. Ex.1006, 15:29-32. Maintaining
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`synchronization of the transmitter and receiver via this timing signal allows
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`Yamano’s non-idle detector to wake periodically to detect a pure tone that “can be
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`used to signal the presence of packet data” or, in other words, the beginning of a
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`superframe boundary. Ex.1006, 14:20-23; Ex.1012, ¶18. Because Yamano’s timing
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`signal is used in this way, it satisfies the “synchronization signal” under the
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`Board’s construction. Ex.1012, ¶18.
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`2.
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`Yamano’s timing signal is a synchronization signal under
`the Petitioner’s construction.
`
`Yamano’s timing signal is a synchronization signal under both Petitioner’s
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`construction (“a signal used to maintain timing between transceivers”) and Patent
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`Owner’s first construction (“a signal or indication used to establish or maintain a
`
`timing relationship between transceivers”) because it is “used to maintain
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`synchronization of [] time intervals” between receiver and transmitter circuits. See
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`Petition, 42-43; Ex.1003, p.56-57; Ex.1006, 15:29-32. This is undisputed.
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`3.
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
`
`Yamano’s timing signal is a synchronization signal under
`Patent Owner’s new construction.
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`
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`Yamano’s timing signal is a synchronization signal even under Patent
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`Owner’s new, overly narrow construction (“a signal used to maintain a timing
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`relationship between transceivers by correcting errors or differences between a
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`timing reference of the transmitter of the signal and a timing reference of the
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`receiver of the signal”). Again, as previously stated, Yamano’s timing signal is
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`“used to maintain synchronization of [] time intervals” between receiver and
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`transmitter circuits. Ex.1006, 15:29-32. And, as shown in the ANSI specification, a
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`purpose of maintaining synchronization is to correct errors or differences that may
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`periodically exist between transceivers. Ex.1007, 62 (section 6.9.1.2). Thus, even if
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`the claims are construed to incorporate Patent Owner’s extra limitations, Yamano’s
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`timing signal satisfies these limitations in that it maintains synchronization to avoid
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`re-initialization. Ex.1012, ¶17.
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`Patent Owner argues that Yamano does not teach a synchronization signal
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`because its timing signal is not described as “lock[ing] the timing reference of the
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`near end receiver with the far end transmitter and/or ‘correct[ing] timing errors that
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`occur while communicating with other ADSL units in order to alleviate the need to
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`retrain [] when timing errors occurs.’” Response, 40-41. This argument, however,
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`reads-in further limitations that are not present in the claims or even Patent
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`Owner’s proposed claim construction. There is no requirement in either to “lock”
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`the timing references of the transceivers or to alleviate the need to retrain.
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`Patent Owner’s argument is really an attempt to import limitations into the
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`claims, which is impermissible. Liebel-Flarsheim Co. v. Medrad, Inc., 358 F. 3d
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`898, 913 (Fed. Cir. 2004) (“it is improper to read limitations from a preferred
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`embodiment described in the specification—even if it is the only embodiment
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`….”); Phillips v. AWH Corp., 415 F. 3d 1303, 1323 (Fed. Cir. 2005) (there exists a
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`“danger of reading limitations from the specification into the claims”).
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`Patent Owner also argues that Yamano’s transceiver “establishes
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`synchronization with the far end transceiver only at the start of the reception of the
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`data packet, and this occurs only when the transceiver is already in … full power
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`mode.” Response, 41. Patent Owner then concludes that “Yamano’s teaching that
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`synchronization is established in full power mode necessarily teaches that
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`synchronization is not maintained in the low power mode.” Id., 42. This non
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`sequitur argument is simply untrue.
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`As discussed above, Yamano’s timing signal is expressly taught to maintain
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`synchronization between transmitting and receiving circuits when the receiver is
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`operating in a low power mode. Ex.1006, 15:29-32. The fact that Yamano teaches
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`using a synchronization signal in full power mode in addition to the
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`synchronization signal used in low power mode is consistent with the express
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`claim language. For example, claim 6 recites “receive, in the full power mode, a
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`synchronization signal” and “receive, in the low power mode, a synchronization
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`signal.” As clearly shown, both limitations recite “a synchronization signal.” In
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`other words, the claims do not require the same synchronization signal to be used
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`in both full and low power modes. Patent Owner’s expert agrees. Ex.1011, 74:2-3
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`(“The literal claim language does not require the two signals to be identical.”).
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`Accordingly, Yamano’s use of different synchronization signals in full and low
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`power modes is consistent with the claims.
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`4.
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`Yamano’s timing signal is received in the low power mode.
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`Patent Owner argues that Yamano’s “periodic poll or timing signal is not
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`received by the transceiver in a low power mode.” Response, 45-46. This argument
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`ignores Yamano’s “timing signal” embodiment and is based on the fallacy that the
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`word “poll” means “to request a station to send data.” Id., 46; Ex.2007, 221. Patent
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`Owner found this definition from a dictionary published 30 years prior to the ’404
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`Patent (see Ex.2007 (copyright 1969)) that was located through a search for a
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`dictionary to fit Dr. Chrissan’s purposes. Ex.1011, 97:18-98:1 (“I asked for a
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`search of dictionary definitions…. This one satisfied my interpretation of a poll.”).
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`But another version of the same dictionary published 8 years later offers a
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`more contemporary definition that includes Dr. Kiaei’s understanding that “poll”
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`includes monitoring other transceivers. Ex.1013 at 262 (“to periodically interrogate
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`a device to determine if an interaction is required between the device doing the
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`polling and the device that is being polled.”). Thus, when using the proper
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`definition, Yamano’s poll can be “received,” contrary to Patent Owner’s argument.
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`Patent Owner also relies on the assumption that “no functional blocks in
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`[Yamano’s] receiver [are] capable of receiving a periodic poll or other timing
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`signal” while Yamano is operating in its low power mode. Response, 46. To
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`support this, Patent Owner references Ex.2002 from Dr. Kiaei’s deposition (Fig. 4
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`of Yamano) showing the components of Yamano’s receiver that are powered down
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`in the low power mode:
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`20
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`Id., 47; Ex.2002. What Patent Owner misses from this figure is that Yamano’s non-
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`idle detector 401 is periodically enabled in low power mode to detect a timing
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`signal while the other components remain inactive. Ex.1006, 15:26-29 (“receiver
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`circuit 400 can periodically enable the non-idle detector 401”). Thus, a POSITA
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`would understand that Yamano’s receiver can in fact receive a timing signal to
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`maintain synchronization in low power mode. Ex.1012, ¶20.
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`IV. A POSITA would have combined Bowie, Yamano, and the ANSI
`specification.
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`Patent Owner argues that a POSITA would not have combined the teachings
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`of Bowie, Yamano, and the ANSI specification. See Response, 48-61. All of the
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`arguments are discussed below and fail as they rely on a misunderstanding of the
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`prior art, improper bodily incorporation of the teachings in the references, and/or
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`improperly arguing the references individually.
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`A. Bowie and the ’404 Patent teach similar systems and methods.
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`Patent Owner argues that a POSITA would not have combined Bowie with
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`Yamano and the ANSI specification since “Bowie and the 404 patent follow
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`fundamentally different—and mutually exclusive—paths to going back to
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`transmitting data in a DSL system after coming out of a low power mode.” Id., 49.
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`This argument is based on the previously discussed misunderstanding that Bowie
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`“teaches using stored loop characteristics as part of re-determining the loop
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`characteristics and engaging in ‘additional handshaking’ upon coming out of a low
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`Petitioner’s Reply
`IPR2016-01466 (Patent No. 8,611,404)
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`power mode and before resuming transmission of user data.” Id.
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`First, it is nonsense to argue that Bowie stores loop characteristics in order
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`to re-determine them when coming out of low power mode. Second, Bowie states
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`that handshaking is optional and is only required when parameters have changed
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`enough to necessitate reinitialization. Ex.1005, 6:36-40 (emphasis added) (“Hand
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`shaking information may be required where, for example, loop characteristics
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`have changed due, for example, to temperature-dependent ch