Filed on behalf of TQ Delta, LLC
`By: Peter J. McAndrews
`Thomas J. Wimbiscus
`Scott P. McBride
`Christopher M. Scharff
`McAndrews, Held & Malloy, Ltd.
`500 W. Madison St., 34th Floor
`Chicago, IL 60661
`Tel: 312-775-8000
`Fax: 312-775-8100
`E-mail: pmcandrews@mcandrews-ip.com
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`CISCO SYSTEMS, INC.
`Petitioner
`
`v.
`
`TQ DELTA, LLC
`Patent Owner
`_____________
`
`Case No. IPR2016-01466
`Patent No. 8,611,404
`_____________
`
`PATENT OWNER’S RESPONSE
`
`
`
`
`
`
`
`
`
`
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`TABLE OF CONTENTS
`
`
`
`
`I.
`
`INTRODUCTION ........................................................................................... 1
`
`II.
`
`SUMMARY OF ARGUMENT ....................................................................... 1
`
`III. OVERVIEW OF U.S. PATENT No. 8,611,404 ............................................. 3
`
`A. Background of the Technology .............................................................. 3
`
`B. The 404 Patent ........................................................................................ 6
`
`IV. OVERVIEW OF THE CITED REFERENCES .............................................. 7
`
`A. Bowie ...................................................................................................... 8
`
`B. Yamano ................................................................................................. 11
`
`C. The 1995 ADSL Standard .................................................................... 15
`
`V.
`
`LEVEL OF ORDINARY SKILL IN THE ART ........................................... 17
`
`VI. CLAIM CONSTRUCTION .......................................................................... 17
`
`A.
`
`“Synchronization Signal” ..................................................................... 17
`
`B.
`
`“Parameter Associated with the Full Power Mode Operation” ............ 21
`
`VII. PETITIONER HAS FAILED TO SHOW THAT THE REFERENCES
`ALONE OR
`IN COMBINATION DISCLOSE ALL THE
`ELEMENTS OF THE CLAIMS ................................................................... 22
`
`A. Petitioner Has Failed To Establish That Bowie Discloses
`Storing, In A Low Power Mode, A “Parameter Associated With
`the Full Power Mode Operation” ........................................................ 23
`
`B.
`
`Petitioner Fails To Establish That “Storing, In the Low Power
`Mode . . . At Least One of a Fine Gain Parameter and a Bit
`Allocation Parameter” Would Have Been Obvious Over Bowie
`and the 1995 ADSL Standard .............................................................. 24
`
`
`
`i
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`1.
`
`2.
`
`Bowie’s Loop Characteristics Are Not the Claimed Fine
`Gain and Bit Allocation Parameters ......................................... 25
`
`
`
`The Teachings of the Cited Art Undermine Petitioner’s
`Reasons for Modifying Bowie to Store Bit Allocation or
`Fine Gain Parameters in a Low Power Mode ........................... 31
`
`C. Bowie Does Not Disclose Exiting the Low Power Mode without
`Needing To Reinitialize the Transceiver ............................................. 34
`
`D. The combination of Bowie and ANSI T1.413 does not teach
`“receive[transmit], in the full power mode, a synchronization
`signal” .................................................................................................. 37
`
`E. Yamano Does Not Disclose Transmitting or Receiving, in the
`Low Power Mode, a Synchronization Signal ...................................... 38
`
`1.
`
`2.
`
`3.
`
`Of
`Construction
`Owners’s
`Patent
`Under
`“Synchronization Signal,” Yamano Does Not Teach the
`Limitation .................................................................................. 39
`
`Under The Board’s Construction Of “Synchronization
`Signal,” Yamano Does Not Teach the Limitation .................... 43
`
`Yamano’s Periodic Poll Or Other Timing Signal is not
`Received By The Device In Low Power Mode ........................ 45
`
`VIII. A PERSON OF ORDINARY SKILL IN THE ART WOULD NOT
`HAVE BEEN MOTIVATED TO COMBINE THE REFERENCES ........... 47
`
`A. Bowie Would Have Led A POSITA Away From the Inventions
`of the 404 Patent .................................................................................. 49
`
`B. A POSITA Would Not Have Modified Bowie to Transmit or
`Receive, In the Low Power Mode, a Synchronization Signal ............ 52
`
`C. Yamano’s Burst Mode Protocol is Incompatible with the ADSL
`Standard ............................................................................................... 54
`
`D. Petitioner’s Obviousness Analysis is Tainted by Impermissible
`Hindsight ............................................................................................. 58
`
`
`
`ii
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`E.
`
`Petitioner’s Proposed Reasons for Combining the Cited
`References Conflict with the Teachings of Those References ........... 59
`
`
`
`IX. DR. KIAEI’S TESTIMONY IS CONTRADICTORY, LACKS
`CREDIBILITY AND OBJECTIVE SUPPORT, AND SHOULD BE
`IGNORED BY THE BOARD ....................................................................... 61
`
`X.
`
`CONCLUSION .............................................................................................. 64
`
`iii
`
`
`
`
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`
`TABLE OF EXHIBITS
`
`
`Exhibit 2001 Exhibit from Deposition of Sayfe Kiaie (IPR2016-01466)
`(Annotated of Figure 4 of U.S. Pat. No. 6,075,814)
`Exhibit 2002 Exhibit from Deposition of Sayfe Kiaie (IPR2016-01466)
`(Annotated of Figure 4 of U.S. Pat. No. 6,075,814)
`Exhibit 2003 Exhibit from Deposition of Sayfe Kiaie (IPR2016-01466)
`(Drawing)
`Exhibit 2004 Transcript of Deposition of Sayfe Kiaie (IPR2016-01466)
`Exhibit 2005 Declaration of Douglas A. Chrissan, Ph.D. for Inter Partes Review
`No. IPR2016-01466
`Exhibit 2006 Curriculum Vitae of Douglas A. Chrissan, Ph.D.
`Exhibit 2007 Standard Dictionary of Computers and Information Processing
`Exhibit 2008 Dictionary of Networking, 3rd Ed.
`
`iv
`
`
`
`
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`I.
`
`INTRODUCTION
`
`
`
`The Board instituted inter partes review of claims 6, 10, 11, 15, 16, and 20
`
`of U.S. Pat. No. 8,611,404 (“the 404 patent”) based on a single Ground—alleged
`
`obviousness over the combination of U.S. Patent No. 5,956,323 (“Bowie”), U.S.
`
`Patent No. 6,075,814 (“Yamano”), and the American National Standards Institute
`
`(ANSI) T1.413-1995 Standard (the “1995 ADSL Standard”). TQ Delta, LLC
`
`(“Patent Owner”) submits this Response under 37 CFR § 42.120.
`
`II.
`
`SUMMARY OF ARGUMENT
`
`For purposes of institution, the Board credited several unsupported factual
`
`statements by Petitioner and its expert that are incorrect and contradicted by the
`
`asserted references themselves. To carry its burden on the single ground of
`
`obviousness, Petitioner was required to provide evidence and particularized
`
`explanation showing that all the elements of the 404 claims are found in the cited
`
`references, and that a person of ordinary skill in the art (“POSITA”) would have
`
`been motivated to combine the prior art in the way claimed and would have had a
`
`reasonable expectation of success in doing so. See PersonalWeb Techs., LLC v.
`
`Apple, Inc., 848 F.3d 987, 991 (Fed. Cir. 2017). Petitioner has not done so.
`
`Specifically, Petitioner has not demonstrated that the combination of the
`
`cited references suggests or teaches “store[ing], in a low power mode, at least one
`
`parameter associated with the full power mode operation wherein the at least one
`
`
`
`1
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`parameter comprises at least one of a fine gain parameter and a bit allocation
`
`parameter,” “transmitting[/receiving], in the low power mode, a synchronization
`
`signal,” or “restor[ing] the full power mode . . . without needing to reinitialize the
`
`transceiver.” See, e.g., St. Jude Med., Inc. v. Access Closure, Inc., 729 F.3d 1369,
`
`1380-81 (Fed. Cir. 2013).
`
`Moreover, Petitioner’s obviousness analysis is legally deficient. In lieu of
`
`articulating the scope of the prior art, the differences between the claimed
`
`invention and the prior art, and the reasons why a person of ordinary skill in the art
`
`would have been motivated to combine the prior art in the way claimed and would
`
`have had a reasonable expectation of success in doing so, as required by Graham v.
`
`John Deere Co., 383 U.S. 1 (1966). Petitioner relies on hindsight, using the
`
`challenged claims as a template to cull teachings from the references to fit the
`
`parameters of
`
`the claimed
`
`inventions.
`
` As a result, Petitioner
`
`ignores
`
`incompatibilities between the prior art elements and, therefore, fails to provide “a
`
`plausible rationale as to why the prior art references would have worked together
`
`to render the [patent claims] obvious” under its proffered theory of obviousness.
`
`Power-One, Inc. v. Artesyn Techs., Inc., 599 F.3d 1343, 1351-522 (Fed. Cir. 2010).
`
`Because Petitioner has failed to carry both its burden of production and
`
`persuasion on the single ground of obviousness, Patent Owner respectfully requests
`
`that the Board issue a Final Written Decision upholding the patentability of claims
`
`
`
`2
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`6, 10, 11, 15, 16, and 20 of the 404 patent. See In re Magnum Oil Tools Int'l, Ltd.,
`
`829 F.3d 1364, 1375-76 (Fed. Cir. 2016).
`
`III. OVERVIEW OF U.S. PATENT NO. 8,611,404
`
`The 404 patent, entitled “Multicarrier Transmission System with Low Power
`
`Sleep Mode and Rapid-On Capability,” issued on December 17, 2013. The
`
`inventions of the 404 patent represented a significant improvement in the field of
`
`multicarrier transmission systems and multicarrier transceivers. In particular, the
`
`404 patent teaches a multicarrier transceiver that saves energy by operating in a
`
`low power mode, but that can go rapidly from the low power mode back to a full
`
`power mode without needing to reinitialize the transceiver. See Ex. 2005 at ¶ 15.
`
`A. Background of the Technology
`
`Multicarrier transmission systems provide high speed data links between
`
`communication points. See Ex. 1001 at 1:37-38. A digital subscriber loop
`
`(“DSL”) system is an exemplary multicarrier transmission system that is used to
`
`provide high-speed data communication over the same local subscriber loop that is
`
`used to provide telephone service to a subscriber. See id. at 1:38-41. In a DSL
`
`system, the overall communication bandwidth of the communication channel
`
`between the subscriber and the central office is divided into a number of separate
`
`sub-channels or carriers, e.g., 256 sub-channels. See id. at 1:48-55. A transceiver
`
`divides data to be transmitted into groups of bits, allocates each group of bits to a
`
`
`
`3
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`sub-channel, and modulates each group of bits onto its respective sub-channel. See
`
`id. at 1:63-66; Ex. 2005 at ¶¶ 16-19.
`
`Prior to exchanging data over the channel, the DSL transceivers first go
`
`through an initialization process. See Ex. 1001 at 3:7-9; Ex. 2005 at ¶ 20. The
`
`initialization process includes several distinct phases. The first phase involves
`
`synchronizing the timing references of the transceivers. The transceivers
`
`synchronize their timing by exchanging information to synchronize and “lock” the
`
`timing of their respective clocks. Ex. 2005 at ¶ 64. This is called “timing
`
`synchronization.” Id.
`
`After timing synchronization, the initialization process goes into its next
`
`phase during which the transceivers determine characteristics of the wire loop
`
`connecting the transceivers, i.e., loop characteristics. Attenuation is an example of
`
`a loop characteristic. Attenuation is the reduction in signal power a signal
`
`experiences as it travels across the wire from the originating transceiver to the
`
`destination
`
`transceiver.
`
` Attenuation
`
`is a function of different physical
`
`characteristics of the wire loop, such as the length, diameter, and composition.
`
`Loop background noise is another example of a loop characteristic. Id. at ¶ 65.
`
`Once the loop characteristics are determined, the initialization process
`
`continues with a sub-channel characterization and analysis phase. During this
`
`phase, the transceivers determine equalization settings and echo canceller settings
`
`
`
`4
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`and measure signal to noise ratios (“SNR”) on a sub-channel basis. SNR is a
`
`function of loop characteristics such as noise levels and attenuation. Id. at ¶ 66.
`
`In
`
`the
`
`last phase of
`
`initialization,
`
`the sub-channel characterization
`
`information is used to determine transmission parameters that are used for data
`
`transmission. See id.; Ex. 1001 at 3:10-20. Examples of transmission parameters
`
`include transmission and reception data rates, fine gain parameters, and bit
`
`allocation parameters. Transmission parameters are specific to and conform to the
`
`communication protocol used for data transmission. See Ex. 2005 at ¶ 94. The
`
`transceivers then go through the step of exchanging the transmission parameters.
`
`Id. at ¶ 66.
`
`When initialization is finished, the transceivers can start exchanging data
`
`using the transmission parameters. Id. at ¶ 58. In the context of DSL, data is sent
`
`in superframes. A superframe includes 68 data frames or discrete multitone
`
`(“DMT”) symbols followed by a synchronization frame or synch symbol. See id.
`
`at ¶¶ 59, 67. The transceivers count the received frames and may use their
`
`respective timing references to synchronize their respective frame counters. See
`
`Ex. 1001 at 5:51–52; Ex. 2005 at ¶ 82. A transceiver may use the received
`
`synchronization frame to identify, in part, the superframe boundaries. Ex. 2005 at
`
`¶¶ 62, 67, 129. This is known as “frame synchronization,” which is not the same
`
`as timing synchronization. Id. at ¶ 82.
`
`
`
`5
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`B.
`
`The 404 Patent
`
`
`
`The 404 Patent recognizes that prior art multicarrier transceivers were
`
`typically maintained in the “on” state – even if they were not actively transmitting
`
`or receiving data – because of their complexity and because they had to remain
`
`ready to immediately transmit or receive data. See Ex. 1001 at 2:55-58; Ex. 2005
`
`at ¶ 21. In the “on” state, both the transmitter and receiver of a prior art transceiver
`
`remained fully functional at all times. As a result, the multicarrier transceivers
`
`wasted a significant amount of power and had short life spans. See Ex. 1001 at
`
`2:58-63. Although low power modes (in which data communications are
`
`temporarily suspended) were known in the prior art, they were unsatisfactory
`
`because, after exiting the low power mode, the transceivers still had to go through
`
`the lengthy re-initialization process to determine parameters necessary for full data
`
`transmission. See id. at 3:23-30. The initialization process could take, for
`
`example, “tens of seconds.” This was unacceptable to users who desired near-
`
`instantaneous responses for data communications. See id. at 3:23-25; Ex. 2005 at ¶
`
`67.
`
`The inventions of the 404 patent (e.g., claims 1-20) provide a unique low
`
`power mode that improved the operation of multicarrier transceivers. The
`
`inventions allow the transceiver to enter a low power mode (and thus save power)
`
`while maintaining a framework
`
`that enables rapid return
`
`to full data
`
`
`
`6
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`communication capability. See Ex. 1001 at 3:31-33. The inventive framework for
`
`rapid-on capability includes maintaining synchronization between first and second
`
`transceivers by transmitting or receiving a synchronization signal while in the low
`
`power mode, reducing power consumption of at least one portion of a transmitter,
`
`and/or storing, in the low power mode, parameters used for full power mode data
`
`transmission (such as fine gain or bit allocation parameters). See id. at 10:2-12:21;
`
`Ex. 2005 at ¶ 22.
`
`Storing parameters associated with full-power mode and maintaining
`
`synchronization in the low power mode allows the claimed multicarrier transceiver
`
`to rapidly emerge from the low power mode and resume full data transmission
`
`immediately without performing
`
`time-consuming steps
`
`to re-initialize
`
`the
`
`transceivers. Ex. 1005 at 7:13-15, 8:4-13; Ex. 2005 at ¶ 22.
`
`Thus, the claimed inventions of the 404 patent address the deficiencies of
`
`prior art transceivers by eliminating the need for a constant “on” mode while still
`
`providing the desired near-instantaneous response. Ex. 1001 at 3:38–41. As
`
`discussed below, none of Bowie, Yamano, and the 1995 ADSL Standard teaches or
`
`suggests the novel systems and methods of the 404 patent. In fact, those references
`
`disclose systems that operate very differently from the inventions of the 404 patent
`
`and each other.
`
`IV. OVERVIEW OF THE CITED REFERENCES
`
`
`
`7
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`A. Bowie
`
`
`
`Bowie relates to a power conservation method for an asymmetric digital
`
`subscriber line (“ADSL”) system that transmits wide-bandwidth modulated data
`
`over a two-wire loop using high frequency carrier signals. Ex. 1005 at 1:4-8, 1:23-
`
`25. As shown below, the Bowie system uses ADSL units (e.g., modems) that are
`
`connected by a wire loop 120. Each ADSL unit includes signal processing
`
`electronics 111, data transmit circuitry 112, data receive circuitry 113, and a
`
`resume signal detector 115. See id. at 5:52-55; Ex. 2005 at ¶ 24.
`
`Bowie teaches that, prior to data being sent between two ADSL units over
`
`the loop, loop characteristics, such as “loop loss” (i.e., attenuation), must be
`
`determined and exchanged. See Ex. 1005 at 4:64-5:3. Bowie describes this
`
`
`
`
`
`8
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`exchange of loop characteristics as “handshaking.” See id. at 5:3-5. Bowie further
`
`teaches that, when an ADSL unit receives a shut-down signal, it enters a low
`
`power mode in which the signal processing, data transmit, and data receive
`
`circuitry is all shut down with only the resume signal detector remaining
`
`operational. See id. at 5:17-28. When the two ADSL units are in the low power
`
`mode, the loop in Bowie is “in an inactive state.” Id. at 5:28-29; Ex. 2005 at ¶¶ 25-
`
`26.
`
`Bowie explains that shutting down the transmitting, receiving, and signal
`
`processing circuitry which comprises most of the transceiver’s circuitry, saves a
`
`significant amount of power – up to five watts per loop. See Ex. 1005 at 2:1-6.
`
`Bowie further teaches that, upon entering the low power mode, the ADSL units
`
`may “store[] in memory 117 characteristics of the loop 220 that were determined
`
`by . . . handshaking.” Id. at 5:17-28. Unlike the inventions of the 404 patent,
`
`Bowie does not teach storing bit allocation or fine gain parameters in the low
`
`power mode. Ex. 2005 at ¶¶ 26-27.
`
`Upon receipt of a “resume signal” at the resume signal detector 115, the
`
`Bowie unit “returns the signal processing 111, transmitting 112, and receiving 113
`
`circuitry to full power mode.” Ex. 1005 at 5:60-62. The stored “loop transmission
`
`characteristics . . . are retrieved from memory 117 and used to enable data
`
`transmission to resume quickly by reducing the time needed to determine loop
`
`
`
`9
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`transmission characteristics.”1 Id. at 5:62-66. Thus, Bowie teaches using the
`
`stored loop characteristics as a starting point for re-determining the transmission
`
`parameters that are necessary for returning to full data transmission after coming
`
`out of the low power mode. Ex. 2005 at ¶ 28; Ex. 1005 at Fig. 3 (step 306), 6:26-
`
`42.
`
`According to Bowie, the additional handshaking (i.e., reinitialization) that
`
`occurs before returning to full data transmission includes a re-determination of
`
`loop characteristics to account for changes in loop characteristics that occurred
`
`while the system was in the low power mode. See Ex. 1005 at 5:66-6:1, 6:37-41
`
`(“Handshaking information may be required [after coming out of low power mode]
`
`where . . . loop characteristics have changed due, for example, to temperature-
`
`dependent changes in loop resistance.”). Re-determining the loop characteristics
`
`after coming out of low power mode is required to ensure “reliable data
`
`communication between the units.” Id. at 6:36-37; Ex. 2005 at ¶ 29.
`
`
`1 Bowie uses the terms “loop characteristics,” “electronic characteristics of the
`
`particular wire loop,” “loop transmission characteristics,” and “loop characteristic
`
`parameters” interchangeably. Ex. 1005 at 5:1-3, 5:23-25, 5:62-66, 6:25-33; Ex.
`
`2005 at ¶ 25.
`
`
`
`10
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`Thus, in contrast to the inventions of the 404 patent, Bowie teaches that re-
`
`
`
`initialization (i.e., re-determining
`
`the
`
`loop characteristics and exchanging
`
`handshaking information) must occur when the transceiver comes out of the low
`
`power mode. See id. at 5:62-6:2, 6:35-43; Ex. 2005 at ¶¶ 30-32.
`
`B. Yamano
`
`Yamano discloses embodiments
`
`that purport
`
`to correct alleged
`
`disadvantages of prior art single carrier DSL modems. Yamano explains that
`
`conventional DSL modems transport data by generating an analog transmission
`
`signal which is representative of a synchronous, constant rate, i.e., continuous, bit
`
`stream. Ex. 1006 at 1:18–20. Yamano further explains that the transmitter of a
`
`conventional DSL modem transmits “a continuous bit stream” which “is
`
`synchronous with respect to the modem bit clock.” Id. at 1:41–45. When no
`
`packets are available for transmission, the transmitter of a conventional DSL
`
`modem inserts idle information into the continuous bit stream. Id. at 1:45–49. The
`
`“continuous bit stream” that Yamano references, corresponds to the signaling and
`
`associated superframe structure described in the 1995 ADSL Standard. See Ex.
`
`1007 at p. 24.
`
`Yamano identifies several disadvantages with prior art DSL modem’s.
`
`Specifically, Yamano explains that because prior art DSL modems transmit
`
`constantly (either packet data or idle information), a large percentage of the total
`
`
`
`11
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`information carrying capacity is used to transmit idle information and the modems
`
`are not suited for multidrop operation. Ex. 1006 at 2:7–16. With respect to the
`
`prior art receiver of DSL modems, Yamano recognizes that “a significant
`
`percentage of [the receiver’s] processing is dedicated to the processing of the idle
`
`information generated by” the far end transmitter when the far end transmitter has
`
`no packets to transmit. Id. at 3:26–28.
`
`Yamano describes several embodiments that seek to overcome the purported
`
`disadvantages of conventional single carrier DSL transceivers that implement the
`
`1995 ADSL Standard. In a first embodiment, the receiver of the conventional
`
`ADSL transceiver is improved with circuitry that detects that idle information is
`
`being transmitted by the far end transmitter and, in response to detecting the
`
`transmitted idle information, the circuitry disables certain functional blocks of the
`
`receiver. See id. at, e.g., 3:44-64. Petitioner does not rely on this embodiment of
`
`Yamano in its obviousness analysis.
`
`In a second embodiment, instead of transmitting a continuous, synchronous
`
`bit stream, Yamano teaches modifying the transmitter to only transmit user data.
`
`The transmitter does not transmit idle information. See id. at 13:53-56. In this
`
`embodiment, data is transmitted as packets with intervening periods of no signal
`
`transmission between the packets. See id. at 13:56-65. Yamano refers to this
`
`transmission scheme as a “burst mode protocol.” See id. at 13:51-53.
`
`
`
`12
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`To operate in accordance with the burst mode protocol, Yamano discloses a
`
`receiver that includes a non-idle detector. See id. at 14:3-12. In this embodiment,
`
`the receiver has two modes of operation – a reduced processing mode and a full
`
`processing mode. See id. at 14:25-42. In the full processing mode, all the blocks
`
`of the receiver are enabled, and the receiver is capable of processing packet data
`
`transmitted by the far end transmitter. See id. at 14:25-42, Fig. 4. In the reduced
`
`processing mode – the mode the Petitioner understands as being the claimed low
`
`power mode – Yamano describes only enabling the non-idle detector and disabling
`
`the other blocks of the receiver shown in Figure 4 except the sample buffer and
`
`A/D converter. See id; Ex. 2005 at ¶46. The non-idle detector is configured to
`
`detect a non-idle state signal transmitted by the far end transmitter and to enable
`
`the full processing mode of the receiver circuit in response to detection of the non-
`
`idle state signal. See id. at 14:13-29.
`
`The far end transmitter implementing the burst mode protocol transmits a
`
`non-idle state signal prior to transmitting the available packet(s) of data. See id. at
`
`13:56-59. After completing transmission of the data, the transmitter ceases all
`
`transmission. See id. at 13:59-65, 14:29-33. The non-idle detector of the near end
`
`receiver detects the non-idle state signal and enables the disabled blocks of the
`
`receiver that then receives the data being transmitted by the far end transmitter.
`
`See id. at 14:25-29. After reception of data is complete, the receiver detects the
`
`
`
`13
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`absence of data and returns to the reduced processing mode where all blocks
`
`except for the non-idle detector, sample buffer, and A/D convert are disabled. See
`
`id. at 14:29-42. Details of Yamano’s burst mode protocol are discussed in the
`
`attached declaration of Patent Owner’s expert, Dr. Chrissan. See Ex. 2005 at ¶¶
`
`42-56. Significantly, Yamano’s burst mode embodiment does not comply with the
`
`superframe-based signaling of the 1995 ADSL Standard. See id. at ¶ 34 and 121-
`
`123.
`
`Yamano describes an improvement to the burst mode embodiment wherein
`
`the receiver disables the non-idle detector during the reduced processing mode. To
`
`facilitate the reception of data, Yamano explains that the transmitter of the
`
`transceiver whose receiver is in the reduced processing mode (i.e., the near-end
`
`transceiver) periodically transmits a poll or other timing signal to the far end
`
`transmitter. Either immediately after transmitting the poll or at a time
`
`corresponding to the other timing signal, the receiver enables the idle signal
`
`detector. See Ex. 2005 at ¶¶53-56. If the far end transceiver has data available for
`
`transmission, in response to detecting the poll or other timing signal, the far end
`
`transceiver transmits a non-idle state signal followed by the data. See Ex. 2005 at
`
`¶¶55-56. The non-idle detector of the near end receiver receives the non-idle state
`
`signal and, in response to detecting the signal, enables the disabled blocks of the
`
`receiver and receives the data being transmitted by the transmitter following the
`
`
`
`14
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`non-idle state signal. See Ex. 2005 at ¶51. Important to this proceeding is the fact
`
`that the periodic poll or timing signal disclosed in Yamano is merely used to
`
`ensure that the transmission of the non-idle state signal by the far end transmitter
`
`coincides with the time period when the near end receiver enables the non-idle
`
`detector. See Ex. 2004 at 174:8-24; Ex. 2005 at ¶¶56 and 116.
`
`Petitioner incorrectly relies on the disclosure of the poll to allege that
`
`Yamano teaches receiving or transmitting the claimed synchronization signal in the
`
`low power mode. See Pet. at 41-43, 57-58.
`
`C. The 1995 ADSL Standard
`
`The 1995 ADSL Standard discloses electrical characteristics of ADSL
`
`signals appearing at a network interface and the requirements for transmission
`
`between a network and customer installation. Ex. 1007 at 1; Ex. 2005 at ¶ 57. In
`
`its obviousness argument, Petitioner relies on the 1995 ADSL Standard, in part, for
`
`teaching determining fine gains and bit allocations as part of the initialization
`
`process. Pet. at 39-40. Importantly, the 1995 ADSL Standard teaches that, in the
`
`context of ADSL transceiver initialization, bit allocation and fine gain parameters
`
`are different than, and, in fact, are determined in part from, loop characteristics like
`
`those disclosed in Bowie.
`
`The 1995 ADSL Standard explains that initialization includes separate,
`
`sequential steps of determining loop characteristics and then determining bit and
`
`
`
`15
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`gain parameters based on the loop characteristics and other information. See Ex.
`
`2005 at ¶ 68; Ex. 1007 at 9 (“One part of the ADSL initialization and training
`
`sequence estimates the loop characteristics to determine whether the number of
`
`bytes per Discrete MultiTone (DMT) frame required for
`
`the requested
`
`configuration’s aggregate data rate [i.e., bit allocation] can be transmitted across
`
`the given loop.”), at 87 (“[E]ach receiver communicates to its far-end transmitter
`
`the number of bits and relative power levels [i.e., bit allocation and fine gain
`
`parameters] to be used on each DMT sub-carrier, as well as any messages and final
`
`data rates information. For highest performance these settings shall be based on
`
`the results [e.g.,, loop characteristics] obtained through the transceiver training and
`
`channel analysis procedures.”).2
`
` Thus, the 1995 ADSL Standard clearly
`
`distinguishes between collecting loop characteristics, on one hand, and determining
`
`and exchanging bit allocation and fine gain parameters, on the other hand. See Ex.
`
`2005 at ¶ 68.
`
`In addition, the technology described by the 1995 ADSL Standard differs
`
`from the inventions of the 404 patent. Specifically, the 1995 ADSL Standard does
`
`not describe, anywhere, operating in a low power mode. Additionally, the 1995
`
`ADSL Standard does not disclose storing bit allocation or fine gain parameters in a
`
`low power mode. Moreover, the 404 patent teaches avoiding the initialization
`
`
`2 All emphases are added unless otherwise indicated.
`
`
`
`16
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`steps disclosed in the 1995 ADSL Standard when transitioning from a low power
`
`mode to a full power mode. See Ex. 1001 at 10:16-18, Ex. 2005 at ¶ 69.
`
`V. LEVEL OF ORDINARY SKILL IN THE ART
`
`As of January 1998, and with respect to the 404 patent, a POSITA would
`
`have had an electrical engineering background and experience in the design of
`
`multicarrier communication systems, such as
`
`those employing orthogonal
`
`frequency division multiplexing or discrete multitone modulation. Such a POSITA
`
`would have had a bachelor’s degree in electrical engineering (or a similar technical
`
`degree or equivalent work experience) and at least 3 years of experience working
`
`with such multicarrier communication systems. See Ex. 2005 at ¶¶ 76-79.
`
`VI. CLAIM CONSTRUCTION
`
`A.
`
`“Synchronization Signal”
`
`Patent Owner originally proposed that the term “synchronization signal” be
`
`construed to mean “an indication used to establish or maintain a timing
`
`relationship between transceivers.” While Patent Owner continues to believe that
`
`this construction is correct, based on the Board’s constructions in the Institution
`
`Decision and on the application of those constructions, further clarification is
`
`necessary. Thus, Patent Owner proposes that the term “synchronization signal”
`
`should be construed to mean “a signal used to maintain a timing relationship
`
`between transceivers by correcting errors or differences between a timing reference
`
`
`
`17
`
`

`

`Patent Owner’s Response
`IPR2016-01466
`
`
`of the transmitter of the signal and a timing reference of the receiver of the signal.”
`
`See Ex. 2005 at ¶ 81.
`
`In its Institution Decision, the Board construed “synchronization signal” to
`
`be “a signal allowing frame synchronization between the transmitter of the signal
`
`and the receiver of the signal.” Paper No. 7 at 6. The Board’s construction is not
`
`reasonable because it is not consistent with the ordinary meaning of the claim
`
`language and the teachings of the specification.
`
`To begin with, the language of the Board’s constr