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`(12) United States Patent
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`US 6,287,973 132
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`(10) Patent N0.:
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`Aoi
`(45) Date of Patent:
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`Sep. 11, 2001
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`US006287973B2
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`(54) METHOD FOR FORMING
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`INTERCONNECTION STRUCTURE
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`(75)
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`Inventor: Nobuo Aoi, Hyogo (JP)
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`(73) Assignee: Matsushita Electric Industrial C0.,
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`Ltd., Osaka (JP)
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`( * ) Notice:
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`Subject to any disclaimer, the term of this
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`patent is extended or adjusted under 35
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`U.S.C. 154(b) by 0 days.
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`(21) Appl. No.: 09/756,242
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`(22)
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`Filed:
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`Jan. 9, 2001
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`0680 085 A1
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`06—291193
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`07-153842
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`09064034
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`09153545
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`11/1995 (EP).
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`10/1994 (JP).
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`6/1995 (JP).
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`3/1997 (JP).
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`6/1997 (JP).
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`OTHER PUBLICATIONS
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`European Search Report dated Jul. 1, 1999.
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`* cited by examiner
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`Primary Examiner—Benj amin L. Utech
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`Assistant Examiner—Lynette T. Umez-Eronini
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`(74) Attorney, Agent, or Firm—Eric J. Robinson; Nixon
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`Peabody LLP
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`Related US. Application Data
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`(57)
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`ABSTRACT
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`63
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`(30)
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`Mar. 26, 1998
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`PP
`lication No. 09/274,114, filed on Mar.
`Continuation of a
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`23, 1999, now Pat. No. 6,197,696.
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`Foreign Application Priority Data
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`(JP) ............................................... .. 10—079371
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`(51)
`Int. Cl.7 .................... .. H01L 21/311; H01L 21/3065
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`(52) US. Cl.
`........................ .. 438/700; 438/706; 438/723;
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`438/725
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`(58) Field of Search ................................... .. 438/700, 706,
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`438/723, 725
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`(56)
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`References Cited
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`U.S. PATENT DOCUMENTS
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`..................... .. 438/623
`5/1992 Kessler et al.
`5,110,712
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`438/624
`5/1996 Park ............ ..
`5,518,963
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`438/638
`6/1997 Huang et al.
`5,635,423
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`438/628
`7/1997 Dennison et al.
`5,651,855
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`438/620
`12/1997 Lee et al.
`5,702,982
`.... ..
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`438/622
`6/2000 Huang et al.
`6,077,769 *
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`438/624
`7/2000 Lee .............. ..
`6,083,822 *
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`438/700
`3/2001 Aoi
`6,197,696 *
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`4/2001 Han .................................... .. 257/622
`6,222,255 *
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`FOREIGN PATENT DOCUMENTS
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`5/1991 (EP) .
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`0 425 787 A2
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`In a method for forming an interconnection structure, first,
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`second and third insulating films and a thin film are sequen-
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`tially formed over lower-level metal interconnects. Then, the
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`thin film is masked With a first resist pattern and etched to
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`form a mask pattern With openings for interconnects. Next,
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`the third insulating film is masked With a second resist
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`pattern and dry-etched such that the third insulating film and
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`the first and second resist patterns are etched at a high rate
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`and that the second insulating film is etched at a low rate to
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`form openings for contact holes in the third insulating film
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`and remove the first and second resist patterns. Then, the
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`second insulating film is masked With the third insulating
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`film and dry-etched such that the second insulating film is
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`etched at a high rate and that the first and third insulating
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`films are etched at a low rate to form the openings for contact
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`holes in the second insulating film. Then, the third and first
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`insulating films are masked With the mask pattern and the
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`second insulating film, respectively, and dry-etched such
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`that the first and third insulating films are etched at a high
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`rate and that the mask pattern and the second insulating film
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`are etched at a low rate to form Wiring grooves and contact
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`holes in the third and first insulating films, respectively.
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`Finally, upper-level metal interconnects and contacts are
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`formed.
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`8 Claims, 37 Drawing Sheets
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`TSMC Exhibit 1035
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`TSMC v. IP Bridge
`IPR2016-01379
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`Page 1 of 55
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`TSMC Exhibit 1035
`TSMC v. IP Bridge
`IPR2016-01379
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`

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`US. Patent
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`Sep. 11,2001
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`Sheet 1 0137
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`US 6,287,973 B2
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`Sheet 2 0137
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`US 6,287,973 B2
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`Sheet 19 0137
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`US 6,287,973 B2
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`Fig.24(c)
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`559
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`556B
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`555B
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`554A
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`553A
`551
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`Fig. 29 (a)
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`Sheet 30 0137
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`US 6,287,973 B2
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`605
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`604
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`603
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`602
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`601
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`600
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`607
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`606
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`605
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`604
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`603
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`602
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`601
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`600
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`607
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`608
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`605
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`604
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`603
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`602
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`601
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`600
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`Fig.30(a)
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`Fig.30(b)
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`! L
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`Fig.30(c)
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`Sheet 31 0137
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`US 6,287,973 B2
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`L‘\“\\\\‘
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`L\\\\\‘\“
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`Fig.31(a)
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`Fig.31(b)
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`608
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`605
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`604
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`603
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`602
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`601
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`600
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`609
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`608
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`605
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`603
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`602
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`Fig.31(c)
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`602
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`Sheet 32 0137
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`US 6,287,973 B2
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`Fig.32(a)
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`608
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`605A
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`604A
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`603
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`602
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`601
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`600
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`Fig.32(b)
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`610
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`611
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`608
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`605B
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`604A
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`603A
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`602
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`601,
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`600
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`612
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`613
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`Fig.32(c)
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`605B
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`604B
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`603A
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`Sheet 33 0137
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`US 6,287,973 B2
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`655
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`654
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`653
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`652
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`650
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`657
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`656
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`655
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`654
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`653
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`652
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`651
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`650
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`657
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`658
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`655
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`654
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`653
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`652
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`651
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`650
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`Fig.33(a)
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`Fig.33(b)
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`Fig. 33 (C)
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`Sheet 34 0137
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`US 6,287,973 B2
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`R\\\\\\\‘
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`L\“\\‘\“
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`Fig.34(a)
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`Fig.34(b)
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`658
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`655
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`654
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`653
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`652
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`651
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`650
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`659
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`658
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`655
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`654
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`653
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`652
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`651
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`650
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`658
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`655A
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`654
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`653
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`652
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`651
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`650
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`Fig.34(c)
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`Sheet 35 0137
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`US 6,287,973 B2
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`658
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`655A
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`654A
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`653
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`652
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`651
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`650
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`658
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`655B
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`654A
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`653A
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`652
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`651
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`650
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`655B
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`654B
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`653A
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`652A
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`651
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`650
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`Fig.35(a)
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`Fig.35(b)
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`660
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`661
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`662
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`663
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`Fig.35(c)
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`US 6,287,973 B2
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`Fig.36
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`MASK PATTERN<559>
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`SECOND RESIST PATTERN
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`(560)
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` OPENINGS FOR
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`FORMING CONTACT HOLES
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`FORMING INTERCONNECTS
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`OPENINGS FOR
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`Sheet 37 0137
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`US 6,287,973 B2
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`Fig.37(a)
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`560 559
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`501
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`L‘“
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`L‘“ 559
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`551
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`!!!!!!!!!lII
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`1
`METHOD FOR FORMING
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`INTERCONNECTION STRUCTURE
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`This application is a Continuation of application Ser. No.
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`09/274,114 filed Mar. 23, 1999, now US. Pat. No. 6,197,
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`696.
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`5
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`2
`The relative dielectric constant of a fluorine-doped silicon
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`dioxide film is about 3.3 to about 3.7, which is about 20
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`percent lower than that of a conventional silicon dioxide
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`film. Nevertheless, a fluorine-doped silicon dioxide film is
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`highly hygroscopic, and easily absorbs water in the air,
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`resulting in various problems in practice. For example, when
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`the fluorine-doped silicon dioxide film absorbs water, SiOH
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`groups, having a high relative dielectric constant, are intro-
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`duced into the film. As a result,
`the relative dielectric
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`constant of the fluorine-doped silicon dioxide film adversely
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`increases, or the SiOH groups react with the water during a
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`heat treatment to release H20 gas. In addition, fluorine free
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`radicals, contained in the fluorine-doped silicon dioxide
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`film, segregate near the surface thereof during a heat treat-
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`ment and react with Ti, contained in a TiN layer formed
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`thereon as an adhesion layer, to form a TiF film, which easily
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`peels off.
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`An HSQ (hydrogen silsesquioxane) film, composed of Si,
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`O and H atoms,
`is an exemplary low-dielectric-constant
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`SOG film. In the HSQ film, the number of the H atoms is
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`about two-thirds of that of the O atoms. However, the HSQ
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`film releases a larger amount of water than a conventional
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`silicon dioxide film. Accordingly, since it is difficult to form
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`a buried interconnection line in the HSQ film, a patterned
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`metal film should be formed as metal interconnects on the
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`HSQ film.
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`Also, since the HSQ film cannot adhere so strongly to
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`metal interconnects, a CVD oxide film should be formed
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`between the metal
`interconnects and the HSQ film to
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`improve the adhesion therebetween. However,
`in such a
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`if the CVD oxide film is formed on the metal
`case,
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`interconnects, then the substantial line-to-line capacitance is
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`equal to the serial capacitance formed by the HSQ and CVD
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`films. This is because the CVD oxide film with a high
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`dielectric constant exists between the metal interconnects.
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`Accordingly, the resulting line-to-line capacitance is larger
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`as compared with using the HSQ film alone.
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`An organic polymer film, as well as the low-dielectric-
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`constant SOG film, cannot adhere strongly to metal
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`interconnects, either. Accordingly, a CVD oxide film should
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`be formed as an adhesion layer between the metal intercon-
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`nects and the organic polymer film, too.
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`Moreover, an etch rate, at which an organic polymer film
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`is etched, is approximately equal to an ash rate, at which a
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`resist pattern is ashed with oxygen plasma. Accordingly, a
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`usual resist application process is not applicable in such a
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`situation, because the organic polymer film is likely to be
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`damaged during ashing and removing the resist pattern.
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`Therefore, a proposed alternate process includes: forming a
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`CVD oxide film on an organic polymer film; forming a resist
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`film on the CVD oxide film; and then etching the resist film
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`using the CVD oxide film as an etch stopper, or a protective
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`film.
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`However, during the step of forming the CVD oxide film
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`on the organic polymer film,
`the surface of the organic
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`polymer film is exposed to a reactive gas containing oxygen.
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`Accordingly, the organic polymer film reacts with oxygen to
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`take in polar groups such as carbonyl groups and ketone
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`groups. As a result, the relative dielectric constant of the
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`organic polymer film disadvantageously increases.
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`Also,
`in forming inlaid copper
`interconnects in the
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`organic polymer film, a TIN adhesion layer, for example,
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`should be formed around wiring grooves formed in the
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`organic polymer film, because the organic polymer film
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`cannot adhere strongly to the metal interconnects. However,
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`since the TiN film has a high resistance,
`the effective
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`10
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`15
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`20
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`25
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`30
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`35
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`40
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`45
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`50
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`55
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`60
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`65
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`BACKGROUND OF THE INVENTION
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`The present invention relates to a method for forming an
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`interconnection structure in a semiconductor integrated cir-
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`cuit.
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`integrated within a single
`As the number of devices,
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`semiconductor integrated circuit, has been tremendously
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`increasing these days, wiring delay has also been increasing
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`noticeably. This is because the larger the number of devices
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`integrated, the larger line-to-line capacitance (i.e., parasitic
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`capacitance between metal interconnects), thus interfering
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`with the performance improvement of a semiconductor
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`integrated circuit. The wiring delay is so-called “RC delay”,
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`which is proportional to the product of the resistance of
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`metal interconnection and the line-to-line capacitance.
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`In other words,
`to reduce the wiring delay, either the
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`resistance of metal interconnection or the line-to-line capaci-
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`tance should be reduced.
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`In order to reduce the interconnection resistance, IBM
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`Corp., Motorola, Inc., etc. have reported semiconductor
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`integrated circuits using copper, not aluminum alloy, as a
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`material for metal interconnects. A copper material has a
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`specific resistance about two-thirds as high as that of an
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`aluminum alloy material. Accordingly, in accordance with
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`simple calculation, the wiring delay involved with the use of
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`a copper material for metal
`interconnects can be about
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`two-thirds of that involved with the use of an aluminum
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`alloy material therefor. That is to say, the operating speed
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`can be increased by about 1.5 times.
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`integrated within a
`However,
`the number of devices,
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`single semiconductor integrated circuit, is expected to fur-
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`thus
`ther increase by leaps and bounds from now on,
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`increasing the wiring delay considerably. Therefore, it is
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`concerned that even the use of copper as an alternate metal
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`interconnection material would not be able to catch up with
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`such drastic increase. Also, the specific resistance of copper
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`as a metal interconnection material is just a little bit higher
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`than, but almost equal to, that of gold or silver. Accordingly,
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`even if gold or silver is used instead of copper as a metal
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`interconnection material, the wiring delay can be reduced
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`only slightly.
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`Under these circumstances, not only reducing intercon-
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`nection resistance but also suppressing line-to-line capaci-
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`tance play a key role in further increasing the number of
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`devices that can be integrated within a single semiconductor
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`integrated circuit. And the relative dielectric constant of an
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`interlevel insulating film should be reduced to suppress the
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`line-to-line capacitance. A silicon dioxide film has hereto-
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`fore been used as a typical material for an interlevel insu-
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`lating film. The relative dielectric constant of a silicon
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`dioxide film is, however, about 4 to about 4.5. Thus, it would
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`be difficult to apply a silicon dioxide film to a semiconductor
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`integrated circuit incorporating an even larger number of
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`devices.
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`In order to solve such a problem, fluorine-doped silicon
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`dioxide film, low-dielectric-constant spin-on-glass (SOG)
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`film, organic polymer film and so on have been proposed as
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`alternate interlevel insulating films with respective relative
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`dielectric constants smaller than that of a silicon dioxide
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`film.
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`Page 39 0f 55
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`Page 39 of 55
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`US 6,287,973 B2
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`3
`cross-sectional area of the metal interconnects decreases.
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`Consecuently, the intended effect attainable by the use of the
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`copper lines, i.e., reduction in resistance, would be lost.
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`SUMMARY OF THE INVENTION
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`An object of the present invention is providing a method
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`for forming an interconnection structure in which an insu-
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`lating film with a low dielectric constant can be formed by
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`an ordinary resist application process.
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`A first method for forming an interconnection structure
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`according to the present invention includes the steps of: a)
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`forming a first insulating film over lower-level metal inter-
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`connects; b) forming a second insulating film, having a
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`different composition than that of the first insulating film,
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`over the first insulating film; c) forming a third insulating
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`film, having a different composition than that of the second
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`insulating film, over the second insulating film; d) forming
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`a thin film over the third insulating film; e) forming a first
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`resist pattern, having a plurality of openings for forming
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`wiring grooves, on the thin film; f) etching the thin film
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`using the first resist pattern as a mask, thereby forming a
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`mask pattern out of the thin film to have the openings for
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`forming wiring grooves; g) forming a second resist pattern,
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`having a plurality of openings for forming contact holes, on
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`the third insulating film; h) dry-etching the third insulating
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`film under such conditions that the third insulating film and
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`the first and second resist patterns are etched at a relatively
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`high rate and that the second insulating film is etched at a
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`relatively low rate, thereby patterning the third insulating
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`film to have the openings for forming contact holes and
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`removing the first and second resist patterns either entirely
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`or partially with respective lower parts thereof left;
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`dry-etching the second insulating film using the patterned
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`third insulating film as a mask under such conditions that the
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`second insulating film is etched at a relatively high rate and
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`the first and third insulating films are etched at a
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`relatively low rate, thereby patterning the second insulating
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`film to have the openings for forming contact holes;
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`dry-etching the third and first insulating films using the mask
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`pattern and the patterned second insulating film as respective
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`masks under such conditions that the first and third insulat-
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`ing films are etched at a relatively high rate and that the mask
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`pattern and the second insulating film are etched at a
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`relatively low rate,
`thereby forming wiring grooves and
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`contact holes in the third and first insulating films, respec-
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`tively; and k) filling in the wiring grooves and the contact
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`holes with a metal film, thereby forming upper-level metal
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`interconnects and contacts connecting the lower- and upper-
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`level metal interconnects together.
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`the third
`In the first method of the present invention,
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`insulating film is dry-etched under such conditions that the
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`third insulating film and the first and second resist patterns
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`are etched at a relatively high rate and that the second
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`insulating film is etched at a relatively low rate, thereby
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`patterning the third insulating film and removing the first
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`and second resist patterns in the step h). Accordingly, it is
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`not necessary to perform the step of ashing and removing the
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`first and second resist patterns with oxygen plasma. In other
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`words, since it is possible to prevent the third insulating film
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`from being damaged during ashing and removing a resist
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`pattern, a low-dielectric-constant
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`would otherwise be damaged easily by oxygen plasma, may
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`be used as the third insulating film. As a result, an interlevel
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`insulating film with a low dielectric constant can be formed
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`by an ordinary resist application process.
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`In addition, the second insulating film