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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`
`
`Case IPR2016-01377
`Patent 6,197,696 B1
`
`
`PETITIONER’S REPLY TO PATENT OWNER’S RESPONSE
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`
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`IPR2016-01377
`Patent 6,197,696 B1
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`TABLE OF CONTENTS
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`2.
`
`3.
`
`4.
`
`
`INTRODUCTION ........................................................................................... 1
`I.
`II. ARGUMENT ................................................................................................... 2
`A. Grill is prior art because its Japanese parent, JP ’371, does not
`support the challenged claims, and because Grill’s priority date
`predates JP ’371. .................................................................................... 2
`IPB has the burden of proving JP ’371 supports the
`1.
`challenged claims, and TSMC had no obligation to
`disprove that in its petition. ......................................................... 2
`The Board’s claim construction does not support IPB’s
`argument that JP ’371 discloses claim 10. .................................. 3
`Even if the Board applies the construction the way IPB
`advocates, IPB’s priority claim fails. .......................................... 9
`Grill benefits from the filing date of the ’628 application
`because that application supports Grill’s claim 28. .................. 14
`B. A POSITA would have been motivated to combine Grill and
`Aoyama with a reasonable expectation of success. ............................. 22
`Aoyama’s via pattern complements Grill. ................................ 23
`1.
`Grill does not teach away from Aoyama’s via pattern. ............ 27
`2.
`III. CONCLUSION .............................................................................................. 32
`IV. CERTIFICATION UNDER 37 C.F.R. §42.24(d) ......................................... 32
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`IPR2016-01377
`Patent 6,197,696 B1
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`
`TABLE OF AUTHORITIES
`Cases
`Bayer CropScience AG v. Dow Agro Sciences LLC, 728 F.3d 1324 (Fed. Cir.
`2013) ..................................................................................................................... 9
`
`Dynamic Drinkware, LLC v. Nat’l Graphics, Inc., 800 F.3d 1375 (Fed. Cir.
`2015) .......................................................................................................... 2, 3, 14
`
`In re Applied Materials, Inc., 692 F.3d 1289 (Fed. Cir. 2012) ............................... 27
`
`In re Gurley, 27 F.3d 551 (Fed. Cir. 1994) .............................................................. 31
`
`In re Mouttet, 686 F.3d 1322 (Fed. Cir. 2012) ................................................. 25, 27
`
`Lucent Techs., Inc. v. Gateway, Inc., 543 F.3d 710 (Fed. Cir. 2008) ........................ 2
`
`Markman v. Westview Instruments, Inc., 52 F.3d 967 (Fed. Cir. 1995) .................... 9
`
`Trs. of Columbia Univ. v. Symantec Corp., 811 F.3d 1359 (Fed. Cir. 2016) ............ 9
`
`TurboCare Div. of Demag Delaval Turbomachinery Corp. v. General Elec.
`Co., 264 F.3d 1111 (Fed. Cir. 2001) ................................................................... 22
`
`Other Authorities
`Core Survival, Inc. v. S&S Precision, LLC, PGR2015-00022, Paper 8
`(P.T.A.B. Feb. 19, 2016) ....................................................................................... 3
`
`Rules
`37 C.F.R. §42.24 ...................................................................................................... 32
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`
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`
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`ii
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`IPR2016-01377
`Patent 6,197,696 B1
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`
`LIST OF EXHIBITS
`
`Exhibit 1001:
`
`U.S. Patent No. 6,197,696 to Aoi et al.
`
`Exhibit 1002:
`
`Expert Declaration of Dr. Bruce W. Smith, Ph.D.
`
`Exhibit 1003:
`
`U.S. Patent No. 3,617,824 to Shinoda et al.
`
`Exhibit 1004:
`
`U.S. Patent No. 3,838,442 to Humphreys.
`
`Exhibit 1005:
`
`U.S. Patent No. 6,140,226 to Grill et al.
`
`Exhibit 1006:
`
`U.S. Patent No. 5,635,423 to Huang et al.
`
`Exhibit 1007:
`
`Exhibit 1008:
`
`
`Exhibit 1009:
`
`
`Exhibit 1010:
`
`U.S. Patent No. 5,741,626 to Jain et al.
`C. Akrout et al., “A 480-MHz Microprocessor in a 0.12μm Leff
`CMOS Technology with Copper Interconnects,” IEEE J. of
`Solid-State Circuits, Vol. 33, no. 11 (November 1998).
`
`J.N. Burghartz et al., “Monolithic Spiral Inductors Fabricated
`Using a VLSI Cu-Damascene Interconnect Technology and
`Low-Loss Substrates,” International Electron Devices Meeting
`(December 1996).
`
`U.S. Patent No. 6,100,184 to Zhao et al.
`
`Exhibit 1011:
`
`U.S. Patent No. 6,103,616 to Yu et al.
`
`Exhibit 1012:
`
`File History of U.S. Patent No. 6,197,696 to Aoi et al.
`
`Exhibit 1013:
`
`Japanese Patent Application No. 10-079371 to Aoi.
`
`Exhibit 1014:
`
`Certified Translation of Japanese Patent Application No. 10-
`079371 to Aoi.
`
`Exhibit 1015:
`
`Japanese Patent Application No. 11-075519 to Aoi.
`
`Exhibit 1016:
`
`Certified Translation of Japanese Patent Application No. 11-
`075519 to Aoi.
`
`Exhibit 1017:
`
`U.S. Provisional Patent Application No. 60/071,628.
`
`iii
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`Exhibit 1018:
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`U.S. Patent No. 5,592,024 to Aoyama et al.
`
`Exhibit 1019:
`
`Exhibit 1020:
`
`
`Exhibit 1021:
`
`
`Exhibit 1022:
`
`
`Exhibit 1023:
`
`
`Exhibit 1024:
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`Exhibit 1025:
`
`
`Exhibit 1026:
`
`
`Exhibit 1027:
`
`
`Exhibit 1028:
`
`
`
`Exhibit 1029:
`
`U.S. Patent No. 5,920,790 to Wetzel et al.
`
`Transcript of Teleconference with the Board, dated November
`16, 2016.
`
`http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=
`4251.
`
`IEEE, “Technical Digest of the International Electron Devices,”
`1996 International Electron Devices Meeting at San Francisco,
`CA, Table of Contents (December 8-11, 1996).
`
`J.N. Burghartz et al., “Monolithic spiral inductors fabricated
`using a VLSI Cu-damascene interconnect technology and low-
`loss substrates,” 1996 International Electron Devices Meeting
`at San Francisco, CA, pp. 99-102 (December 8-11, 1996).
`
`http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=15684.
`
`G. Gerosa, “Introduction to the Digital Section,” IEEE Journal
`of Solid-State Circuits, vol. 33, no. 11, p. 1599 (Nov. 1998).
`
`J. Dreibelbis, “Introduction to the Memory Section,” IEEE
`Journal of Solid-State Circuits, vol. 33, no. 11, p. 1649 (Nov.
`1998).
`
`L.E. Thon, “Introduction to the Signal Processing Section,”
`IEEE Journal of Solid-State Circuits, vol. 33, no. 11, pp. 176-
`643 (Nov. 1998).
`
`http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=156
`84&filter%3DAND%28p_IS_Number%3A15684%29&page
`Number=2.
`
`C. Akrout et al., “A 480-MHz RISC Microprocessor in a 0.12-
`μm Leff CMOS Technology with Copper Interconnects,” IEEE
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`Exhibit 1030:
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`Exhibit 1031:
`
`Exhibit 1032:
`
`Exhibit 1033:
`
`Journal of Solid-State Circuits, vol. 33, no. 11, pp. 1609-16
`(Nov. 1998).
`
`Declaration of J. Preston Long dated February 15, 2017.
`
`Excerpts from James D. Plummer et al., “Silicon VLSI
`Technology: Fundamentals, Practice, and Modeling” (2000).
`
`Excerpts from C.Y. Chang & S. M. Sze, “ULSI Technology”
`(1996).
`
`Excerpts from S. Wolf & R.N. Tauber, “Silicon Processing for
`the VLSI Era: Volume 1: Process Technology” (1986).
`
`Exhibit 1034:
`
`U.S. Patent No. 5,091,047 to Cleeves et al.
`
`Exhibit 1035:
`
`U.S. Patent No. 6,287,973 to Aoi et al.
`
`Exhibit 1036:
`
`U.S. Patent No. 4,560,436 to Bukhman et al.
`
`Exhibit 1037:
`
`U.S. Patent No. 6,091,081 to Matsubara et al.
`
`Exhibit 1038:
`
`U.S. Patent No. 4,473,437 to Higashikawa et al.
`
`Exhibit 1039:
`
`U.S. Patent No. 5,880,018 to Boeck et al.
`
`Exhibit 1040:
`
`U.S. Patent No. 4,832,789 to Cochran et al.
`
`Exhibit 1041:
`
`U.S. Patent No. 4,855,252 to Peterman et al.
`
`Exhibit 1042:
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`U.S. Patent No. 5,786,276 to Brooks et al.
`
`Exhibit 1043:
`
`U.S. Patent No. 5,756,216 to Becker et al.
`
`Exhibit 1044:
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`U.S. Patent No. 5,821,168 to Jain.
`
`Exhibit 1045:
`
`J.M. Moran & D. Maydan, “High Resolution, Steep Profile
`Resist Patterns,” J. Vac. Sci. & Tech., vol. 16, no. 6 (Nov./Dec.
`1979).
`
`Exhibit 1046: M.M. O’Toole et al., “Linewidth Control in Projection
`Lithography Using a Multilayer Resist Process,” IEEE
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`Transactions on Electron Devices, vol. ED-28, no. 11 (Nov.
`1981).
`
`Exhibit 1047:
`
`E. Bassous et al., “A Three-Layer Resist System for Deep U.V.
`and RIE Microlithography on Nonplanar Surfaces,” J.
`Electrochem. Soc.: Solid-State Sci. & Tech. (Feb. 1983).
`
`Exhibit 1048:
`
`Transcript of the Deposition of Dr. A. Glew (June 30, 2017).
`
`
`Exhibit 1049:
`
`
`Exhibit 1050:
`
`U.S. Provisional Patent Application No. 60/071,628 (with line
`numbering appended).
`
`Declaration of Dr. Bruce W. Smith, Ph.D. in Support of
`Petitioner’s Reply.
`
`vi
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`I.
`
`INTRODUCTION
`IPB does not dispute the Grill-Aoyama combination teaches every limitation
`
`of claims 10-12. All IPB argues is Grill is not prior art and a POSITA would not
`
`have combined the references.
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`On the first issue, IPB must overcome two obstacles to remove Grill as prior
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`art but cannot. First, IPB fails to establish support for claim 10 in JP ’371 because
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`it misapplies the Board’s construction of “using the [designated layer] as a mask.”
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`Second, IPB cannot credibly challenge Grill’s entitlement to the benefit of its
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`parent application because its sole argument—that one sentence in Grill
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`constituted new matter—ignores disclosures in the parent that convey the same
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`information.
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`On the second issue, a POSITA would have found it obvious to combine
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`Grill and Aoyama because they complement one another to minimize the
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`consequences of misalignment during photolithography. IPB’s contrary arguments
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`address combinations TSMC never proposed and contain manifest factual errors.
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`Because IPB could not provide any credible challenges to the Board’s
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`preliminary findings, and because a preponderance of evidence supports the
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`instituted obviousness combination, the Board should cancel the challenged claims.
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`IPR2016-01377
`Patent 6,197,696 B1
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`II. ARGUMENT
`A. Grill is prior art because its Japanese parent, JP ’371, does not
`support the challenged claims, and because Grill’s priority date
`predates JP ’371.
`
`Grill is presumptively prior art because it was filed before the application for
`
`the ’696 patent. For IPB to remove Grill as prior art, it must (1) show JP ’371, the
`
`Japanese parent to the ’696 patent, supports the challenged claims, and (2) deny
`
`Grill the benefit of its parent’s filing date for prior art purposes. IPB cannot clear
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`either hurdle.
`
`1.
`
`IPB has the burden of proving JP ’371 supports the
`challenged claims, and TSMC had no obligation to disprove
`that in its petition.
`
`IPB bears the burden to establish earlier priority for the challenged claims.
`
`Paper 9, 1-3. Grill is presumptively prior art, so TSMC did not need to rebut a
`
`priority claim until IPB made one. Dynamic Drinkware, LLC v. Nat’l Graphics,
`
`Inc., 800 F.3d 1375, 1379-80 (Fed. Cir. 2015).
`
`Priority is assessed claim-by-claim, Lucent Techs., Inc. v. Gateway, Inc., 543
`
`F.3d 710, 718 (Fed. Cir. 2008), and contrary to IPB’s allegation (Paper 19, 35-36),
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`a priority document listed on the patent’s face does not indicate whether or how a
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`patent owner might allege priority for any particular claim.1 In Tech. Licensing
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`
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`1 For example, IPB alleges priority for claims 10 and 11 but not claim 12.
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`2
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`Corp. v. VideoTek, Inc., 545 F.3d 1316, 1327-28 (Fed. Cir. 2008), from which
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`Drinkware draws extensively, and Core Survival, Inc. v. S&S Precision, LLC,
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`PGR2015-00022, Paper 8, 8-10 & n.3 (P.T.A.B. Feb. 19, 2016), the patents-at-
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`issue listed priority documents, but the patent owner still bore the burden of proof.
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`Although the law did not require TSMC to guess IPB’s strategy and
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`preemptively dispute it, TSMC put IPB on notice of its arguments as the Board
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`recommends. Paper 2, 22-32 & n.2; EX1002 (App’x B); see also Core Survival,
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`Paper 8, 9-10 & n.3.
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`2.
`
`The Board’s claim construction does not support IPB’s
`argument that JP ’371 discloses claim 10.
`
`The Board adopted IPB’s proposed construction that “using the [designated
`
`layer] as a mask” means using the designated layer to “define areas for etching.”
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`Paper 11, 18-19. To argue JP ’371 supports claim 10, IPB relies on the false
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`premise that a buried layer “define[s] areas for etching” whenever it has a vertical
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`sidewall “in line and flush with an edge of overlying layer” (e.g., layer 358 below).
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`Paper 19, 8-14, 24-27. The Board already rejected IPB’s argument (Paper 11, 17-
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`18), and it should continue to do so.
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`3
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`a.
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`IPB has no support for its misapplication of “mask.”
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`IPB asserts a buried layer “defines an area for etching” even when it has
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`nothing to do with the etch. See Paper 19, 24-28. To illustrate IPB’s mistake,
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`consider the images below. The striped layer contains the via (i.e., contact-hole)
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`pattern, the blue layer contains a wiring pattern, and the etch transfers the via
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`pattern into the green layer.
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`
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`IPB believes the blue layer is a mask even though it plays no role defining the
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`square-shaped via pattern, which is what a mask does. EX1050, ¶29.
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`IPB speculates a buried layer blocks laterally traveling particles (Paper 19,
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`16), but the etches at issue are highly directional with negligible lateral deviation.
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`EX1031, 25 (“[M]odern fabrication methods tend to employ directional etching
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`and vertical steps with little undercutting.”), 39 (“[I]t is usually assumed that all the
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`ions arrive normal to the wafer surface, as shown in Figure 10-11(b).”), 41 (“Since
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`the ions are striking normal to the wafer surface, the enhancement will occur
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`4
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`normal to the wafer surface.”); EX1032, 56 (“[T]ransport must be perpendicular to
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`the surface so that only the etch rate of the bottom surface is enhanced.”); EX1050,
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`¶11.
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`IPB introduced the figure on the left below (Paper 19, 16), but it inaccurately
`
`depicts what occurs in reactive ion etching (“RIE”). The non-vertical trajectories
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`IPB posits would undercut the layer being etched, as shown on the right. EX1050,
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`¶12. This does not occur in practice (id.), disproving IPB’s speculation.
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`
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`In RIE, “the profiles are not just a linear combination of isotropic chemical
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`etching and anisotropic physical etching,” but are “much more like the case for
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`physical etching acting alone, as in Figure 10-3(c) [below].” EX1031, 40. “Since
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`the ions are striking normal to the wafer surface,” RIE “result[s] in directional,
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`anisotropic etching.” EX1031, 41. “If the chemical component in the etch system is
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`increased, the vertical etching is increased but not the lateral etching, which is not
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`what would be expected.” EX1031, 40; see also EX1050, ¶¶13-15.
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`EX1031, Figure 10-3(c)
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`IPB’s discussion of tri-layer “masks”—more aptly tri-layer resist
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`“processes” (EX2015, 7-8; EX1032, 41-42, 70; EX1033, 13-14)—fails to support
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`its position. A tri-layer resist process (depicted in the figures below) begins with an
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`intermediate hard mask layer (e.g., SiO2) sandwiched between a top photoresist
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`layer and a bottom planarization/primary layer. EX1032, 41-42; EX1033, 14;
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`EX1034, 2:28-35; EX2015, 8; EX1050, ¶18.
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` EX1045, Figure 4 EX1033, Fig. 11
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`6
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` EX1032, FIGURE 17 EX1034, FIGS. 1–4
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`The top resist layer is the mask for patterning the intermediate layer, and
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`afterward, the intermediate layer acts as the mask for etching the bottom layer.
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`EX1034, Abstract; EX1032, 41-42, 70, FIG. 17; EX1033, 14, Fig. 11; EX2010,
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`60:22-63:2; EX1034, 3:20-22, 3:29-30; EX1050, ¶18. The intermediate layer is not
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`a mask because of its sidewalls; it becomes a mask after eliminating the top resist
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`layer, as shown above. EX1032, 41-42, FIG. 17; EX1033, 14, Fig. 11; EX1034,
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`3:20-41; EX2010 at 61:14-63:2; EX1045, 4-6; EX1046, 3; EX1047, 2-3; EX1050,
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`¶18. The bottom layer is also not a mask for etching the layer below it. Contrary to
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`IPB’s allegations, neither TSMC’s expert nor his textbook suggests otherwise.2
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`EX1050, ¶¶16-19.
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`
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`2 IPB mistakenly suggests Figure 12.3(c) in Dr. Smith’s book contradicts
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`this understanding (Paper 19, 17-18), but it misinterprets Figure 12.3(c), which
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`does not depict a structure. EX2010, 61:14-63:2. Citing EX1045 through EX1047
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`7
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`b.
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`Inconsistencies in the intrinsic evidence do not justify
`IPB’s priority argument.
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`IPB cherry-picks three examples where the specification incorrectly refers to
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`a buried layer as a “mask” (EX1001, 17:35-40, Figs. 13(b), 13(c) (layer 305A);
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`19:50-54, Figs. 16(c), 16(d) (layer 355A); 26:22-29, Figs. 28(b), 29(a) (layer
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`556B)), ignoring at least seven contrary examples (EX1001, 11:51-55, Figs. 2(c),
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`3(a) (103A not a mask), 13:37-41, Figs. 6(a), 6(b) (103A not a mask), 14:41-45,
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`Figs. 8(a), 8(b) (103A not a mask), 16:7-11, Figs. 10(c), 11(a) (203A not a mask),
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`17:20-29, Figs. 13(a), 13(b) (305A and 304A not masks), 19:33-38, Figs. 16(a),
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`16(b) (355A not a mask), 21:33-39, Figs. 18(c), 19(a) (405A not a mask)). See
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`EX1050, ¶¶21, 27.
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`Even IPB’s declarant admits the ’696 patent sometimes uses “mask”
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`incorrectly. EX1048, 97:12-99:21 (admitting layer 509 not a mask in EX1001,
`
`23:40-46, Figs. 22(b), 22(c), despite contrary textual description); see also
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`EX1050, ¶¶23-26.
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`
`
`as sources, Dr. Smith’s figure illustrates a tri-layer process sequence using one
`
`composite image instead of 3-4 discrete images as in the figures above. EX1050,
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`¶18; EX2018, 18-19 (Ref. [7]), 33 (Refs. [53], [56]).
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`8
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`The specification does not consistently use “mask” in the manner IPB
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`suggests, and three inconsistent examples do not redefine the term “mask.”
`
`EX1050, ¶¶20-28; Markman v. Westview Instruments, Inc., 52 F.3d 967, 980 (Fed.
`
`Cir. 1995) (“[A]ny special definition given to a word must be clearly defined.”);
`
`see also EX1050, ¶¶20-28. “The patentee cannot rely on its own use of inconsistent
`
`and confusing language in the specification to support a broad claim construction
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`which is otherwise foreclosed.” Trs. of Columbia Univ. v. Symantec Corp., 811
`
`F.3d 1359, 1366 (Fed. Cir. 2016); see also Bayer CropScience AG v. Dow Agro
`
`Sciences LLC, 728 F.3d 1324, 1328-29 (Fed. Cir. 2013).
`
`IPB has no basis for asserting the district court would have applied the
`
`construction differently. The district court never addressed this issue.
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`3.
`
`Even if the Board applies the construction the way IPB
`advocates, IPB’s priority claim fails.
`
`Although the Board denied claim 10 entitlement to priority before March 23,
`
`19993 (Paper 11, 21-26), IPB recycled its flawed argument that “claim 10 is fully
`
`supported under §112 ¶1 by at least the third embodiment variant disclosed in [JP]
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`’371.” Paper 19, 20.
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`
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`3 IPB does not allege earlier priority for claim 12.
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`9
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`IPR2016-01377
`Patent 6,197,696 B1
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`Step i) of claim 10 requires “dry-etching the fourth insulating film using . . .
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`the mask pattern as a mask,” but layer 358 ( “mask pattern”) is not a mask for
`
`etching layer 355 (“fourth insulating film”). Instead, “the second silicon dioxide
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`film 355 and the organic film 354 are sequentially dry-etched using the second
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`resist pattern 359 as a mask.” EX1014, ¶93, Fig. 16(a);4 EX2012, 38:10-13.
`
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`EX1014, Fig. 16(a)
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`
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`IPB argues JP ’371 discloses step i) through a description of how to mitigate
`
`misalignment damage (Paper 19, 24-27 (see figures below); EX2012, 39:12-23),
`
`but this description actually contradicts IPB’s position. EX1050, ¶¶30-33.
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`
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`4 Although TSMC does not believe its translation to be in error, none of
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`IPB’s alleged inconsistencies affects TSMC’s arguments.
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`
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`10
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`The specification identifies layer 359, not layer 358, as the mask for etching
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`layer 355 above. EX2012, 39:12-16 (“[T]he mask pattern 358 should be dry-
`
`etched using the second resist pattern 359 as a mask before the second silicon
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`dioxide film 355 is dry-etched using the second resist pattern 359 as a mask.”). In
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`fact, the sole purpose of the process is to eliminate exposed portions of layer 358
`
`so it does not act as a mask. EX1014, ¶96; EX2012, 39:16-21; EX1050, ¶31. By
`
`leaving the exposed portions of layer 358 in place, layer 358 would define a
`
`narrower via than designed, causing increased contact resistance, void formation
`
`during metallization, reduced reliability, and failed contacts. EX1001, 13:51-55,
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`Fig. 6(c); EX1050, ¶31.
`
`IPB offers no reason a POSITA would have thought layer 358, which
`
`contains the wiring pattern, would define the via pattern, especially when the goal
`
`of the process is to faithfully reproduce the via pattern from layer 359 in layer 355.
`
`EX1014, ¶93; EX2012, 38:13-17; EX1050, ¶32. EX1050, ¶¶29-33. The following
`
`images show the plan view corresponding to the process IPB describes, and
`
`confirm that only layer 359 defines the area etched in layer 355. EX1014, ¶¶93, 96;
`
`EX2012, 38:13-17, 39:12-16; EX1050, ¶32.
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`11
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`This situation differs from the all of the examples in the specification IPB
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`suggests are buried “masks.” In those examples, the buried layer contains the same
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`pattern as the top layer. In contrast, buried layer 358 above contains the wiring
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`pattern, and top layer 359 contains the via pattern. IPB provides no evidence a
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`buried layer containing a different pattern than the top layer is a mask as IPB’s
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`priority argument requires. EX1050, ¶33.
`
`JP ’371 also fails to disclose step j) of claim 10. EX1050, ¶¶34-36. The
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`image below illustrates IPB’s flawed argument to the contrary. See Paper 19, 27-
`
`28.
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`12
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`IPB suggests layers 359 (not shown) and 355 together define areas for
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`etching layer 354, but JP ’371 states that only layer 359 is the mask for etching
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`layer 354. EX1014, ¶93. When JP ’371 explains layer 359 acts as a mask for
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`etching layer 354 and “is removed during the step of etching the organic film 354”
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`(EX1014, ¶93; EX2012, 38:13-19), it does not mean layer 355 is exposed partway
`
`through the etch to act as a mask. Because only layer 359 is identified as a mask
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`(and not layer 355), a POSITA would have understood layer 354 is fully patterned
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`before layer 359 is completely removed. EX1050, ¶¶35-36. This is consistent with
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`a well-known “overetch” technique (see below) often used to remove residual
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`material over stepped structures as in JP ’371. EX1031, 28 (“[O]veretching is also
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`required to remove residual film from steps.”); EX1050, ¶36.
`
`
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`If, as IPB suggests, layer 355 were a mask for etching layer 354, it would be
`
`identified as such together with layer 359 the way JP ’371 identifies both layers
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`355A and 354A as masks for etching layer 353 (see below). EX1014, ¶94, FIGS.
`
`16(b), 16(c). Unlike layer 359, layer 355A is relatively thin and is eliminated
`
`before layer 353 is fully patterned. Id. This leaves layer 354A exposed to act as a
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`13
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`mask partway through the etch, consistent with the Board’s use of “mask.” See
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`Paper 11, 18 n.7. This does not happen with layer 355 while layer 354 is being
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`etched (see above).
`
`Claim 10 is not entitled to a priority date before March 23, 1999, and Grill
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`
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`remains prior art.5
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`4.
`
`Grill benefits from the filing date of the ’628 application
`because that application supports Grill’s claim 28.
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`Even if claim 10 were entitled to the filing date of JP ’371, Grill would
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`remain prior art to the challenged claims because it is entitled to the filing date of
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`its parent ’628 application, filed before JP ’371. The ’628 application contains all
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`of Grill’s relevant teachings and supports Grill’s claim 28.6 See Drinkware, 800
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`F.3d at 1381-82.
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`
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`5 JP ’371 does not support dependent claim 11 for the same reasons it does
`
`not support independent claim 10.
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`6 The Board recognizes Grill’s §102(e) date is the filing date of its parent if
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`the parent supports one of Grill’s claims. See Paper 19, 37 n.18.
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`14
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`The table below shows the ’628 application’s support for Grill’s claim 28,
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`establishing Grill’s §102(e) date as January 16, 1998. See also EX1050, ¶¶37-54.
`
`Grill Claim 28
`
`A method for forming
`an interconnect
`structure on the upper
`surface of a substrate
`having conductive
`regions comprising the
`steps of:
`
`forming over said
`substrate a first
`dielectric layer having
`a thickness
`corresponding to the
`thickness of an
`interconnect via,
`
`
`forming over said first
`dielectric layer a
`second dielectric layer
`having a thickness
`corresponding to the
`thickness of an
`interconnect wiring
`layer,
`
`
`forming a first hard
`mask layer over said
`second [dielectric]
`layer,
`
`’628 application
`
`See below.
`
`EX1049, 15:11-12, 12:31-40.
`
`
`EX1049, 15:11-12, 12:31-40.
`
`EX1049, 15:11-13.
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`15
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`EX1049, 15:11-22.
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`EX1049, 15:17-18.
`
`forming a second hard
`mask layer over said
`first hard mask layer,
`said second hard mask
`layer preferably formed
`of a material different
`from said first hard
`mask to permit
`selective etching of said
`second hard mask
`layer with respect to
`said first hard mask
`layer,
`
`forming a first layer of
`resist over said second
`hard mask layer,
`
`
`EX1049, 15:17-18.
`
`patterning said first
`layer of resist with a
`wiring pattern,
`
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`16
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`patterning said second
`hard mask layer using
`said wiring-patterned
`first layer of resist as a
`mask,
`
`
`EX1049, 15:19-22.
`
`
`
`
`
`
`
`EX1049, 15:17-22.
`
`removing said wiring-
`patterned first layer of
`resist,
`
`
`
`
`Layer 58 may be SiO2 (EX1049, 15:14-17), and a
`POSITA would have known photoresist layer 60
`would resist an SiO2 etch, requiring subsequent
`removal. EX2020, 44-45 (“[T]he durability of
`commonly used positive resists is quite high,
`especially those used for the selective etching of
`SiO2 and Si3N4.”).
`EX1049, 15:23-24.
`
`17
`
`forming a second layer
`of resist over said first
`and second hard mask
`
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`layer,
`
`
`EX1049, 15:23-24.
`
`patterning said second
`layer of resist with a
`via pattern,
`
`
`
`
`
`
`
`
`EX1049, 15:25-26.
`
`EX1049, 15:29-30.
`
`patterning said first
`hard mask layer using
`said via-patterned
`second layer of resist
`as a mask,
`
`
`transferring said via
`pattern in said patterned
`first hard mask layer
`into said second
`dielectric layer, while
`concurrently removing
`said via-patterned
`second layer of resist,
`and
`
`
`
`
`
`
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`18
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`patterning said via-
`patterned first hard
`mask layer using said
`wiring-patterned
`second hard mask
`layer as a mask,
`
`transferring, at least
`partially concurrently,
`said via pattern into
`said first dielectric
`layer to form via
`cavities corresponding
`to said via pattern, and
`said wiring pattern
`into said second
`dielectric layer to form
`wiring cavities
`corresponding to said
`wiring pattern, and
`
`filling said cavities with
`conductive material to
`make electrical contact
`with said conductive
`
`Although Grill added a statement that the
`“[p]atterned second resist layer 62 is absent from
`FIG. 5F because it is typically removed by the
`etching process used to pattern dielectric 12,” a
`POSITA understood this to be part of the disclosure.
`Photoresist layer 62 is concurrently removed while
`etching DLC layer 12 because they have similar etch
`characteristics. EX1049, 11:12-15, 12:37- 39, 15:23-
`24; see also EX1010, 6:43-53, 7:30-46, 8:9-18;
`EX1039, 6:19-26; EX1037, 13:54-59; EX1038,
`1:30-35.
`
`EX1049, 15:30-32.
`
`
`
`
`
`EX1049, 15:32-34.
`
`
`
`EX1049, 15:34-35.
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`regions and to form
`said vias and said
`wiring pattern.
`
`
`
`
`
`The only element of claim 28 IPB challenges is the step of concurrently
`
`removing the via-patterned photoresist. Paper 19, 38-50; EX1005, 13:47-50
`
`(“transferring said via pattern in said patterned first hard mask layer into said
`
`second dielectric layer, while concurrently removing said via-patterned second
`
`layer of resist”). IPB argues a POSITA would not have understood layer 62 (“via-
`
`patterned second layer of resist”) to be removed while patterning layer 12 (“second
`
`dielectric layer”) in the process shown below from the ’628 application.
`
`
`
`Layer 62 is photoresist, and layer 12 is a carbon-based material, such as
`
`diamond-like carbon (DLC) or fluorinated DLC. EX1049, 12:37-38, 15:23-24. The
`
`’628 application explains photoresist and carbon-based dielectrics like DLC “have
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`similar etch characteristics” (EX1049, 11:12-15), so a POSITA would have known
`
`any process for patterning/etching layer 12 concurrently removes layer 62.7
`
`EX1050, ¶46.
`
`Even without this explicit teaching, a POSITA would have understood
`
`photoresist layer 62 is removed while patterning carbon-based layer 12 because of
`
`their similar etch properties. See, e.g., EX1037, 13:54-59 (“[T]he silicon oxide film
`
`can be etched until the DLC film 44 is exposed without removing the resist. It may
`
`then be removed at the same time that the DLC film 44, the amorphous carbon
`
`fluoride film 43, and the DLC film 42 are etched.”); EX1010, 6:43-53 (“[T]he
`
`photoresist strip step can cause the removal of some of the low- material of layer
`
`14 residing below the opening 17, as shown in FIG. 5.”), 7:30-46, 8:9-18; EX1039,
`
`6:19-26 (“[P]hotoresist mask 44 used to define the opening within dielectric layer
`
`40 is removed at the same time that dielectric layer 40 is etched.”); EX1038, 1:30-
`
`35 (“[O]rganic material layer 2 is etched off anisotropically and resist layer 4 is
`
`removed as shown in FIG. 1(b).”); EX1050, ¶¶47-52.
`
`
`
`7 IPB insists Grill’s claim 28 “requires ‘removing’ an entire layer” (Paper
`
`19, 43”), but claim 28 reads “while concurrently removing,” indicating the removal
`
`process need not be completed. The ’696 patent also uses “removing” to include
`
`partial removal. EX1001, 11:19-31, 23:51-65, 26:3-14, 28:55-67, 30:62-31:6.
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`From the layer chemistries the ’628 application discloses and describes, a
`
`POSITA would have understood photoresist layer 62 is removed while patterning
`
`carbon-based layer 12. EX1050, ¶53.
`
`IPB denies the ’628 application discloses concurrent removal of layer 62
`
`because Grill added a sentence that reads, “Patterned second resist layer 62 is
`
`absent from FIG. 5F because it is typically removed by the etching process used to
`
`pattern dielectric 12.” EX1005, 7:64-66. This sentence, though, merely confirms
`
`that it would be unusual not to remove layer 62 while patterning layer 12. This
`
`adds nothing to the disclosures of the ’628 application, which already explains
`
`layers 62 and 12 have similar etch characteristics. EX1049, 11:12-15. As such, the
`
`new sentence is a clarification, not new matter. See TurboCare Div. of Demag
`
`Delaval Turbomachinery Corp. v. General Elec. Co., 264 F.3d 1111, 1118 (Fed.
`
`Cir. 2001) (“[T]he amendment served merely to clarify that [certain elements]
`
`were not illustrated.”) (reversing summary judgment premised on finding new
`
`matter); EX1050, ¶53.
`
`B. A POSITA would have been motivated to combine Grill and
`Aoyama with a reasonable expectation of success.
`
`Aoyama is one of many references that disclose well-known technology for
`
`making vias. See, e.g., EX1040, 2:64-3:45, FIGS. 1-4; EX1041, 3:39-45, FIG. 6.
`
`22
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`IPR2016-01
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