US007190234B1
`
`C
`(12; Umted States Patent
`Dye et al.
`
`am Patent No.:
`(45) Date of Patent:
`
`US 7,190,284 B1
`Mar. 13, 2007
`
`(54) SELECTIVE LOSSLESS, LOSSY, OR NO
`CTOMPRESSION OF DATA BASED ON
`
`4.881.025 A
`4.903.317-" A "
`
`ll.-‘I989 Wang
`231990 Nishihztra el al.
`
`.
`
`
`
`341.-“S7
`358.-1.9
`
`1.-Z1991 Leveritc ct al.
`::i:z3:
`t!.:::::::::::~
`6:199; Whnlng CH1‘
`8-1992 Yoshtda et a].
`el Ell‘
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`395.-‘"888
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`711.444
`395.6250
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`358426
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`358.-'468
`
`341-"51
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`
`(76)
`
`( “ ] Notice:
`
`Inventors: Thomas A. Dye, 6621 Candle Ridge
`.
`.
`LOVe, A1lSt1l'1_. TX
`Manuel
`J. Alvarez, II. 8800 Pepper Rock l)r..
`Austin. TX (US) 78717: Peter Geigelfi
`10407 Treasure Island Dr._. Austin. TX
`(US) 78730
`Stlhjccl-10 ally disclaimer. the term oflhis
`patent is extended or E:lC1_]llS1.CC1 under 35
`I
`I
`I
`5
`I
`USC 1 4(1)) by Odays
`
`_
`(211 Al’p1‘N“" "9’239°659
`.
`(223 F‘l"d'
`
`J3“-211999
`Related U-S- A1JP“I==Ifi0n Data
`(63) Continuation—in—part of application No. 081916.464.
`)
`.
`filed o11Aug. 8. 1997. now 1 at. No. 6.173.381. Wl]lC11
`is a continuation-in-palll of applicalioll No. (187465.
`106. filed on Jan. 5, 1925, now abandoned. winch IS
`a cont1nuat1on—1n—part of application No. 081340.667.
`filed on Nov. 16, 1994. now Pat. No. 6.002.411.
`
`(51)
`
`Int, C],
`H0334’ 7/30
`Sow/av
`(52) U.S.(.‘l.
`
`(200601)
`<2oo6~on
`34];‘5];34lf87:7l()i’68:
`7111470; 3821232; 382E233-,382f244
`Field of Classification Search
`3827232.
`382a"2?-3.244; 710.168; 7097247; 341151.
`341187; 7l].u"l70
`Sec application 1111:: for complete SL“dDCl'l history.
`
`(58)
`
`(56)
`
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`_.
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`711,.-Q03
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`
`
`
`APPLE 1009
`
` 1
`
`APPLE 1009
`
`1
`
`

`
`5.572.206 A
`5.577.248 A
`5,584.008 A
`5,590,047 A *
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`
`1251999 Dye
`1251999 Chadez
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`
`
`
`395-"497.04
`395.5670
`
`3755240.15
`71051
`
`710.5100
`
`3455521
`358.5l.l5
`
`358542602
`
`236.592 B
`
`348520799
`
`l5ORl'€l(}N PA'l‘l'lN'l‘ I)O('_‘.UMl"lN'l‘S
`
`EP
`JP
`W0
`
`0 702 457
`05204747 A ’“
`95.5 19662
`
`351996
`8.51993
`7.51995
`
`OTHER PUBLICATIONS
`
`Brenza. “Synonym Avoidance Cache.“ IBM Technical Disclosure
`Bulletin. vol. 34. No. 1. Jun. 1991. pp. 377-381.
`International Search Report tor Application No. PC'T5US 00.502355.
`mailed Jun. 16. 2000.
`U.S.App1. No. 08.5463.106. filed Jun. 5. 1995. Dye.
`
`US 7,190,284 B1
`Page 2
`
`711.5114
`700.5214
`35851.15
`3585404
`
`
`
`375.-5240.05
`
`U.S. Appl. No. 605144.125. filed Jul. 16. 1999. Dye.
`US. Appl. No. 095491343. filed Jan. 26. 2000, Dye.
`U.S, Appl. No. 095818283. filed Mar. 27, 2001, Dye.
`Yabe ct al., Compression5Dccompression DRAM for Unified
`Memory Systems: A 16 M11. 200l\-'11-1'/.. 90°/o to 50% Graphics-
`Ba.ndwidl.h Reduction Prototype. IEEE 1998 So1id—Sla.le Circuits
`Conference, Feb. 1998. pp. 342-343.
`Kjclso ct al.. Design and Performance of a Main Memory Hardware
`Data Compressor. Etlrohdiero 96 Conference. lEF,F.. %p. 1996. pp.
`423-430.
`
`3955308
`3825232
`
`” cited by examiner
`
`Primary Exam5rzer—H0ng Kiln
`
`35851.16
`
`(57)
`
`ABS'1"RAC’1‘
`
`An integrated memory controller (IMC) including Memo-
`ryF5X Technology which includes data compression and
`decompression engines for
`improved performance. The
`memory controller (IMC) oftlie present invention preferably
`selectively uses a combination of losslcss,
`lossy, and no
`compression modes. Data transfers to and from tl1e inte-
`grated memory controller of the present invention can thus
`be in a plurality of formats,
`these being compressed or
`normal [non-compressed), compressed lossy or lossless, or
`compressed with a combination of lossy and lossless. The
`invention also indicates preferred methods for specific C0111-
`pression and decompression of particular data formats such
`as digital video, 31) textures and image data using a com-
`bination of novel lossy and lossless compression algorithms
`in block or span addressable formats. To improve latency
`and reduce perfomtance degradations normally associated
`with compression and decompression techniques.
`the
`Memorylifx Technology encompasses multiple novel tech-
`niques such as: 1) parallel lossless comp1'ession5deI:ompres-
`sion; 2) selectable compression modes such as lossless.
`lossy or no compression; 3) priority compression mode; 4)
`data cache teclmiques; 5) variable compression block sizes;
`6) compression reordering; and 7) unique address transla-
`tion. attribute, and address caches. The parallel compression
`and decompression algorithm allows high-speed parallel
`compression and high speed parallel decompression opera-
`tion. The IMC also preferably uses a special memory
`allocation and directory technique for reduction oftable size
`and low latency operation. The integrated data compression
`and decompression capabilities of the IMC remove system
`bottle—necks and increase performance. This allows lower
`cost systems due to smaller data storage, reduced bandwidth
`requirements. reduced power and noise.
`
`16 Claims, 34 Drawing Sheets
`
`2
`
`

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`U.S. Patent
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`Mar 13, 2007
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`U.S. Patent
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`Mar. 13, 200?
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`Sheet '.+' of 34
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`US 7,190,234 B1
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`Parallel Compression
`
`Maintain a history table
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`Fig. 7
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`9
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`
`U.S. Patent
`
`Mar. 13, 2007
`
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`
`U.S. Patent
`
`Mar. 13, 200?
`
`Sheet 11 of 34
`
`US 7,190,284 B1
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`

`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 12 of 34
`
`US 7,190,284 B1
`
`
`
`Send out
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`
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`Done
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`N0
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`No
`
`Send out data 0
`M
`
`14
`
`

`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 13 of 34
`
`Us 7,190,284 B1
`
`Entry
`
`012345s7a9101112131415
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`
`Input 03:0
`
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`1
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`
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`13
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`16
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`U.S. Patent
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`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 16 of 34
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`Us 7,190,284 B]
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`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 17 of 34
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`US 7,190,284 B1
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`U.S. Patent
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`Sheet 19 of 34
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`US 7,190,234 B1
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`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 20 of 34
`
`Us 7,190,284 B1
`
`Compression of received data
`
`Receive uncompressed data
`
`£10.21
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`Determine a compression mode
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`§€L4.
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`compression mode information with
`the data
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`
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`
`

`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 21 of 34
`
`US 7,190,284 B1
`
`Access compressed data
`
`Receive a request for the data
`.&1_2
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`Access the data from the memory
`QM.
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`Determine a compression mode
`for the data
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`Selectively decompress the data
`according to the compression mode
`flfi
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`Provide the data in response
`to the request
`
`§Z0.
`
`Fig. 23
`
`23
`
`23
`
`

`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 22 of 34
`
`US 7,190,284 B1
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`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 23 of 34
`
`Us 7,190,284 B]
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`

`
`U.S. Patent
`
`Mar. 13, 200?
`
`Sheet 24 of 34
`
`US 7,190,234 B1
`
`@Memory Allocation
`(lnitialized CATT)
`2709
`
`271 1
`
`Allocate CATT Ent
`
`Arrange entry order
`(if required based on istarllend address)
`
`271
`
`Set the compression type
`271 5
`
`Al|ocate% of the requested memory
`(Based on block sizg a1nd compression type)
`
`7 7
`
`Set the data pointer to start at the initial block
`in the CATT
`2?19
`
` Allocate Overflow Address memory (OAM)
`
`(Set by IMC driver or BIOS)
`
`
`Typically 118th ogginal data size
`
`
`2? 1
`
`Initialize the OAT pointer in the GATT
`2723
`
`Initialize allocated memory headers to zero
`2725
`
`
`
`Initialize OAT entries, set overflow
`pointer in OAT
`2727
`
`
`
`
`Fig. 26
`
`26
`
`26
`
`

`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 25 of 34
`
`US 7,190,284 B1
`
`
`
`
` @Compressed
`Memory Store (Addr N)
`2749
`
`Yes
`
`
`Check
`Cache for Hit
`
`While searching CATT
`
`
`
`
`E N
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`o
`
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`H = Header
`Calculate Initial Address I. continue to
`from Address I
`compress data (Validate present entry)
`2759
`2733
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`
`
`
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`
`
`(391 Next
`Address (U:f(H))
`2799
`
`
`
`Remaining
`Compressed block
`>Block SIZE?
`
`
`Store block of Compressed data at
`address 1 with headeI=LAST
`
`2737
`
`
`
`Store block of Compressed data at
`address I with header(U) Set |=U
`2739
`
`
`
`header of H to UNUSED Set H=f(H2)
`2745
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`
`Q H2=HeaderfromAddressHSet
`
`
`Yes
`
`Store uncompressed block and header
`at Add N in cache and set most
`recently modified bit for cache
`as
`
`Done
`
`Fig. 27
`
`27
`
`27
`
`

`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 26 of 34
`
`Us 7,190,284 B1
`
`-
`Deliver daI2t%Ig£0m cache
`1
`
`
`
`
`@Memory Fetch
`(address N)
`2?59
`
`
`
`
`Yes
`
`
`Search
`cache Directory HIT?
`
`2751
`
`
`
`No
`
`Solve for initial address (I) = (Matching
`
`CATT start address - N)t')( (X is based on data type)
`
`2}’53
`
`Fetch from memory
`compressed block I
`2755
`
`Strip the Header bits, and decompress
`the remaining data from I
`2757
`
`LAST Block?
`2?61
`
`No
`
`Yes
`
`
`
`Fetch the overflow block using the
`overflow pointer as base and the
`header as offset
`Mi
`
`Read oompressed overflow blocks
`2756
`
`Send decompressed data to
`requesting agent
`2765
`
`Update Cache, invalidate LRU_ mark
`new block as MRU
`2769
`
`Completed compressed
`read operation
`
`Fig 28
`
`28
`
`28
`
`

`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 27 of 34
`
`US 7,190,284 B1
`
`
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`mmeuum:3.35._..__5E5552.5;m_.___=_._m9esm.coEmE__soEmsohozoosam:2m8__¢
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`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 28 of 34
`
`Us 7,190,284 B1
`
`8mm
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`30
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`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 29 of 34
`
`Us 7,190,284 B]
`
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`31
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`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 30 of 34
`
`Us 7,190,284 B1
`
`'1"
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`V— v— 1— 1— 1* "l— 1.— C\|
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`32
`
`
`
`
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`
`
`BytesCompressed
`
`BitsUsed
`
`Count
`
`Index
`
`Flag
`
`32
`
`

`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 31 of 34
`
`US 7,190,284 B1
`
`Input Data 8 Bytes
`
`
`
`
`
`
`
`
`
`
`
`
`‘
`
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`
`Data
`Vaiid
`
`Data Bytes
`0
`7
`
`
`
`Stage 3: Calculate Final Selects
`
`Final Selects
`.
`.
`.
`.
`.
`
`. 15
`
`flfifis
`
`History Window
`
`Fig. 33
`
`33
`
`
`
`Pie Reister 128 bits
`
`Stage 4: Data Selection
`0
`“ta ”‘
`15
`
`
`
`Start Count
`0
`7
`
`Index
`
`0
`
`7
`
`Index
`Valid
`
`
`
`Stage 1: Initial input Seiector and Byte Counter
`
`
`
`
`
`Pie R ister 168 bits
`
`Stage 2: Calculate Initial Selects and Overftows
`
`Partial Selects and Overfiows
`0
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`.
`.
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`. 15
`
`Pie Reister 144 bits
`
`
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`
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`
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`
`33
`
`

`
`U.S. Patent
`
`Mar. 13, 2007
`
`Sheet 32 of 34
`
`US 7,190,284 B1
`
`Input Data
`D0:D63
`
`D0:
`D24
`
`D9: D10: D13: D25:
`D3:
`D63 D63 D6
`D63 D63
`
`25521
`
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`
`E55
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`
`E9:
`E55
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`E55
`E55
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`
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`
`Data Index
`Byte
`
`Start Counts
`
`Data Index
`Byte
`
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`By1e
`
`25535
`
`Fig. 34
`
`34
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`H9:
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`Data Index
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`
`4
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`—ec0der2
`
`Data Index
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`
`4
`
`coum
`
`34
`
`

`
`U.S. Patent
`
`r.aM
`
`7...002m
`
`43fl033w_..HS
`
`US 7,190,284 B1
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`
`US ?,l90,284 B1
`
`1
`Slill.l4l(I'I‘lVE L()SSLESS, l.()SSY., OR NO
`COMPRESSION OF DATA BASED ON
`ADDRESS RANGE, DATA TYPE, AND.-‘OR
`REQUESTING AGENT
`
`(T()NTINUATI()N DATA
`
`This application is a continuation—in—part (CIP) ofSer. No.
`08i’9l6,464,
`filed Aug. 8, 1997. and now U.S. Pat. No.
`6,173,381, isstted on Jan. 9. 2001'.
`which is a continuation-in-part (CIP) of Ser. No. 08.I’463.
`106, filed Jun. 5, 1995, now abandoned;
`which is a continuation—in—part (CIP) of Ser. No. 08:840.
`667. filed on Nov. 16, 1994. which is now U.S. Pat. No.
`6.(l{)2,4ll, issued on Dec. 14. I999.
`
`l-'IIiI,l) OF TIIl.i IN\r’l_iN'l"I()N
`
`The present invention relates to computer system archi-
`tectures. and more particularly to a memory controller which
`includes an embedded data compression and decompression
`engine for the reduction of system bandwidth and improved
`efliciency.
`
`DI€S(IRlP'l‘I()N ()l"' Tlll-5 RI.£I..A'l'IilJ ART
`
`Since their introduction in I98]. the architectttre of pe -
`sonal
`computer
`systems
`has
`remained
`substantially
`unchanged. The current state of the art in cotnputer system
`architectures includes a central processing unit (CPU) which
`couples to a memory controller interface that in turn couples
`to system memory. The computer system also includes a
`separate graphical interface for coupling to the video dis-
`play. In addition, the computer system includes inputfoutput
`(IEO) control
`logic for various U0 devices.
`including a
`keyboard. mouse. floppy drive, hard drive, etc.
`I11 general. the operation of tnodern computer architecture
`is as follows. Programs and data are read from a respective
`IEO device such as a floppy disk or hard drive by the
`operating syste1n._ and the programs and data are temporarily
`stored in systetn memory. Once a user program has been
`transferred into the system memory. the CPU begins execu-
`tion of the program by reading code and data from the
`system memory through the memory controller. The appli-
`cation code and data are presumed to produce a specified
`result when manipulated by the system CPU. "lhe (TPU
`processes the code and data. and data is provided to one or
`tnore of the various output devices. The computer system
`may include several output devices, including a video dis-
`play. audio (speakers). primer. etc. In most systems.
`the
`video display is the primary output device.
`Graphical output data generated by the CPU is written to
`a graphical interface device for presentation on the display
`monitor. The graphical interface device may simply be a
`video g;I'aphics array (VCIAJ card. or the system may inchtde
`a dedicated video processor or video acceleration card
`including separate video RAM (\r"RAM].
`111 a computer
`system including a separate, dedicated video processor, the
`video processor includes graphics capabilities to reduce the
`workload of the lnain CPU. Modern prior an personal
`computer systems typically inclttde a local btts video system
`based on the Peripheral Component Interconnect (PCI) bus,
`the Advanced Graphics Port (AGP), or perhaps another local
`bus standard. The video subsystem is generally positioned
`on the local bus near the CPU to provide increased perfor-
`]T]£:ll'lCC.
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`Therefore, in summary. program code and data are first
`read from the hard disk to the system memory. The program
`code and data are then read by the CPU frotn system
`memory. the data is processed by the CPU, and graphical
`data is written to the video RAM in the graphical interface
`device for presentation on the display monitor.
`The system memory interface to the memory controller
`requires data bandwidth proportional to the application and
`system requirements. Thus.
`to achieve increased system
`performance, either wider data buses or higher speed spe-
`cialty metnory devices are required. These solutions force
`additional side-effects such as increased system cost. power
`and noise.
`I"I('"r.
`1
`illustrates the data transfer paths iii a
`typical computer memory controller and system memory
`using prior art technology.
`The CPU typically reads data from system memory across
`the local bus in a normal or non—compressed format. and
`then writes the processed data or graphical data back to the
`[E0 bus or local bus where the graphical interface device is
`situated. The graphical interface device in turn generates the
`appropriate video signals to drive the display monitor. It is
`noted that prior art computer architectures and operation
`typically do not perform data compression andfor decom-
`pression during the transfer between system memory and the
`CPU or between the system memory and the local [I0 bus.
`Prior art oomputer architecture also does nothing to reduce
`the size of system memory required to run the required user
`applications or software operating system. In addition. soft-
`ware controlled compression and decompression algorithms
`typically controlled by the CPU fiir non-volatile memory
`redttction techniques can not he applied to real time appli-
`cations that require high data rates such as audio, video, and
`graphics applications. Further. CPU software controlled
`compression and decompression algorithms put additional
`loads on the CPU and CPU cache subsystems.
`Certain prior art systems utilize multiple DRAM devices
`to gain improved memory bandwidth. These additional
`DRAM devices may cost the manufacturer more due to the
`abundance of memory that is not fully utilimd or required.
`The multiple DRAM devices are in many instances included
`primarily for added bandwidth. and when only the added
`bandwidth is needed, additional cost is incurred due to the
`multiple DRAM packages. For example, ifa specific com-
`puter system or consumer computing appliance such as a
`Digital TV set-top box uses l)Rl')RAM memory and requires
`more than 1.6 Gbytesfsec of bandwidth. then the tninimum
`amount of memory for this bandwidth requirement will be
`16 Mbytes. In such a case the manufacture pays for 16
`Mbytes even if the set-top box only requires 8 Mbytes.
`Computer systems are being called upon to perform larger
`and more complex tasks that reqttire increased computing
`power. In addition, tnodern software applications require
`_ computer systems with increased graphics capabilities.
`Modern software applications include graphical user inter-
`faces (Gills) which place increased burdens on the graphics
`capabilities of the computer system. I-iurther. the increased
`prevalence of multimedia applications also demands com-
`puter systems with more powerzfiil graphics capabilities.
`Therefore, a new system and method is desired to redttce the
`bandwidth requirements required by the computer system
`application and operating software. A new system and
`method is desired which provides increased system per:lor—
`_ mance without specialty high speed memory devices or
`wider data IEO buses required in prior art computer system
`architectures.
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`SUMMARY OI" 'l‘[Ili lNV[iNTI(JN
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`US ?,l90,284 B1
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`As mentioned above, according to the present invention
`the MemoryFJ'X Technology embedded within the IMC
`includes one or more compression and decompression
`engines for compressing and decompressing data within the
`system. ln the preferred embodiment the Mernoryl7r"X Tech-
`nology comprises separate oompression and decompression
`engines. In an alternate embodiment, a single combined
`compressionfdecompression engine can be implemented.
`The IMC preferably. primarily uses a lossless data compres-
`sion and decompression scheme. |.)ata transfers to and from
`the integrated memory controller of the present invention
`can thus be in either two formats, these being compressed or
`normal (non—compressed). The IMC may also include one or
`more lossy compression schemes for audiofvideolgraphics
`data.
`
`Thus compressed data from system L"O peripherals such
`as the non—volatile memory_.
`floppy drive, or local area
`network (LAN) are decompressed in the IMC and stored
`into system memory or saved in the system memory in
`compressed fomrat. Thus, data can be saved in either a
`normal or compressed format, retrieved from the system
`memory for CPU usage in a normal or compressed format.
`or‘ transmitted and stored on a medium in a nomial or
`
`The present invention comprises a memory controller.
`also referred to as the integrated memory controller (IMC),
`which provides improved data efliciency and bandwidth.
`The memory controller includes a compressionJ'dccompres-
`sion engine, preferably parallel data compression and
`decompression slices, that are embedded into the memory
`control logic ofthe memory controller. I’L1r1l1er, the present
`invention does not require specialty memory devices or
`system software changes for operation. The rnelnory con-
`troller logic of the present invention preferably interfaces to
`the system CPU either extemal or internal to the memory
`controller. Fur1her, the memory controller interfaces to the
`main system r11ernory and other interface buses such as a
`l1igl1—speed system peripheral bus, e.g., the PCI bus or the
`AGP. Additionally the IMC may contain graphics, video
`andfor audio control functions. The IMC includes one or
`
`more symmetric memory ports for connecting to system
`memory. The IMC also may include video outputs to
`directly drive the display device, as well as an audio
`interface for digital audio delivery to an external stereo
`digital-to-analog conver1er (DAC).
`'Il're IMC includes an embedded Technology termed
`“Memoryl7r"X” desigred for the reduction ofdata bandwidth
`between the main or system memory and the memory
`controller. The MemoryFJ'X Technology reduces the band-
`width requirements while increasing the memory efliciency
`for almost all data types within the computer system. Thus.
`conventional standard (JDEC) memory devices can achieve
`higher bandwidth with less system power and noise than
`when used in conventional systems without the MemoryF:'X
`Technology.
`Tl're IMC transfers data between the local bus, the embed-
`ded MemoryFr'X Technology and system memory. In addi-
`tion,
`the IMC also transfers data between the system
`memory and the display output. Therefore, the MemoryF:'X
`technology of the present
`invention typically resides
`between the CPU local bus, peripheral interconnect buses.
`and the rrrain system memory.
`The MemoryFJ'X Technology is designed to embed into
`memory control circuits and has a novel architecture to
`compress and decompress parallel data streams within the
`computing system. In addition, the Men1oryI'U"X Technology
`has a “scalable” architecture designed to function in a
`plurality of memory configurations or compression modes
`with a plurality of performance requirements.
`The lV[emoryl"fX Technology's system level architecture
`reduces data bandwidth requirements and thus irrrproves
`memory efliciency. Eflicierrcy is improved by the reduction
`of device L"O pins between the main memory bank and the
`memory controller. Compared to conventional systems, the
`Me1r1oryl*'r"X Technology obtains equivalent bandwidth to
`conventional architectures that use wider buses, specialty
`memory devi