throbber
US007 1 8 l 608B2
`
`(12) United States Patent
`Fallon et al.
`
`(10) Patent No.:
`
`(45) Date of Patent:
`
`US 7,181,608 B2
`Feb. 20, 2007
`
`(54)
`
`(75)
`
`SYSTEMS AND METHODS FOR
`ACCELEILATED LOADIN G OF OPERATING
`SYSTEMS AND APPLICATION PROGRAMS
`
`Inventors: James J. Fallon, Arrnonk, NY (US);
`John Buck, Oceanside, NY (US); Paul
`F. Pickel, Bethpage, NY (US); Stephen
`J. MeEerlain, New York, NY (US)
`
`(73)
`
`Assignee:
`
`Realtime Data LLC, New York, NY
`(US)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 223 days.
`
`(21)
`
`Appl. No.: 09/776,267
`
`(22)
`
`Filed:
`
`Feb. 2, 2001
`
`(65)
`
`(60)
`
`(51)
`
`(52)
`(58)
`
`(56)
`
`Prior Publication Data
`
`US 2002/0069354 A1
`
`Jun. 6, 2002
`
`Related U.S. Application Data
`
`Provisional application No. 60/ 180,114, filed on Feb.
`3, 2000.
`
`Int. Cl.
`G06F 9/24
`
`(2006.01)
`(2006.01)
`G06F 9/00
`(2006.01)
`G06F 13/00
`U.S. Cl.
`.............................. .. 713/2:713/1;711/113
`Field of Classification Search .................. .. 713/2,
`713/], 100; 711/170, 118,113
`See application file for complete search history.
`References Cited
`
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`OTHER PUBLICATIONS
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`IBM, Fast Dos Soft Boot, Feb. 1, 1994, vol, 37, Issue 2B, pp.
`185-136.*
`
`(Continued)
`
`Primary E.mn'n’ner—Thon1as Lcc
`Assistant Examz'ner—Suresh K Suryawanshi
`(74) Attorney, Agent, or Fz'rm—Fish & Neave IP Group of
`Ropes & Gray LLP
`
`(57)
`
`ABSTRACT
`
`Systems and methods are provided for accelerated loading
`of operating system and application programs upon system
`boot or application launch. In one aspect, a method for
`providing accelerated loading of an operating system
`includes maintaining a list of boot data used for booting a
`computer system, preloading the boot data upon initializa-
`tion of the computer system, and servicing requests for boot
`data from the computer system using the preloaded boot
`data. The boot data may comprise program code associated
`with an operating system of the computer system, an appli-
`cation program, and a combination thereof. The boot data is
`retrieved from a boot device and stored in a cache memory
`device. The boot data is stored in a compressed format on the
`boot device and the preloaded boot data is decompressed
`prior to transmitting the preloaded boot data to the request-
`ing system.
`
`4,127,518 A
`
`ll/1978 Coy eta].
`
`31 Claims, 13 Drawing Sheets
`
`DATA
`COMPRESSION
`ENGINE
`
`
`
`APPLE 1001
`
`1
`
`APPLE 1001
`
`

`
`US 7,181,608 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
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`
`D>B>>Il>D>I>>>D>>>21>II>iI>>>>I1>D>i>II>D>>>D>>il>>i1>iI>>>>>>il>I1>D>>D>>>>D>il>iI>>.>>>3>I>i>D>I>>>D>>D>il>iI>D>II>>>I1>>D>I1>{I>
`
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`
`>-3>il>>D>B>>>3>>3>B>Il>>D>>>>D>>D>3>>>>>>3>>>D>>>1?->>>Il>>3>>3>>L1>>>B>>>>3>>>D>>>>B>>i1>>>D>>>>3>>>B>>>>
`
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`2
`
`

`
`US 7,181,608 B2
`Page 3
`
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`6,463,509
`6,487,640
`6,489,902
`6,513,113
`6,529,633
`6,539,456
`6,542,644
`
`i>>I1>I1>I>>.>>>I1>>i>iI>I>>>D>>>3>3>i>D>>>D>Cl>3>>D>>D>>>>>il>>D>>
`
`>3
`
`B1
`B1
`B1'’'‘
`B1
`B1
`B1
`B1"‘
`B1*
`B1
`B1
`B1
`B1
`B1
`B1
`B1
`B1
`B1
`B1
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`
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`
`* cited by examiner
`
`3
`
`

`
`U.S. Patent
`
`US 7,181,608 B2
`
`
`
`
`
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`
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`
`4
`
`
`

`
`U.S. Patent
`
`Feb. 20,2007
`
`Sheet 2 of 13
`
`US 7,181,608 B2
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`Sheet 6 of 13
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`Us 7,181,608 B2
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`ENSURE ENOUGH 58
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`DELAY FOR VOLATILE
`|I_I\(I)I'T||AI;Ll|)ZIA\'(f|IT)T\I
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`54
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`PROGRAMMABLE
`LOGIC
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`DATA BYTE DELAY 20 nsec
`DEVICE
`
`9
`
`

`
`U.S. Patent
`
`Feb. 20, 2007
`
`Sheet 7 of 13
`
`Us 7,181,608 B2
`
`
`
`
`
`
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`DSP READ LAST
`DATA BYTE & LATCH INTO
`
`VOLATILE LOGIC
`DEVICE
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`DEVICE TO ENSURE
`
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`CONTINUE DATA STORAGE
`CONTROLLER
`INITIALIZATION
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`68
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`FLAG ERROR
`REPEAT
`ENTIRE PROCESS
`
`
`
`FIG. 6b
`
`10
`
`10
`
`

`
`U.S. Patent
`
`Feb. 20, 2007
`
`Sheet 8 of 13
`
`Us 7,181,608 B2
`
`
`
`
`
`RETREIVE REQUESTED
`BOOT DATA FROM DISK
`
`
`
`BOOT PROCESS
`
`COMPLETE
`
`?
`
`
`
`11
`
`

`
`U.S. Patent
`
`Feb. 20, 2007
`
`Sheet 9 of 13
`
`Us 7,181,608 B2
`
`75
`
` POWEFI-UP
`OR SYSTEM
`
`RESET
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`YES '
`75
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`77 RETRIEVE & READ LIST
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`PREFETCH DATA BLOCKS
`SPECIFIED IN LIST
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`78
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`79 COMMENCE BOOT PROCESS
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`RECEIVE READ REQUEST
`FOR BOOT DATA
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`0
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`BOOT DATA NOT PREVIOUSLY
`SPECIFIED IN LIST
`
`12
`
`

`
`U.S. Patent
`
`Feb. 20, 2007
`
`Sheet 10 of 13
`
`Us 7,181,608 B2
`
`
`
`RECEIVE REQUEST FOR APPLICATION
`
`DATA ASSOICATED WITH
`
`LAUNCHED APPLICATION
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`LAUNCH
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`PROCESS
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`
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`?
`
`STORE LIST
`
`FIG. 8a
`
`13
`
`13
`
`

`
`U.S. Patent
`
`Feb. 20, 2007
`
`Sheet 11 of 13
`
`Us 7,181,608 B2
`
`
`
`APPLICATION
`LAUNCHED
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`APPLICATION
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`DATA PREVIOUSLY
`
`SPECIFIED IN LIST
`
`
`
`FIG. 8b
`
`14
`
`14
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`

`
`U.S. Patent
`
`Feb. 20, 2007
`
`Sheet 12 of 13
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`Us 7,181,608 B2
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`US 7,181,608 B2
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`US 7,181,608 B2
`
`1
`SYSTEMS AND METHODS FOR
`ACCELERATED LOADING OF OPERATING
`SYSTEMS AND APPLICATION PROGRAMS
`
`(IR()SS-RlCl"lLRIINCH 'l'() Rll,I.A'l'|",])
`APPLICATION
`
`This application is based on a U.S. provisional application
`Ser. No. 60/180,114, filed on Feb. 3, 2000, which is fully
`incorporated herein by reference.
`
`BACKGROUND
`
`1. Technical Field
`
`The present invention relates generally to systems and
`methods for providing accelerated loading of operating
`system and application programs upon system boot or
`application launch and, more particularly, to data storage
`controllers employing lossless and/or lossy data compres-
`sion and decompression to provide accelerated loading of
`operating systems and application programs.
`2. Description of the Related Art
`Modern computers utilize a hierarchy of memory devices.
`To achieve maximum performance levels, modem proces-
`sors utilize onboard memory and on board cache to obtain
`high bandwidth access to both program and data. Limita-
`tions in process technologies currently prohibit placing a
`sufiicient quantity of onboard memory for most applications.
`Thus, in order to olfer suflicient memory for the operating
`system(s), application programs, and user data, computers
`often use various forms of popular oif-processor high speed
`memory including static random access memory (SRAM),
`synchronous dynamic random access memory (SDRAM),
`synchronous burst static ram (SBSRAM). Due to the pro-
`hibitive cost of the high-speed random access memory,
`coupled with their power volatility, a third lower level of the
`hierarchy exists for non-volatile mass storage devices.
`Furthermore, mass storage devices olfer increased capac-
`ity and fairly economical data storage. Mass storage devices
`(such as a “hard disk”) typically store the operating system
`of a computer system, as well as applications and data and
`rapid. access to such data is critical l.o system performance.
`The data storage and retrieval bandwidth of mass storage
`devices, however, is typically much less as compared with
`the bandwidth of other elements of a computing system.
`Indeed, over the last decade, although computer processor
`performance has improved by at
`least a factor of 50,
`magnetic disk storage performance has only improved by a
`factor of 5. Consequently, memory storage devices severely
`limit the performance of consumer, entertainment, ofiice,
`workstation, servers, and mainframe computers for all disk
`and memory intensive operations.
`The ubiquitous lntemet combined with new multimedia
`applications has put tremendous emphasis on storage volu-
`metric density, storage mass density, storewidth, and power
`consumption. Specifically, storage density is limited by the
`number olibits that are encoded in a mass storage device per
`unit volume. Similarly mass density is defined as storage bits
`per unit mass. Storewidth is the data rate at which the data
`may be accessed. There are various ways of categorizing
`storewidth in terms, several of the more prevalent metrics
`include sustained continuous storewidth, burst storewidth,
`and random access storewidth, all typically measured in
`megabytes/sec. Power consumption is canonically defined in
`terms of power consumption per bit and may be specified
`under a number of operating modes including active (While
`data is being accessed and transmitted) and standby mode.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`
`Hence one fairly obvious limitation within the current art is
`the need for even more volume, mass, and power eflicient
`data storage.
`Magnetic disk mass storage devices currently employed
`in a variety of home, business, and scientific computing
`applications suffer from significant seek-time access delays
`along with profound read/write data rate limitations. Cur-
`rently the fastest available disk drives support only a sus-
`tained output data rate in the tens of megabytes per second
`data rate (MB/sec). This is in stark contrast to the modern
`Personal Computer’s Peripheral Component Interconnect
`(PCI) Bus’s low end 32 bit/33 Mhz input/output capability
`of 264 MB/sec and the PC’s internal local bus capability of
`800 MB/sec.
`
`Another problem within the current art is that emergent
`high performance disk interface standards such as the Small
`Computer Systems Interface (SCSI-3), Fibre Channel, AT
`Attachment UltraDMA/66/ 100, Serial Storage Architecture,
`and Universal Serial Bus ofler only higher data transfer rates
`through intermediate data buJ.lering in random access
`memory. These interconnect strategies do not address the
`fundamental problem that all modem magnetic disk storage
`devices for the personal computer marketplace are still
`limited by the same typical physical media restrictions. In
`practice, faster disk access data rates are only achieved by
`the high cost solution of simultaneously accessing multiple
`disk drives with a technique known within the art as data
`striping and redundant array of independent disks (RAID).
`RAID systems often afl°ord the user the benefit of
`increased data bandwidth for data storage and retrieval. By
`simultaneously accessing two or more disk drives, data
`bandwidth may be increased at a maximum rate that is linear
`and directly proportional to the number of disks employed.
`Thus another problem with modem data storage systems
`utilizing RAID systems is that a linear increase in data
`bandwidth requires a proportional number of added disk
`storage devices.
`Another problem with most modem mass storage devices
`is their inherent unreliability. Many modem mass storage
`devices utilize rotating assemblies and other types of elec-
`tromechanical components that possess failure rates one or
`more orders of magnitude higher than equivalent solid-state
`devices. RAID systems employ data redundancy distributed
`across multiple disks to enhance data storage and retrieval
`reliability. In the simplest case, data may be explicitly
`repeated on multiple places on a single disk drive, on
`multiple places on two or more independent disk drives.
`More complex techniques are also employed that support
`various trade-ofi°s between data bandwidth and data reliabil-
`
`ity.
`Standard types of RAID systems currently available
`include RAID Levels CI, 1, and 5. The configuration selected
`depends on the goals to be achieved. Specifically data
`reliability, data validation, data storage/retrieval bandwidth,
`and cost all play a role in defining the appropriate RAID data
`storage solution. RAID level 0 entails pure data striping
`across multiple disk drives. This increases data bandwidth at
`best linearly with the number of disk drives utilized. Data
`reliability and validation capability are decreased. A failure
`of a single drive results in a complete loss of all data. Thus
`another problem with RAID systems is that
`low cost
`improved bandwidth requires a significant decrease in reli-
`ability.
`1 utilizes disk mirroring where data is
`RAID Level
`duplicated on an independent disk subsystem. Validation of
`data amongst the two independent drives is possible if the
`data is simultaneously accessed on both disks and subse-
`
`17
`
`17
`
`

`
`US 7,181,608 B2
`
`3
`quently compared. This tends to decrease data bandwidth
`from even that of a single comparable disk drive. In systems
`that offer hot swap capability, the failed drive is removed and
`a replacement drive is inserted. The data on the failed drive
`is then copied in the background while the entire system 5
`continues to operate in a performance degraded but fully
`operational mode. Once the data rebuild is complete, normal
`operation resumes. Hence, another problem with RAID
`systems is the high cost of increased reliability and associ-
`ated decrease in performance.
`RAID Level 5 employs disk data striping and parity error
`detection to increase both data bandwidth and reliability
`simultaneously. A minimum of three disk drives is required
`for this technique. In the event of a single disk drive failure,
`that drive may be rebuilt from parity and other data encoded
`on disk remaining disk drives. In systems that offer hot swap
`capability, the failed drive is removed and a replacement
`drive is inserted. The data on the failed drive is then rebuilt
`
`l0
`
`15
`
`in the background while the entire system continues to
`operate in a performance degraded but fully operational
`mode. Once the data rebuild is complete, normal operation
`resumes.
`
`Thus another problem with redundant modem mass stor-
`age devices is the degradation of data bandwidth when a
`storage device fails. Additional problems with bandwidth
`limitations and reliability similarly occur within the art by
`all other forms of sequential, pseudo-random, and random
`access mass storage devices. These and other limitations
`within the current art are addressed by the present invention.
`
`SUMMARY OF THE INVENTION
`
`The present invention is directed to systems and methods
`for providing accelerated loading of operating system and
`application programs upon system boot or application
`launch and, more particularly, to data storage controllers
`employing lossless and/or
`lossy data compression and
`decompression to provide accelerated loading of operating
`systems and application programs.
`In one aspect of the present invention, a method for
`providing accelerated loading of an operating system coni-
`prises the steps of: maintaining a list of boot data used for
`booting a computer system; preloading the boot data upon
`initialization of the computer system; and servicing requests
`for boot data from the computer system using the preloaded
`boot data. The boot data may comprise program code
`associated with an operating system ofthe computer system,
`an application program, and a combination thereof. In a
`preferred embodiment, the boot data is retrieved from a boot
`device and stored in a cache memory device.
`In another aspect, the method for accelerated loading of
`an operating system comprises updating the list of boot data
`during the boot process. The step of updating comprises
`adding to the list any boot data requested by the computer
`system not previously stored in the list and/or removing
`from the list any boot data previously stored in the list and
`not requested by the computer system.
`In yet another aspect, the boot data is stored in a com-
`pressed format on the boot device and the preloaded boot
`data is decompressed prior to transmitting the preloaded
`boot data to the requesting system.
`In another aspect, a method for providing accelerated
`launching of an application program comprises the steps of:
`maintaining a list of application data associated with an
`application program; preloading the application data upon
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`
`launching the application program; and servicing requests
`for application data from a computer system using the
`preloaded application data.
`In yet another aspect, a boot device controller for provid-
`ing accelerated loading of an operating system of a host
`system comprises: a digital signal processor (DSP); a pro-
`grammable logic device, wherein the programmable logic
`device is programmed by the digital signal processor to (i)
`instantiate a first interface for operatively interfacing the
`boot device controller to a boot device and to (ii) instantiate
`a second interface for operatively interfacing the boot device
`controller to the host system; and a non-volatile memory
`device, for storing logic code associated with the DSP, the
`first interface and the second interface, wherein the logic
`code comprises instructions executable by the DSP for
`maintaining a list of boot data used for booting the host
`system, preloading the boot data upon initialization of the
`host system, and servicing requests for boot data from the
`host system using the preloaded boot data. The boot device
`controller fiirther includes a cache memory device for stor-
`ing the preloaded boot data.
`The present invention is realized due to recent improve-
`ments in processing speed, inclusive of dedicated analog and
`digital hardware circuits, central processing units, (and any
`hybrid. combinations thereof), that, coupled. with advanced
`data
`compression and decompression algorithms
`are
`enabling of ultra high bandwidth data compression and
`decompression methods that enable improved data storage
`and retrieval bandwidth
`
`These and other aspects, features and advantages, of the
`present invention will become apparent from the following
`detailed description of preferred embodiments that is to be
`read in connection with the accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of a data storage controller
`according to one embodiment of the present invention;
`FIG. 2 is a block diagram ol‘ a data storage controller
`according to another embodiment of the present invention;
`FIG. 3 is a block diagram of a data storage controller
`according to another embodiment of the present invention;
`FIG. 4 is a block diagram of a data storage controller
`according to another embodiment of the present invention;
`FIG. 5 is a block diagram of a data storage controller
`according to another embodiment of the present invention;
`FIGS. 6a and 61) comprise a flow diagram of a method for
`initializing a data storage controller according to one aspect
`of the present invention;
`FIGS. 7a and 7b comprise a flow diagram of a method for
`providing accelerated loading of an operating system and/or
`application programs upon system boot, according to one
`aspect of the present invention;
`FIGS. 8a and 8b comprise a flow diagram of a method for
`providing accelerated loading of application programs
`according to one aspect of the present invention;
`FIG. 9 is a diagram of an exemplary data compression
`system that may be employed in a data storage controller
`according to the present invention; and
`FIG. 10 is a diagram of an exemplary data decompression
`system that may be employed in a data storage controller
`according to the present invention.
`
`18
`
`18
`
`

`
`US 7,181,608 B2
`
`5
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`
`In the following description, it is to be understood that
`syste1n elements having equivalent or similar l'uncLionalily
`are designated with the same reference numerals in the
`Figures. It
`is to be further understood that
`the present
`invention may be implemented in various forms of hard-
`ware, software, firmware, or a combination thereof. Prefer-
`ably, the present invention is implemented on a computer
`platform including hardware such as one or more central
`processing units (CPU) or digital signal processors (DSP), a
`random access memory (RAM), and input/output
`(I/O)
`interface(s). The computer platform may also include an
`operating system, microinstruction code, and dedicated pro-
`cessing hardware utilizing combinatorial logic or finite state
`machines. The various processes and functions described
`herein may be either part of the hardware, microinstruction
`code or application programs that are executed via the
`operating system, or any combination thereof.
`It is to be further understood that, because some of the
`constituent system components described herein are prefer-
`ably implemented as software modules, the actual system
`connections shown in the Figures may dilfer depending
`upon the manner in that the systems are programmed. It is
`to be appreciated that special purpose microprocessors,
`dedicated hardware, or and combination thereof may be
`employed to implement the present invention. Given the
`teachings herein, one of ordinary skill in the related art will
`be able to contemplate these and similar implementations or
`configurations of the present invention.
`
`1. System Architectures
`The present invention is directed to data storage control-
`lers that provide increased data storage/retrieval rates that
`are not otherwise achievable using conventional disk con-
`troller systems and protocols to store/retrieve data to/from
`mass storage devices. The concept of “accelerated” data
`storage and retrieval was introduced in U.S. patent applica-
`tion Ser. No. 09.:"266,394,
`filed Mar. 11, 1999, entitled
`“System and Methods For Accelerated Data Storage and
`Retrieval”, which is now U.S. Pat. No. 6,601,104 and U.S.
`patent application Ser. No. 09/481,243, filed Jan. 11, 2000,
`entitled “System and Methods For Accelerated Data Storage
`and Retrieval,” which is now U.S. Pat. No. 6,604,158, both
`of which are commonly assigned and incorporated herein by
`reference. In general, as described in the above-incorporated
`applications, “accelerated” data storage comprises receiving
`a digital data stream at a data transmission rate which is
`greater than the data storage rate of a target storage device,
`compressing the input stream at a compression rate that
`increases the elfective data storage rate of the target storage
`dev

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