`Petition for Inter Partes Review
`
`DOCKET NO.: 54918.4
`Filed on behalf of Qualcomm and GlobalFoundries
`
`By: David L. McCombs, Reg. No. 32,271
`
`David M. O’Dell, Reg. No. 42,044
`
`
`
`
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`__________________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`___________________
`
`
`
`QUALCOMM INCORPORATED, GLOBALFOUNDRIES INC.,
`GLOBALFOUNDRIES U.S. INC., GLOBALFOUNDRIES DRESDEN
`MODULE ONE LLC & CO. KG, GLOBALFOUNDRIES DRESDEN MODULE
`TWO LLC & CO. KG
`Petitioner
`
`v.
`
`DSS Technology Management, Inc.
`Patent Owner
`
`Case IPR2016-01314
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 6,784,552
`CHALLENGING CLAIMS 8-12
`UNDER 35 U.S.C. § 312 AND 37 C.F.R. § 42.104
`
`i
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`TABLE OF CONTENTS
`
`Introduction ............................................................................................................................. 1
`I.
`II. Mandatory Notices .................................................................................................................. 7
`A.
`Real Party-in-Interest ....................................................................................................... 7
`B.
`Related Matters ................................................................................................................ 7
`C.
`Counsel ............................................................................................................................. 8
`III. Certification of Grounds for Standing ................................................................................. 8
`IV. Overview of Challenge and Relief Requested ..................................................................... 8
`A.
`Prior Art Patents and Printed Publications ....................................................................... 9
`B.
`Grounds for Challenge ..................................................................................................... 9
`V. Technology Background ....................................................................................................... 10
`A.
`Basic Structure of Transistors ........................................................................................ 10
`B.
`Overview of Transistor Fabrication ............................................................................... 11
`1.
`Formation of Transistor Components ......................................................................... 11
`2.
`Etching to Create Contact Openings .......................................................................... 12
`VI. Overview of the ’552 Patent .............................................................................................. 17
`A.
`The Alleged Problem in the Art ..................................................................................... 17
`B.
`The Alleged ’552 Patent Invention ................................................................................ 19
`C.
`Prosecution History ........................................................................................................ 22
`VII. Overview of the Primary Prior Art References .................................................................. 25
`A.
`Summary of the Prior Art ............................................................................................... 25
`B.
`Overview of Heath (Ex. 1103) ....................................................................................... 25
`C.
`Overview of Dennison (Ex. 1104) ................................................................................. 27
`VIII.
`Claim Construction ........................................................................................................ 28
`IX.
`Level of Ordinary Skill In The Art .................................................................................... 34
`X. Specific Grounds for Petition ................................................................................................ 34
`A.
`Ground 1: Claims 8-12 are Anticipated by Heath ......................................................... 35
`1.
`Independent Claim 8 ................................................................................................... 35
`2.
`Claim 9: “The structure of claim 8, wherein the electrically insulative spacer has a
`surface portion without overlying etch stop material” .......................................................... 44
`Claim 10: “The structure of claim 9, wherein the electrically insulative spacer
`3.
`surface portion without overlying etch stop material comprises a surface portion most
`distant from the substrate” .................................................................................................... 45
`Claim 11: “The structure of claim 8, further comprising a second insulating layer on
`4.
`the etch stop layer and over the conductive layer” ............................................................... 46
`
`
`
`i
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`5.
`Claim 12: “The structure of claim 11, further comprising a second conductive
`material in the contact region” .............................................................................................. 47
`B.
`Ground 2: Claims 8-12 Would Have Been Obvious Over Heath in View of Dennison 48
`1.
`Heath, in combination with Dennison, renders the claims obvious under an overly
`narrow construction of the “angle” limitation—e.g., limiting it to a particular portion of the
`“side” of the insulative spacer—recited in claim 8 (element 8(g)) ....................................... 48
`Even if Heath is found to not disclose an etch stop material over the insulating spacer,
`2.
`Heath, in combination with Dennison, renders the claims obvious. ..................................... 58
`XI. Conclusion ......................................................................................................................... 61
`
`
`
`ii
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`Petitioner respectfully requests Inter Partes Review of claims 8-12 of U.S.
`
`Patent No. 6,784,552 (the “’552 patent”) (Ex. 1101) pursuant to 35 U.S.C. §§ 311-
`
`19 and 37 C.F.R. § 42.1 et seq. The above-listed claims of the ’552 patent are
`
`presently the subject of a substantially identical petition for inter partes review
`
`styled Intel Corporation v. DSS Technology Management, Inc., which was filed
`
`December 8, 2015 and assigned Case No. IPR2016-00288. Petitioner will seek
`
`joinder with that inter partes review under 35 U.S.C. § 315(c), 37 C.F.R. §§ 42.22
`
`and 42.122(b).
`
`I. INTRODUCTION
`The ’552 patent purports to provide a novel approach to semiconductor
`
`manufacturing but instead merely duplicates a well-known technique patented by
`
`inventor Barbara Heath nearly a decade before the alleged invention.
`
`The ’552 patent is directed to the manufacture of transistors used in
`
`semiconductor products such as microprocessors and memory. Transistors are one
`
`of the basic building blocks of semiconductors—they are microscopic switches
`
`that turn on and off to allow semiconductors to process data. Transistors include
`
`various components and “contacts” that are used to connect a component of one
`
`transistor to a component of another transistor. The ’552 patent is directed to a
`
`particular technique for the formation of “contact openings”—openings created
`
`through the layers of a semiconductor device so that a contact can be formed
`
`
`
`1
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`
`between components.
`
`The patent asserts that prior art techniques for forming these contact
`
`openings resulted in an unacceptably high risk of creating unintentional
`
`connections (and thus a short-circuit) between the contacts and nearby components.
`
`Specifically, the patent explains that prior art techniques used non-conducting
`
`“sidewall spacers” between contact openings and nearby components to prevent
`
`unintentional connections. But the patent notes that during the process of creating
`
`the openings, these sidewall spacers could become sloped. According to the patent,
`
`a sloped sidewall spacer is particularly susceptible to erosion in subsequent
`
`fabrication steps such that it can be worn down to the point that the contact
`
`opening and a nearby component can make an unintentional connection:
`
`’552 patent, Fig. 2(B)
`
`’552 patent, Fig. 3
`
`
`
`In Fig. 2(B), described as “Prior Art,” the patent shows a contact opening
`
`270, a sidewall spacer 235 that has become sloped as a result of the creation of the
`
`contact opening, and a nearby component 220. In Fig. 3, also described as “Prior
`
`Art,” the patent shows that in a subsequent step, the sloped sidewall spacer has
`
`
`
`2
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`become eroded from the dotted line (370) to the solid line, such that nearby
`
`component 320 (a “gate”) is now exposed to the contact opening. According to the
`
`patent, this unintentional connection between the component and the contact
`
`opening would result in a short-circuit and thus a non-functioning transistor.
`
`The patent purports to solve this problem by using a process that prevents
`
`the sidewall spacer from becoming sloped and instead retains the spacer’s
`
`“substantially rectangular” shape. ’552 at 13:4-10. Specifically, the patent
`
`describes using an admittedly known type of “anisotropic etchant”—a material
`
`used to “etch” or create openings in the fabrication process—that etches only
`
`vertically relative to the substrate surface. According to the patent, the use of such
`
`an etchant avoids the problem of creating a sloped sidewall spacer and instead
`
`“retains the substantially rectangular lateral spacer portion” of the spacer. ’552 at
`
`7:45-51 (“… The etch removes the etch stop insulating layer and retains the
`
`substantially rectangular lateral spacer portion of the first insulating layer.”).1
`
`’552 patent, Fig. 4(J)
`
`’552 patent, Fig. 4(K)
`
`
`
`1 All emphasis and annotations added unless otherwise indicated.
`
`
`
`3
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`As shown in the figures above, after the use of the etchant, the sidewall
`
`spacer (lateral spacer portion 420) has sides that are vertical relative to the
`
`substrate surface (i.e., the spacer retains its “substantially rectangular”
`
`shape). ’552 at 12:54-13:10. As a result, according to the patent, the sidewall
`
`spacer is less susceptible to erosion in subsequent fabrication steps and thus the
`
`risk of unintentional connection (and short-circuit) with nearby components is
`
`reduced. ’552 at 7:62-8:3 (“Unlike prior art processes … the sputter etch does not
`
`significantly erode the substantially rectangular lateral spacer of the first insulating
`
`layer, thus allowing the conductive layer of the device structure to remain
`
`completely isolated or insulated by a spacer . . .”). The patent thus claims to solve
`
`the problem of a short-circuit between a contact and nearby component by using a
`
`process that “retains the substantially rectangular” shape of a sidewall spacer. ’552
`
`at 13:9-10.
`
`But well before December 1995—the ’552 patent’s claimed priority date2—
`
`others had already solved precisely the same problem in precisely the same way.
`
`For example, U.S. Patent No. 4,686,000 (“Heath”) (Ex. 1103)—filed nearly ten
`
`2 The prior assignee claimed a priority date prior to April 21, 1995 during
`
`prosecution of the parent application, U.S. Patent No. 6,066,555 (the “’555
`
`patent”). ’555 Decl. Under 37 C.F.R. 1.131, Feb. 25, 1999 (Ex. 1108) at 3. In any
`
`case, the cited references are prior art and invalidate the ’552 patent.
`
`
`
`4
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`years before the parent application for the ’552 patent was filed—describes the use
`
`of a process that retains the substantially rectangular shape of a sidewall spacer
`
`during the formation of a contact opening in a transistor. Heath at Abstract (“An
`
`improved process for self-aligned contact window formation in an integrated
`
`circuit leaves a ‘Stick’ of etch stop on vertical sidewall surfaces to be protected.”).
`
`Specifically, just like the ’552 patent, Heath describes the need to retain the
`
`“vertical” sides of a lateral spacer in order to avoid unintentional connection (and
`
`thus a short-circuit) with nearby components. Heath at 11:1-15 (explaining that a
`
`“substantially vertical” edge protects against erosion that could cause a short
`
`circuit). And just like the ’552 patent, Heath describes etching “anisotropic[ally]”
`
`in a vertical direction to maintain the substantially vertical sidewalls of a lateral
`
`spacer. Heath at 5:25-35 (“Summary of the Invention[:] These and several other
`
`objects and advantages are obtained by providing a self-aligned contact process
`
`which involves establishing gate electrodes and/or isolation edges which are
`
`substantially vertical with respect to the substrate surface …”); 10:2-11 (“[T]he
`
`part of layer 10 between dashed lines 56 is removed leaving a vertical stick 10a of
`
`layer 10. . . . Some oxide 24 will remain on the top of gate electrode 16 even after
`
`the etch exposes the source/drain region 20 within the contact window, and
`
`because the nitride removal is anisotropic [i.e., it can etch vertically], the ‘stick’
`
`10a will remain on the side, so no short to electrode 16 can occur.”). This is
`
`
`
`5
`
`
`
`shown in Fig. 8C of Heath below:
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`
`
`Figure 8C shows a contact opening (pink) that has been formed by etching
`
`anisotropically in the downward direction towards the substrate. The anisotropic
`
`downward etch results in a vertical etch stop layer 10a (purple) adjacent to a
`
`vertical (i.e., substantially rectangular) insulating spacer 16a (brown). Heath at
`
`10:1-47.
`
`Heath thus discloses the allegedly novel concept of the ’552 patent. Indeed,
`
`a side-by-side comparison of the ’552 and Heath figures shows that they describe
`
`structures that are identical in all relevant respects:
`
`’552 patent, Fig. 4(L)
`
`Heath, Fig. 8C
`
`
`
`As shown, both include: a contact opening (pink); a nearby component (a
`
`gate electrode shown in blue) that needs to remain isolated from the opening; and
`
`sidewall spacers (brown) that have retained their “substantially rectangular” shape
`
`
`
`6
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`(i.e.,both have sides that are vertical relative to the substrate surface).
`
`Accordingly, Heath—which was not before the Patent Office during
`
`prosecution of the ’552 patent—alone, or in combination with other prior art
`
`described below, anticipates and/or renders obvious claims 8-12 of the ’552 patent.
`
`II. MANDATORY NOTICES
`A. Real Party-in-Interest
`Qualcomm Incorporated and GLOBALFOUNDRIES Inc.,
`
`GLOBALFOUNDRIES U.S. Inc., GLOBALFOUNDRIES Dresden Module One
`
`LLC & Co. KG, GLOBALFOUNDRIES Dresden Module Two LLC & Co. KG
`
`(collectively “Petitioner”) are the real party-in-interest.
`
`B. Related Matters
`The ’552 patent is currently being asserted by the Patent Owner in the
`
`following cases: DSS Tech. Mgmt., Inc. v. Intel Corp. et al., Civil Action No.
`
`6:15-CV-130-JRG (E.D. Tex. 2015); DSS Tech. Mgmt., Inc. v. Samsung
`
`Electronics Co., Ltd. et al., 15-cv-690 (E.D. Tex. 2015); DSS Tech. Mgmt., Inc. v.
`
`SK Hynix, Inc. et al., 15-cv-691 (E.D. Tex. 2015); and DSS Tech. Mgmt., Inc. v.
`
`Qualcomm Inc., 15-cv-692 (E.D. Tex. 2015).
`
`The ’552 patent is currently being challenged before the Board in the
`
`following cases: Intel Corporation v. DSS Technology Management, Inc.,
`
`IPR2016-00287 and 00288; SK hynix Inc., SK hynix America Inc., SK hynix
`
`memory solutions Inc., and Hynix Semiconductor Manufacturing America Inc. v.
`7
`
`
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`DSS Technology Management, Inc., IPR2016-00192; Samsung Electronics Co.,
`
`LTD., vs. DSS Technology Management, Inc., IPR2016-00782. Also, the Petitioner
`
`is filing a separate inter partes review petition for claims 1-7 of the ’552 patent.
`
`C. Counsel
`
`Back-up Counsel
`
`Lead Counsel
`
`David M. O’Dell
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
`
`Phone: (972) 739-8635
`Fax: (214) 200-0853
`david.odell.ipr@haynesboone.com
`
`USPTO Customer No. 27683
`USPTO Reg. No. 42,044
`
`Please address all correspondence to lead and back-up counsel. Petitioner
`
`David L. McCombs
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
`
`Phone: (214) 651-5533
`Fax: (214) 200-0853
`david.mccombs.ipr@haynesboone.com
`
`USPTO Customer No. 27683
`USPTO Reg. No. 32,271
`
`also consents to electronic service by email.
`
`III. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies pursuant to Rule 42.104(a) that the patent for which
`
`review is sought is available for inter partes review and that Petitioner is not
`
`barred or estopped from requesting an inter partes review challenging the patent
`
`claims on the grounds identified in this Petition.
`
`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner challenges
`
`
`
`8
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`claims 8-12 of U.S. Patent No. 6,784,552 (Ex. 1101).
`
`A. Prior Art Patents and Printed Publications
`The ’552 patent was filed March 31, 2000 and is a divisional of U.S. Patent
`
`Appl. No. 08/577,751, filed on December 22, 1995, now U.S. Patent No. 6,066,555
`
`(the “’555 patent”) (Ex. 1105). Petitioner relies upon the patents and printed
`
`publications listed in the Table of Exhibits, including:
`
`1. Heath, U.S. Patent No. 4,686,000 (“Heath”) (Ex. 1103), which is prior
`
`art under at least 35 U.S.C. §§ 102(a) and (b).3
`
`2. U.S. Patent No. 5,338,700 (“Dennison”) (Ex. 1104), which is prior art
`
`under at least 35 U.S.C. §§ 102(a) and (b).
`
`B. Grounds for Challenge
`Petitioner requests cancellation of claims 8-12 of the ’552 patent
`
`(“challenged claims”) as unpatentable under 35 U.S.C. §§ 102 and/or 103. This
`
`Petition, supported by the declaration of Richard Blanchard, Ph.D. (“Decl.”) (Ex.
`
`1102), demonstrates that there is a reasonable likelihood that Petitioner will prevail
`
`with respect to at least one challenged claim and that each challenged claim is not
`
`patentable. See 35 U.S.C. § 314(a). The grounds for the petition are as follows:
`
`Ground 1: claims 8-12 are anticipated by Heath; and Ground 2: claims 8-12
`
`
`3 Because the ’552 patent issued prior to the AIA, Petitioner has used the pre-AIA
`
`statutory framework to refer to the prior art.
`
`
`
`9
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`would have been obvious over Heath in view of Dennison.
`
`V. TECHNOLOGY BACKGROUND
`A. Basic Structure of Transistors
`The ’552 patent relates to the field of semiconductor integrated circuit
`
`manufacturing. Semiconductor integrated circuits, such as microprocessors and
`
`computer memory, are typically made up of hundreds of millions (and in some
`
`cases billions) of microscopic structures called transistors. Transistors act as
`
`microscopic switches that turn on and off at extraordinarily high rates to enable
`
`aggregations of transistors (and other components) to process data. Decl. ¶ 27.
`
`As shown in the figure below, transistors typically include three primary
`
`“electrodes” or “terminals”—a gate, a source, and a drain—embedded in or on a
`
`dielectric substrate and surrounded by other dielectric materials:
`
`
`The source and drain regions (also referred to as “diffusion regions”) are transistor
`
`components that emit (source) and receive (drain) current when the transistor is
`
`“on.” The gate electrode is a terminal that can have a voltage applied to it that in
`
`turn causes a current to flow between the source and drain. Decl. ¶¶ 28-29.
`
`The gate, source and drain of a transistor typically need to be connected to
`
`
`
`10
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`other components to form an electrical circuit. The ’552 patent refers to the
`
`components used to make these connections as “contacts.” Contacts consist of one
`
`or more conducting materials (e.g., a metal) that allow current to flow between
`
`transistor components. In many cases, it is important to maintain electrical
`
`isolation between contacts and other nearby components (such as a gate electrode)
`
`so that current that is supposed to flow to other parts of the circuit does not instead
`
`flow to these nearby components (e.g., the gate). As described in more detail
`
`below, devices called sidewall spacers can be formed between the contact and the
`
`nearby components to maintain this electrical isolation. Decl. ¶ 30.
`
`B. Overview of Transistor Fabrication
`1. Formation of Transistor Components
`
`Transistor fabrication typically starts with a silicon substrate. In typical
`
`planar transistors, source and drain regions (“diffusion regions”) are created by
`
`implanting regions of the substrate with ions (charged atomic particles) of different
`
`materials—called “dopants” or “impurities”—to make those regions conductive.
`
`(Once implanted the ions become neutral atoms.) This process—referred to as
`
`“doping” because it dopes the silicon substrate with atomic particles that have
`
`additional charge carriers—is shown below:
`
`
`
`11
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`
`
`Structures can then be formed above the substrate by depositing layers of other
`
`materials onto the substrate. A gate electrode, for example, is formed by first
`
`growing or depositing a “gate oxide” (an insulator) on the substrate followed by
`
`depositing a conductive material (metal or polysilicon) on top of the gate oxide.
`
`The conductive material acts as the gate and the gate oxide creates a layer of
`
`isolation between the gate and the source/drain regions (“S/D regions” or
`
`“diffusion regions”). Decl. ¶¶ 31-32.
`
`Insulating materials may then be deposited around and over the gate and the
`
`S/D regions to maintain electrical isolation where desired. Sidewall spacers, for
`
`instance, can be formed on each side of the gate electrode as shown below:
`
`
`As was known as of the time of the alleged ’552 invention, such sidewall spacers
`
`help prevent direct electrical contact between the gate electrode and nearby
`
`components and thus help to prevent short-circuits. Decl. ¶ 33.
`
`2. Etching to Create Contact Openings
`
`Gate electrodes and S/D regions of transistors must typically be connected to
`
`
`
`12
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`other components in the semiconductor device. These connections are made using
`
`“contacts”—connections between components that allow electrical signals to pass
`
`between the components. Contacts are formed by creating openings through the
`
`layers of a semiconductor device (i.e. “contact openings”) and then filling the
`
`openings with a conductive material. Fig. 4(J) of the ’552 patent shows a fully-
`
`formed contact opening 460, while Fig. 4(L) shows the contact opening after it has
`
`been filled with a conductive material 480 (pink) to form the contact:
`
`
`
`
`
`The process of removing material to create contact openings is known as “etching.”
`
`To perform etching, semiconductor manufacturers use “etchants.” As was known
`
`at the time of the alleged ’552 invention, etchants have various known properties
`
`that can be chosen depending on the type of etching desired. Decl. ¶ 34.
`
`Etching can be performed “isotropically” or “anisotropically.” An isotropic
`
`etch will etch material in all directions (e.g., both vertically and horizontally with
`
`respect to the substrate surface). An anisotropic etch will etch material more
`
`effectively in a particular direction (e.g., vertically but not horizontally relative to
`
`the substrate surface). Decl. ¶ 35.
`
`
`
`13
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`Etching can also be “wet” or “dry.” Wet etching refers to etching in which
`
`the etchant is a liquid, which will dissolve through a particular material to create a
`
`contact opening. Dry etching—sometimes based on the physical process known as
`
`“sputtering”—is etching away material by using a gas or plasma to bombard the
`
`material to be etched with ions. Generally, wet etching is used to perform isotropic
`
`etching (i.e., all directions) and dry etching is used to perform anisotropic etching
`
`(i.e., one direction). Decl. ¶ 36.
`
`Etchants can also be “selective” or “non-selective.” The “selectivity” of an
`
`etchant refers to its effectiveness at etching away one type of material versus
`
`another type of material. A highly-selective etchant relative to a particular material
`
`will etch away that material at a much faster rate than a different type of material.
`
`A non-selective etchant will etch away both types of materials at approximately the
`
`same rate. See, e.g., ’552 at 2:12-21; see also id. at 4:66-5:2. The same etchant
`
`can behave as either a selective or non-selective etchant depending on the material
`
`being etched, the processing conditions, and other parameters of the etching
`
`process. Decl. ¶ 37. For example, an etchant that is selective as to one material
`
`can be non-selective as to another. Id.
`
`As was well-known at the time of the ’552 patent, contact openings of
`
`various shapes and sizes can be created depending on the etching method chosen.
`
`As shown in Figs. 4(H) and 4(I) of the ’552 patent, the etchant removes material to
`
`
`
`14
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`create an “opening” in the layers of a semiconductor device. Fig. 4(H) shows a
`
`transistor structure with insulating material 450 (green) covering the diffusion
`
`regions 445 (orange). Fig. 4(I) shows the same structure after the insulating
`
`material has been etched to create contact openings 460 and 465 which extend
`
`down towards the diffusion regions:
`
`Decl. ¶ 38.
`
`As was also well known, “etch stop layers” (material 440 in Figs. 4(H) and
`
`4(I)) can be used to avoid etching areas not intended to be removed. An etch stop
`
`layer, as its name suggests, effectively stops an etchant from further eroding or
`
`removing material once the etching process reaches the etch stop layer. Etch stop
`
`layers are thus used to protect components (e.g., a gate electrode or S/D region) by
`
`stopping the etchant before it reaches the protected component. Decl. ¶ 39.
`
`The following figures, created by Dr. Blanchard, illustrate the process. The
`
`figure below (step 1) shows a diffusion region with an etch stop layer above it and
`
`further covered by an insulating material:
`
`
`
`15
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`
`
`
`Decl. ¶ 40.
`
`As shown in the figure below (step 2), to make a contact opening down to
`
`the diffusion region, an etchant is applied to the insulating material. The etchant
`
`effectively etches away the insulating material but not the etch stop layer. As a
`
`result, when the etchant reaches the etch stop layer, etching is stopped. In this way,
`
`the etch stop layer prevents the etchant from etching into and damaging the
`
`diffusion region:
`
`Decl. ¶ 41.
`
`
`
`As shown in the figure below (step 3), the etch stop layer can then be
`
`removed by using a different (and usually more precise) etching process to
`
`complete the contact opening down to the diffusion region:
`
`
`
`16
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`
`
`
`Decl. ¶ 42.
`
`VI. OVERVIEW OF THE ’552 PATENT
`A. The Alleged Problem in the Art
`The ’552 patent purports to describe an improved technique for forming
`
`contact openings in transistors. The patent asserts that prior art techniques for
`
`forming contact openings resulted in an unacceptably high risk of creating
`
`unintentional connections (and thus a short-circuit) between the contacts and
`
`nearby components. Specifically, according to the patent, the use of highly
`
`selective etchants to create contact openings caused the sidewall spacers between a
`
`contact opening and a nearby component (such as a gate electrode) to become
`
`sloped. ’552 at 5:6-14 (“The properties of the highly selective etch of the
`
`overlying etch stop layer 240 will transform a substantially rectangular spacer
`
`into a sloped spacer.”); id. at 2:4-6, 2:39-41. This is shown in Fig. 2(B):
`
`
`
`17
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`
`
`The figure, described as “Prior Art,” shows a contact opening 270, a sidewall
`
`spacer 235, and a gate electrode 220 that needs to remain isolated from the contact
`
`opening. As shown, the sidewall spacer has become “sloped.” ’552 at 5:6-14; see
`
`also id. at 5:51-55; Decl. ¶ 43.
`
`The patent then explains that, in subsequent fabrication steps, a sloped
`
`sidewall is particularly susceptible to erosion such that it can be worn down to the
`
`point that the contact opening and a nearby component (e.g., the gate electrode)
`
`can come into unintentional contact. Specifically, the patent explains that, after the
`
`contact opening is formed, an additional etching step is usually performed to clean
`
`the contact opening. ’552 at 5:55-56 (explaining that “RF sputter etch 380” is
`
`performed). This final etching step—which is a dry etch performed using vertical
`
`bombardment—can erode the remaining insulating material separating the gate
`
`electrode from the contact opening. The patent explains that because the sidewall
`
`spacer has become sloped, it is more directly exposed to the vertical bombardment
`
`and thus more susceptible to erosion. ’552 at 5:59-6:1 (“The dynamics of the
`
`sputter etch 380 are that it proceeds vertically, directing high-energy particles at
`
`the contact region. . . . Because the spacer portion 370 is sloping or diagonal, a
`
`
`
`18
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`significant surface area portion of the spacer portion 370 is directly exposed to
`
`the high-energy particles from the RF sputter etch 380.”). This is shown in Fig.
`
`3B:
`
`
`As shown, as a result of this process, the sloped sidewall spacer has become further
`
`eroded from the dotted line (370) to the solid line such that the gate electrode 320
`
`is now exposed to the contact opening. ’552 at 6:14-19 (“[T]he result of the
`
`sputter etch 380 is that the sputter etch 380 laterally erodes the diagonal portion of
`
`the TEOS spacer portion 370 adjacent to the contact region to a point where the
`
`polysilicon layer 320 [i.e., the gate electrode] is no longer isolated from the contact
`
`region 360 by an insulating layer.”). According to the patent, such contact results
`
`in a short-circuit and thus a non-functioning transistor. ’552 at 6:19-21; Decl. ¶ 44.
`
`B. The Alleged ’552 Patent Invention
`The patent purports to solve this problem by using a process that prevents
`
`the formation of a sloped spacer and instead retains the “substantially rectangular”
`
`shape of the lateral spacer. ’552 at 11:48-49 (“[C]are is taken to etch the spacers
`
`435 such that the spacers 435 have a substantially rectangular profile.”), 13:9-16
`
`
`
`19
`
`
`
`U.S. Patent No. 6,784,552 Claims 8-12
`Petition for Inter Partes Review
`(“Of primary significance, the spacer portion 435 of the TEOS layer retains its
`
`substantially rectangular profile. . . . The invention relates to these process
`
`conditions as well as others that result in the retention of a boxy spacer.” (TEOS
`
`is a common type of insulator used in integrated circuits)). Decl. ¶ 45.
`
`The patent does not purport to have invented the use of sidewall spacers, the
`
`use of anisotropic etchants to etch in a vertical direction, or the use of such
`
`etchants to form contact openings. All of this was indisputably well-known. ’552
`
`at 1:10-7:13 (Background). Instead, the patent claims as its novel concept the use
`
`of a known etchant in such a way that retains the “substantially rectangular” shape
`
`of the sidewall spacer. Specifically, the patent describes using an anisotropic
`
`