process.
`Infringing structures are found in the Accused products, including the Intel Core i7-4790 processor, which is made on Intel’s 22-nm FinFET
`Atom, and Xeon processors—have the same gate-to-contact structures. Thus, those processors infringe as well.
`Upon information and belief, all processors made on Intel’s 22-nanometer (“nm”) FinFET process—including the i3, i7, Celeron, Pentium,
`Xeon processors contains the infringing semiconductor structure. Unless otherwise noted, TEM images of a Core i7 processor are below.
`The Accused products contain semiconductor structures. Each of the 22 nanometer-process-based i3, i5, i7, Celeron, Pentium, Atom, and
`Infringement Evidence
`mutually exclusive of other infringement theories or which may overlap with other infringement theories in certain respects.
`in multiple ways, DSS’s Infringement Contentions may include alternative theories of infringement for the Accused Products, which may be
`Furthermore, based on DSS’s view that certain Defendant systems, products, processes, and/or services could infringe certain asserted claims
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`entities, and DSS reserves the right to amend and supplement these Infringement Contentions.
`supplementation and/or amendment of these contentions. DSS will continue to develop the evidence of infringement by all Defendant
`DSS anticipates that additional facts and relevant documents will be uncovered and disclosed that could create good cause for further
`available and as DSS has the opportunity to review relevant Defendant document productions. Infringement investigations are ongoing, and
`discovery. Accordingly, DSS reserves the right to seek leave to supplement and/or amend these disclosures as new information becomes
`contained in this disclosure is correct. Certain information about the Accused Products operation is not available without engaging in further
`the best of DSS’s knowledge, information, and belief, formed after an inquiry that is reasonable under the circumstances, the information
`these circumstances, DSS presents these Infringement Contentions reflecting DSS’s current analysis of the facts presently known to it. To
`these disclosures is the result of publicly available information and independent examination and analysis of the Accused Products. Based on
`To date, the parties in this litigation have not engaged in any discovery, and no documents have been produced. All information contained in
`
`are made by an equivalent method with similar functionality, regardless of the specific product or process name.
`Intel’s 22-nm FinFET process. See Exhibit 1. These infringement contentions apply equally to any other Intel semiconductor structures that
`sell, import, and/or offer to sale the Accused Products. DSS has attached a list of processors, known to it at this time, that are made via
`semiconductor structures made via Intel’s 22-nanometer (“nm”) FinFET process (the “Accused Products”). The remaining Defendants use,
`Intel has and continues to make, use, sell, import, and/or offer to sale in the United States systems and methods use to implement
`
`asserts infringement of claims 1-7.
`Conn’s, and Wal-Mart (“Defendants”). DSS contends that Defendants are each individually liable for infringement of the ’552 Patent. DSS
`Plaintiff DSS Technology Management Inc. (“DSS”) serves its Infringement Contentions as to Defendants Intel, AT&T, Gamestop, Dell,
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`Infringement Contentions for US 6,784,552
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`Page 1 of 11
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`over a substrate;
`layer disposed
`a) a conductive
`
`comprising:
`1.A structure,
`Claim 1
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`’552 Patent
`DSS Infringement Contentions—Exhibit B
`
`1
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`INTEL 1106
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`

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`Page 2 of 11
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`dimensional channel region, the gate is formed on top of the substrate, which includes the fin.
`bottom of the below image. Conductive layers, the gates, are over the substrate. In the FinFET configuration where the gate wraps over a 3-
`The Accused Products have a conductive layer disposed over a substrate. The substrate, likely a silicon substrate, is the grey layer at the
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`Source: DSS2-0000755
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`’552 Patent
`DSS Infringement Contentions—Exhibit B
`
`2
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`

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`conductive gate layer with a white “bead” in the center.
`The Accused Products have a first insulating layer on the conductive layer. The first insulating layer is the light grey area on and above the
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`Source: DSS2-0000751
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`Page 3 of 11
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`layer:
`the conductive
`insulating layer on
`(b) a first
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`conductive layer
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`’552 Patent
`DSS Infringement Contentions—Exhibit B
`
`3
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`

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`of the picture to the diffusion region.
`opening through an intermetal dielectric layer—are “contact regions.” The contact region is shown as the dark region extending from the top
`an opening thorough a dielectric layer between polysilicon and a first metal layer—and “vias”—an opening in other oxide layers such as an
`through which the contact is made to the substrate. Both “contact openings”—an opening through a dielectric exposing a diffusion region or
`The Accused Products have a contact region in the first insulating layer. The contact region is the opening through the insulating layer
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`Source: DSS2-0000751.
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`Page 4 of 11
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`insulating layer;
`region in said first
`(c) a contact
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`First insulating layer
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`Conductive layer
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`’552 Patent
`DSS Infringement Contentions—Exhibit B
`
`4
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`

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`layer. The insulating spacers are the vertical, light grey materials on either side of the conductive layers.
`The Accused Products include at least one insulating spacer in the contact region. The insulating spacers are adjacent to the first insulating
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`insulating spacer
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`
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`contact region
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`Source: DSS2-0000751
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`Source: DSS2-0000751.
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`Page 5 of 11
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`and
`insulating layer;
`to the first
`region adjacent
`in the contact
`insulating spacer
`(d) at least one
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`’552 Patent
`DSS Infringement Contentions—Exhibit B
`
`5
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`

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`material are different, either in chemical composition or application.
`of the TEM image between the first insulating material and the etch stop material evidences that the insulating material and etch stop
`material is seen on top of the first insulating layer and on the sides of the insulating spacers, into the contact region. The contrast in shading
`The Accused Products have an etch stop material over the first insulating layer that is adjacent to the insulating spacer. The etch stop
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`’552 Patent
`DSS Infringement Contentions—Exhibit B
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`Page 6 of 11
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`than 85°.
`angle of more
`angle or an acute
`either a right
`surface that is
`the substrate
`angle relative to
`spacer has an
`the insulating
`wherein a side of
`
`insulating spacer,
`material from the
`being a different
`stop material
`spacer, the etch
`the insulating
`and adjacent to
`insulating layer
`said first
`material over
`(e) an etch stop
`
`steeper than the shown reference angle of 85°, shown in black on the insulating spacer below.
`angle of more than 85°. The insulating spacer containing the contact has a nearly right angle that is at least 85°. The sidewall spacer is
`The Accused Products have an insulating spacer with a side that has a relative angle to the substrate surface that is either a right angle or an
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`Source: DSS2-0000751
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`etch stop material
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`6
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`Page 7 of 11
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`The
`Claim 3
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`nitride.
`comprises silicon
`material
`said etch stop
`claim 1 wherein
`apparatus of
`semiconductor
`The
`Claim 2
`
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`Intel’s 22-nm FinFET process.
`Equivalent infringing structures appear in the Intel Core i3, Core i5, Celeron, Pentium, Xeon and Atom processors, which are made using
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`
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`’552 Patent
`DSS Infringement Contentions—Exhibit B
`
`Source: DSS2-0000751.
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`
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`Upon information and belief, the etch stop layer comprises silicon nitride and/or silicon dioxide.
`The contentions for claim 1 above are incorporated by reference herein.
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`The contentions for claim 1 above are incorporated by reference herein.
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`7
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`surface portion without overlying etch stop is at the top of the insulating spacer.
`The Accused Products have an insulating spacer that has a surface portion in the contact region without an overlying etch stop material. The
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`The contentions for claim 1 above are incorporated herein by reference.
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`Upon information and belief, the etch stop layer comprises silicon nitride and/or silicon dioxide.
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`’552 Patent
`DSS Infringement Contentions—Exhibit B
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`Page 8 of 11
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`the insulating
`claim 4, wherein
`The structure of
`Claim 5
`
`
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`stop material.
`overlying etch
`region without
`the contact
`surface portion in
`spacer has a
`the insulating
`claim 1, wherein
`The structure of
`Claim 4
`
`dioxide
`comprises silicon
`material
`said etch stop
`claim 1 wherein
`apparatus of
`semiconductor
`
`
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`The Accused Products contain a structure wherein the insulating spacer surface portion without overlying etch stop material is an insulating
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`The contentions of claim 4 above are incorporated herein by reference.
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`Source: Source: DSS2-0000751
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`8
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`the substrate is at the bottom of the insulating spacer.
`surface portion most distant from the substrate. The surface portion without overlying etch stop is at the top of the insulating spacer, while
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`’552 Patent
`DSS Infringement Contentions—Exhibit B
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`Page 9 of 11
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`conductive layer.
`over the
`stop layer and
`layer on the etch
`second insulating
`comprising a
`claim 1, further
`The structure of
`Claim 6
`
`
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`said substrate.
`most distant from
`surface portion
`insulating spacer
`comprises an
`stop material
`overlying etch
`portion without
`spacer surface
`
`The Accused Products have a second insulating layer on the etch stop layer and over the conductive layer.
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`The contentions of claim 1 above and incorporated by reference herein.
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`Source: Source: DSS2-0000751
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`9
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`material in the contact region is the contact metal. Further, the second conductive material may include a conductive glue layer.
`The Accused Products have a second insulating layer on the etch stop layer and over the conductive layer, the gate. The second conductive
`
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`The contentions for claim 6 above are incorporated herein by reference.
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`second insulating layer
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`’552 Patent
`DSS Infringement Contentions—Exhibit B
`
`Source: DSS2-0000751
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`
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`Page 10 of 11
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`contact region.
`material in the
`conductive
`second
`comprising a
`claim 6, further
`The structure of
`Claim 7
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`
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`10
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`second conducting material
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`Source: DSS2-0000751
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`Page 11 of 11
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`’552 Patent
`DSS Infringement Contentions—Exhibit B
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`11