Trials@uspto.gov
`571-272-7822
`
`
`
`
`
`Paper 25
`Entered: June 1, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION
`and
`QUALCOMM INCORPORATED, GLOBALFOUNDRIES INC.,
`GLOBALFOUNDRIES U.S. INC., GLOBALFOUNDRIES DRESDEN
`MODULE ONE LLC & CO. KG, GLOBALFOUNDRIES DRESDEN
`MODULE TWO LLC & CO. KG,
`Petitioner,
`
`v.
`
`DSS TECHNOLOGY MANAGEMENT, INC.,
`Patent Owner.
`____________
`
`Case IPR2016-002881
`Patent 6,784,552 B2
`
`
`
`Before BRYAN F. MOORE, BRIAN J. McNAMARA, and
`MINN CHUNG, Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`1 Case IPR2016-01314 has been joined with this proceeding.
`
`
`571-272-7822
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`
`
`
`
`Paper 25
`Entered: June 1, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION
`and
`QUALCOMM INCORPORATED, GLOBALFOUNDRIES INC.,
`GLOBALFOUNDRIES U.S. INC., GLOBALFOUNDRIES DRESDEN
`MODULE ONE LLC & CO. KG, GLOBALFOUNDRIES DRESDEN
`MODULE TWO LLC & CO. KG,
`Petitioner,
`
`v.
`
`DSS TECHNOLOGY MANAGEMENT, INC.,
`Patent Owner.
`____________
`
`Case IPR2016-002881
`Patent 6,784,552 B2
`
`
`
`Before BRYAN F. MOORE, BRIAN J. McNAMARA, and
`MINN CHUNG, Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`1 Case IPR2016-01314 has been joined with this proceeding.
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`IPR2016-00288
`Patent 6,784,552 B2
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`I. INTRODUCTION
`
`In this inter partes review, instituted pursuant to 35 U.S.C. § 314,
`Intel Corporation, Qualcomm Incorporated, Globalfoundries Inc.,
`Globalfoundries U.S. Inc., Globalfoundries Dresden Module One LLC &
`Co. KG, and Globalfoundries Dresden Module Two LLC & Co. KG
`(collectively, “Petitioner”) challenge the patentability of claims 8–12 (the
`“challenged claims”) of U.S. Patent No. 6,784,552 B2 (Ex. 1101, “the ’552
`patent”), owned by DSS Technology Management, Inc. (“Patent Owner”).
`The Board has jurisdiction under 35 U.S.C. § 6. This Final Written Decision
`is entered pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73. We base
`our decision on the preponderance of the evidence. 35 U.S.C. § 316(e); 37
`C.F.R. § 42.1(d). With respect to the grounds instituted in this trial, we have
`considered the papers submitted by the parties and the evidence cited
`therein. For the reasons discussed below, we determine Petitioner has
`shown by a preponderance of the evidence that claims 8–12 of the ’552
`patent are unpatentable.
`
`A. Procedural History
`On December 8, 2015, Intel Corporation filed a Petition (Paper 2,
`“Pet.”) requesting inter partes review of claims 8–12 of the ’552 patent.
`Patent Owner filed a Preliminary Response (Paper 7, “Prelim. Resp.”). On
`June 8, 2016, we instituted an inter partes review of claims 8–12 of the ’552
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`patent based on the ground that the challenged claims are anticipated by
`Heath.2 Paper 11 (“Dec. on Inst.”), 28.
`After institution, Qualcomm Incorporated, Globalfoundries Inc.,
`Globalfoundries U.S. Inc., Globalfoundries Dresden Module One LLC &
`Co. KG, and Globalfoundries Dresden Module Two LLC & Co. KG
`(collectively, “Qualcomm”) filed a petition requesting inter partes review of
`claims 8–12 of the ’552 patent on the same grounds asserted by Intel
`Corporation, accompanied by a timely motion seeking joinder with this
`proceeding. IPR2016-01314, Papers 3 (petition), 4 (motion for joinder).3
`Patent Owner did not oppose the joinder. We instituted an inter partes
`review and joined it with the present proceeding. Papers 18, 19.
`On September 7, 2016, Patent Owner filed a Patent Owner Response
`(Paper 20, “PO Resp.”) that contained no citations to evidence and no
`argument, other than noting that, in contrast to the standard applied in
`reaching a decision to institute (i.e., a reasonable likelihood Petitioner will
`prevail on its challenge to patentability of a claim), the standard for reaching
`a final decision is whether the Petitioner proved unpatentability by a
`preponderance of the evidence. PO Resp. 2. Patent Owner then stated that it
`“defers to the Board to make this determination based on its impartial
`analysis of the prior art and Petitioners’ arguments.” Id.
`
`
`2 Ex. 1103, U.S. Patent No. 4,686,000 (Aug. 11, 1987) (“Heath”).
`3 Because Qualcomm’s petition in IPR2016-01314 is identical in all
`substantive aspects to the Petition in this proceeding (see Paper 18, 8), we
`cite only to the Petition throughout this Final Written Decision.
`3
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`In its Reply (Paper 21, “Pet. Reply”) filed on December 7, 2016,
`Petitioner stated that Patent Owner has not cross-examined Petitioner’s
`expert, John C. Bravman, Ph.D., or provided any testimony that contradicts
`Dr. Bravman’s testimony, and that the challenged claims should be found
`unpatentable. Pet. Reply 1–2.
`No hearing was held because we determined oral argument is not
`necessary to render a final written decision in this proceeding. See Paper 24,
`2.
`
`B. Related Proceedings
`According to the parties, the ’552 patent is the subject of the
`following patent infringement cases: DSS Tech. Mgmt., Inc. v. Intel Corp.,
`Case No. 6:15-cv-130-JRG (E.D. Tex.); DSS Tech. Mgmt., Inc. v. Samsung
`Elec. Co., Ltd., Case No. 6:15-cv-690 (E.D. Tex.); DSS Tech. Mgmt., Inc. v.
`SK Hynix, Inc., Case No. 6:15-cv-691 (E.D. Tex.); and DSS Tech. Mgmt.,
`Inc. v. Qualcomm, Inc., Case No. 6:15-cv-692 (E.D. Tex.). Pet. 7; Paper 6,
`2–3.
`
`In related proceedings before the Board, we instituted inter partes
`reviews of claims 1–7 of the ’552 patent in IPR2016-00287 and IPR2016-
`01311.4 The ’552 patent is also the subject of an instituted trial proceeding
`Samsung Elec. Co., Ltd. v. DSS Tech. Mgmt., Inc., Case IPR2016-00782.
`Additionally, we instituted inter partes reviews of claims of U.S. Patent
`
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`4 Case IPR2016-01311 has been joined with IPR2016-00287.
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`No. 5,965,924 in Intel Corp. v. DSS Tech. Mgmt., Inc., Cases IPR2016-
`00289, IPR2016-00290, IPR2016-01312, and IPR2016-01313.5
`
`II. THE ’552 PATENT
`A. Described Invention
`The ’552 patent describes a process of semiconductor device
`fabrication and a structure of a semiconductor device having “substantially
`rectangular” lateral insulating spacers adjacent to gate electrodes. Ex. 1101,
`Abstract. The ’552 patent defines the term “substantially rectangular” to
`mean that “a side of the spacer has an angle relative to the substrate surface
`of more than 85°.” Id. at col. 8, ll. 40–42.
`Figure 4(D) of the ’552 patent is reproduced below.
`
`
`Figure 4(D) illustrates a cross-sectional view of a series of gates 415 (also
`called conducting layers or polysilicon layers) completely encapsulated in
`insulating material 420, e.g., TEOS (tetraethyl orthosilicate glass), where
`spacers or spacer portions 435 of the insulating material adjacent to the gates
`
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`5 Cases IPR2016-01312 and IPR2016-01313 have been joined with
`IPR2016-00290 and IPR2016-00289, respectively.
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`have substantially rectangular profiles. Id. at col. 9, ll. 9–13; col. 11, ll. 40–
`46. As shown in Figure 4(D), gates 415 are insulated from sources or drains
`405 by insulating dielectric layers 410. See id. at col. 10, ll. 49–50. The
`’552 patent describes a process of making high quality contacts to the
`sources or drains, such as “self-aligned” contacts, by etching structures over
`substrate 400 and sources or drains 405. Id. at col. 7, ll. 19–22; col. 8, ll. 4–
`6.
`
`Figure 4(I) of the ’552 patent is reproduced below.
`
`
`Figure 4(I) illustrates additional structures deposited and etched over the
`structure described in Figure 4(D), such as second dielectric layer 440
`(called etch stop layer), blanket layer 450, and photoresist mask layer 455.
`Id. at col. 9, ll. 33–39; col. 11, ll. 63–65; col. 12, ll. 34–42. According to the
`’552 patent, etch stop layer 440, e.g., silicon nitride layer 440, depicted in
`Figure 4(I) is distinct or different from the underlying TEOS insulating
`layer. Id. at col. 12, ll. 10–11. The etch stop layer protects the underlying
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`TEOS layer when blanket layer 450 made of BPTEOS6 is etched away to
`create contact openings 460 and 465 above source or drain 445. See id. at
`col. 12, ll. 36–42; col. 4, ll. 41–59.
`A second etch is then performed to remove etch stop layer 440
`covering source or drain 445 in contact openings 460 and 465. Id. at col. 12,
`ll. 48–52; col. 7, ll. 43–45. The ’552 patent describes that the second etch is
`“almost completely anisotropic,” which means that the etchant etches in the
`vertical direction, or perpendicular relative to the substrate surface. Id. at
`col. 7, ll. 45–48; col. 12, ll. 55–58. Hence, the etch removes the etch stop
`material covering the area of the contact openings or contact regions 460 and
`465, but does not significantly etch the etch stop material adjacent to the
`spacer portions 435.7 Id. at col. 7, ll. 53–55; col. 12, ll. 58–61.
`
`
`6 BPTEOS is an acronym for borophosphosilicate tetraethyl orthosilicate
`glass. See Ex. 1101, col. 11, ll. 6–7.
`7 As discussed above, spacer portions 435 are illustrated in Figure 4(D) and
`the accompanying text. See Ex. 1101, col. 11, ll. 40–46, Fig. 4(D).
`7
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`Figures 4(J) and 4(K) of the ’552 patent are reproduced below.
`
`
`Figures 4(J) and 4(K) illustrate the structure of the semiconductor device of
`the ’552 patent after the second etch for removing the etch stop layer from
`the contact regions 460 and 465 is completed. As shown in Figures 4(J) and
`4(K), due to the anisotropic or vertical nature of the second etch, only a
`small portion, i.e., portion 475, of the TEOS spacer portion 435 is removed
`during the etch. Id. at col. 13, ll. 6–9. Of primary significance, according to
`the ’552 patent, the spacer portion 435 of the TEOS insulating layer 420
`retains its substantially rectangular profile, in contrast to the conventional
`prior art method which transforms a substantially rectangular spacer into a
`sloped spacer. Id. at col. 13, ll. 9–10; col. 7, ll. 48–51; col. 5, ll. 4–14.
`
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`B. Illustrative Claim
`Claim 8 is illustrative of the challenged claims and is reproduced
`below with the key limitation (the “angle limitation”) emphasized in italics:
`8. A structure, comprising:
`(a) a first electrically conductive material formed in and/or on a
`surface of a substrate;
`(b) a contact opening in a region adjacent to a second electrically
`conductive material formed on the substrate;
`(c) an electrically insulative spacer in the contact opening
`adjacent to the second electrically conductive material;
`(d) an etch stop material over the electrically insulative spacer
`and the first and second electrically conductive materials, the
`etch stop material being a different material from the insulative
`spacer;
`(e) a blanket layer over the etch stop material; and
`(f) an opening through a first part of the etch stop material to the
`first electrically conductive material,
`wherein a side of the electrically insulative spacer has an angle
`relative to the substrate surface that is either a right angle or an
`acute angle of more than 85°.
`
`III. CLAIM CONSTRUCTION
`As acknowledged by the parties, the ’552 patent has expired. Pet. 28;
`Prelim. Resp. 14. Thus, we construe the claims in accordance with the
`standard set forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005)
`(en banc). See In re CSB-Sys. Int’l, Inc., 832 F.3d 1335, 1341 (Fed. Cir.
`2016) (“[W]hen an expired patent is subject to reexamination, the traditional
`Phillips construction standard attaches.”) (citing In re Rambus, 694 F.3d 42,
`46 (Fed. Cir. 2012)); Black & Decker, Inc. v. Positec USA, Inc., 646 Fed.
`
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`App’x 1019, 1024 (Fed. Cir. 2016) (holding that in an inter partes review,
`“[c]laims of an expired patent are given their ordinary and customary
`meaning in accordance with our opinion in [Phillips]”).
`In the Decision on Institution, applying the Phillips standard, we
`preliminarily interpreted the “angle limitation” set forth above—i.e., the
`limitation reciting “a side of the electrically insulative spacer has an angle
`relative to the substrate surface that is either a right angle or an acute angle
`of more than 85°”8—to mean “a side of the electrically insulative spacer has
`an angle relative to the substrate surface that is greater than 85° and less than
`or equal to 90°.” Dec. on Inst. 8–14. Importantly, we were unpersuaded by
`Patent Owner’s argument that the angle of a side of the insulating spacer
`must be obtained “through the use of a low selectivity etch” (Prelim. Resp.
`15–19) and determined that the challenged claims do not require the use of a
`low selectivity etch. Dec. on Inst. 8–12.
`
`
`8 Claim 1 includes essentially the same limitation, the only difference being
`that claim 1 recites “insulating spacer” instead of “electrically insulative
`spacer” recited in claim 8. Tracking the language of the claims, the ’552
`patent uses the terms “insulating spacer” and “insulative spacer”
`interchangeably throughout the written description. See, e.g., Ex. 1101,
`col. 6, ll. 13–65; see also id. at col. 13, ll. 55–62 (using “the spacer portions
`of the insulating material” and “the spacer portions [of] insulative material”
`interchangeably). The parties also appear to use the terms “insulating
`spacer” and “insulative spacer” interchangeably in the Petition and the
`Preliminary Response. See, e.g., Pet. 28–29; Prelim. Resp. 15–16, 19. Upon
`considering the complete record, we deem the terms “insulating spacer” and
`“insulative spacer” to be interchangeable and to have no meaningful
`difference in their meaning in the context of the ’552 patent.
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`The parties do not present additional claim construction arguments in
`their Patent Owner Response and Petitioner Reply. Upon considering the
`complete record, we discern no reason to deviate from our construction,
`which was adopted from the parties’ agreed construction at the district court
`(Dec. on Inst. 14 (citing Ex. 1124 (Dist. Ct. Claim Construction Order), 7–
`8)), and maintain our construction of the “angle limitation” to mean “a side
`of the electrically insulative spacer has an angle relative to the substrate
`surface that is greater than 85° and less than or equal to 90°.”
`No other claim terms need to be construed expressly for purposes of
`this Final Written Decision. See Wellman, Inc. v. Eastman Chem. Co., 642
`F.3d 1355, 1361 (Fed. Cir. 2011) (explaining that “claim terms need only be
`construed ‘to the extent necessary to resolve the controversy’” (quoting
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir.
`1999))).
`
`IV. ANALYSIS OF PETITIONER’S PRIOR ART CHALLENGES
`As previously discussed, the Patent Owner Response does not contain
`any substantive argument or citations to evidence. Although it remains
`Petitioner’s burden to prove unpatentability by a preponderance of the
`evidence, in our Scheduling Order, we cautioned Patent Owner that “any
`arguments for patentability not raised in the response will be deemed
`waived.” See Paper 12, 4–5. Patent Owner elected not to respond
`substantively and, instead, “defers to the Board” to determine whether
`Petitioner has demonstrated the challenged claims are unpatentable by a
`preponderance of the evidence. PO Resp. 2. Under the particular
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`circumstance of this case, for purposes of this Final Written Decision, we
`exercise our discretion to consider Patent Owner’s substantive patentability
`arguments in its Preliminary Response in reaching a decision as set forth
`below. See 37 C.F.R. § 42.5(a).
`
`A. Anticipation by Heath
`Petitioner asserts that claims 8–12 are unpatentable under 35 U.S.C.
`§ 102(b) as anticipated by Heath. Pet. 34–47. Petitioner provides detailed
`explanations and specific citations to Heath indicating where in the reference
`the claimed features are disclosed. Id. In addition, Petitioner relies upon the
`Declaration of John C. Bravman, Ph.D. (“Bravman Decl.,” Ex. 1102) to
`support its position. Id. Upon review of all of the parties’ papers and
`supporting evidence discussed in those papers, we are persuaded that
`Petitioner has demonstrated, by a preponderance of evidence, that claims 8–
`12 are unpatentable under 35 U.S.C. § 102(b) as anticipated by Heath.
`
`1. Principles of Law
`A claim is unpatentable under 35 U.S.C. § 102 only if a single prior
`art reference expressly or inherently describes each and every limitation set
`forth in the claim. See Perricone v. Medicis Pharm. Corp., 432 F.3d 1368,
`1375 (Fed. Cir. 2005); Verdegaal Bros., Inc. v. Union Oil Co., 814 F.2d 628,
`631 (Fed. Cir. 1987). Further, a reference cannot anticipate “unless [it]
`discloses within the four corners of the document not only all of the
`limitations claimed[,] but also all of the limitations arranged or combined in
`the same way as recited in the claim.” Net MoneyIN, Inc. v. VeriSign, Inc.,
`545 F.3d 1359, 1371 (Fed. Cir. 2008). Although the elements must be
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`arranged in the same way as in the claim, “the reference need not satisfy an
`ipsissimis verbis test,” i.e., identity of terminology is not required. In re
`Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009); In re Bond, 910 F.2d 831,
`832 (Fed. Cir. 1990). We analyze this asserted ground based on anticipation
`with the principles identified above in mind.
`
`2. Overview of Heath
`Heath describes a process for forming a self-aligned contact window
`in a semiconductor device, such as an integrated circuit. Ex. 1103, Abstract.
`Heath describes a two-step etching process which comprises the steps of first
`etching a dielectric layer down to a silicon nitride etch stop layer, and then
`etching the etch stop, leaving a “stick” of the etch stop material on the
`vertical sidewall of the layer to be protected. Id.
`Figure 8B of Heath is reproduced below.
`
`
`Figure 8B depicts a cross-sectional view of a semiconductor structure after
`the first etching step, including gate electrode 16 insulated from contact
`window 32 and source or drain 20 by silicon nitride layer 10. See id. at
`col. 9, ll. 50–67. In the second etching step, etch stop layer 10 is removed to
`open contact window 32 to source or drain 20. Heath describes that, because
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`the nitride removal is anisotropic, vertical “stick” 10a of nitride layer 10 will
`remain on the side of gate electrode 16 so that no electrical short occurs
`between the gate electrode and the contact window or the source or drain
`region. Id. at col. 10, ll. 1–11.
`
`3. Discussion
`
`a. Claim 8
`Petitioner asserts that the embodiment depicted in Figure 8C of Heath
`discloses every limitation of claim 8. Pet. 34. According to Petitioner,
`Heath is directed to the same problem as the ’552 patent—i.e., avoiding a
`short-circuit between the contact and the gate electrode—and describes
`solving the problem in the same way—that is, through the use of a non-
`conductive sidewall spacer with vertical sides. Id. at 25 (citing Ex. 1103,
`Abstract; Ex. 1102 ¶ 60). Petitioner references Figure 8C of Heath and
`asserts that Heath discloses a transistor structure consisting of the same
`components arranged in the same way as the invention of the ’552 patent.
`Id. at 25–26 (identifying various components depicted in Fig. 8C and citing
`Ex. 1103, Abstract, Fig. 8C, col. 5, ll. 26–30, col. 10, ll. 2–13; Ex. 1102
`¶¶ 61, 62).
`Figure 8C of Heath is reproduced below.
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`Figure 8C above depicts a cross-sectional view of a semiconductor structure
`at the same stage of processing as Figure 8B (reproduced in Overview of
`Heath section above) combined with the addition of a sidewall spacer 16a.
`Ex. 1103, col. 10, ll. 14–19. Referencing Figure 8C, Petitioner provides
`detailed explanations and specific citations to Heath indicating where in the
`reference each limitation of claim 8 is disclosed. Pet. 34–43. For the
`reasons discussed below, we are persuaded that Heath discloses each
`limitation of independent claim 8 as arranged in the claim.
`
`i. Preamble and Elements (a), (b), (c), (d), (e), and (f)
`Beginning with the preamble of claim 8, Petitioner cites Heath’s
`disclosure of a transistor structure in Figure 8C as disclosing a “structure”
`recited in claim 8. Id. at 34 (citing Ex. 1103, col. 10, ll. 33–35, Fig. 8C;
`Ex. 1102 ¶ 78). We agree with Petitioner that Figure 8C of Heath discloses
`a “structure” recited in claim 8 because, as noted by Petitioner, Heath
`describes methods to “produce a transistor structure which has source/drain
`implants like those shown in FIG. 8C.” Id. (quoting Ex. 1103, col. 10,
`ll. 33–35); see also id. at 25–26 (Petitioner arguing that Figure 8C of Heath
`discloses a transistor structure consisting of the same components arranged
`in the same way as the invention of the ’552 patent). As discussed above,
`both the ’552 patent and Heath describe a process of forming a self-aligned
`contact structure in a semiconductor device. Ex. 1101, Abstract, col. 7,
`ll. 19–22, col. 8, ll. 4–6 (“The structure contemplated by the invention is an
`effective device for small feature size structures, particularly self-aligned
`contacts.”); Ex. 1103, Abstract.
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`Petitioner next addresses the limitations recited in the body of claim 8.
`Claim 8 numbers from (a) to (f) the elements recited in the body of the claim
`and recites the numbered elements as follows: (a) a first electrically
`conductive material formed in and/or on a surface of a substrate; (b) a
`contact opening in a region adjacent to a second electrically conductive
`material formed on the substrate; (c) an electrically insulative spacer in the
`contact opening adjacent to the second electrically conductive material; (d)
`an etch stop material over the electrically insulative spacer and the first and
`second electrically conductive materials, the etch stop material being a
`different material from the insulative spacer; (e) a blanket layer over the etch
`stop material; and (f) an opening through a first part of the etch stop material
`to the first electrically conductive material.
`Claim 8 recites two distinct “electrically conductive material”
`elements formed on a substrate: “(a) a first electrically conductive material
`formed in and/or on a surface of a substrate” and “(b) . . . a second
`electrically conductive material formed on the substrate.” Petitioner asserts
`that Figures 2 and 8C of Heath disclose both of these “electrically
`conductive material” limitations. Pet. 34–37.
`Petitioner asserts that source/drain 20 depicted in Figure 8C discloses
`“(a) a first electrically conductive material formed in and/or on a surface of a
`substrate,” as recited in claim 8. Id. at 34–36 (citing Ex. 1103, col. 8, ll. 2–
`5; col. 9, ll. 50–55; Figs. 2–7, 8C), 35 n.7 (citing Ex. 1103, col. 7, ll. 36–41,
`56–58; Figs. 2–7). Citing the testimony of Dr. Bravman, Petitioner argues
`that sources and/or drains are known in the art to be electrically conductive
`diffusion regions of a transistor structure. Id. at 36 (citing Ex. 1102 ¶ 79).
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`Petitioner further argues that Figures 2 and 3 of Heath and their
`accompanying text disclose source/drain 20 as a diffusion region, which is
`formed on substrate 12 by arsenic, boron or phosphorous implantation. Id.
`at 35 n.7 (citing Ex. 1103, col. 7, ll. 36–41, 56–58; Figs. 2–7; Ex. 1102 ¶ 79
`n.5), 36 (citing Ex. 1103, col. 8, ll. 2–5).
`Petitioner also asserts that gate electrode 16 depicted in Figure 8C
`discloses “a second electrically conductive material formed on the
`substrate,” as recited in element (b) of claim 8. Id. at 36–37 (citing
`Ex. 1103, col. 7, ll. 36–38; col. 8, ll. 8–11; col. 9, ll. 44–47, 50–52; Figs. 2,
`8C). Petitioner notes that Heath discloses gate electrode 16 is made of
`doped polysilicon, which Petitioner argues, citing the testimony of Dr.
`Bravman, a person of ordinary skill in the art would understand to be
`electrically conductive in a transistor structure. Id. at 36–37 (citing
`Ex. 1103, col. 8, ll. 8–11; Ex. 1102 ¶ 80). Petitioner further argues that
`Figure 2 of Heath shows gate electrodes 14 and 16 are formed on substrate
`12 as part of the same process of forming the structure depicted in Figure
`8C. Id. at 37 (citing Ex. 1103, col. 7, ll. 36–38, Fig. 2).
`We agree with Petitioner that source/drain 20 shown in Figures
`2 and 8C is a diffusion region formed on substrate 12 because, as
`noted by Petitioner, Heath discloses that
`FIG. 2 illustrates a layer 10 operable as an etch stop and a
`substrate 12 having poly gate electrodes 14 and 16 over a
`relatively thin gate oxide 18. Between the gate electrodes but in
`the substrate is an arsenic, phosphorous or boron implant 20
`which acts as a transistor source or drain.
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`Id. at 35 n.7 (quoting Ex. 1103, col. 7, ll. 36–41). We also agree that Figures
`2 and 8C disclose gate electrode 16 formed on substrate 12 because, as cited
`by Petitioner, Heath discloses that “FIG. 2 illustrates a layer 10 operable as
`an etch stop and a substrate 12 having poly gate electrodes 14 and 16 over a
`relatively thin gate oxide 18” (id. at 37 (quoting Ex. 1103, col. 7, ll. 36–38)),
`“FIGS. 8A, 8B and 8C relate to establishing a contact window to a
`source/drain region next to a gate electrode or field-shield electrode 16 . . .”
`(id. at 36 (quoting Ex. 1103, col. 9, ll. 44–47)), and “FIGS. 8A and 8B show
`a gate electrode 16 and an active area 20 in the substrate to the left of gate
`electrode 16” (id. (quoting Ex. 1103, col. 9, ll. 50–52) (emphases added)).
`In addition, we are persuaded that Figures 2 and 8C are part of the same
`disclosure in Heath because both figures illustrate the process of forming a
`self-aligned contact window in a semiconductor device. See Ex. 1103,
`col. 2, ll. 28–32 (“FIG. 2 shows an illustrative semiconductor structure near
`the completion of processing according to the invented process applied
`illustratively for establishing a self-aligned contact window to a gate
`electrode or field-shield electrode edge.” (emphasis added)), col. 11, ll. 11–
`13 (“As a result of the process described with reference to FIGS. 8 and 9, the
`contact window to the active area will be self-aligned, i.e., it will be
`protected from shorting to an element nearby to which contact is not to be
`made.” (emphases added)).
`We credit Dr. Bravman’s testimony and are persuaded that sources
`and/or drains are known in the art to be electrically conductive diffusion
`regions of a transistor structure, and that polysilicon used to form gate
`electrode 16 of Heath is an electrically conductive material. See Ex. 1102
`18
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`¶¶ 79, 80. Therefore, we are persuaded by Petitioner’s argument and
`evidence that Heath discloses “(a) a first electrically conductive material
`formed in and/or on a surface of a substrate” and “(b) . . . a second
`electrically conductive material formed on the substrate,” as recited in claim
`8.
`
`Petitioner provides an annotated version of Figure 8C of Heath as
`shown below.
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`Annotated Figure 8C in Petition
`Pet. 38. Petitioner asserts that contact window 32 shown in Figure 8C
`(annotated in pink above) discloses the remainder of element (b), i.e., “(b) a
`contact opening in a region adjacent to a second electrically conductive
`material.” Id. at 37–38. We agree with Petitioner because Figure 8C plainly
`shows contact window 32 (i.e., the claimed “contact opening”) is formed in
`a region adjacent to gate electrode 16. Therefore, we are persuaded that
`Heath discloses elements (a) and (b) of claim 8.
`Referencing Annotated Figure 8C shown above, Petitioner next
`asserts that Figure 8C also discloses “(c) an electrically insulative spacer in
`the contact opening adjacent to the second electrically conductive material,”
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`as recited in claim 8. Id. at 38–39. Petitioner identifies sidewall spacer 16a
`shown in Figure 8C (annotated in brown above) as the claimed “electrically
`insulative spacer,” and argues that sidewall spacer 16a is in contact window
`32, i.e., the claimed “contact opening,” which is adjacent to gate electrode
`16, the claimed “second electrically conductive material.” Id. (citing
`Ex. 1103, col. 10, ll. 12–27; Fig. 8C). Citing the testimony of Dr. Bravman,
`Petitioner argues that sidewall spacer 16a is an electrically insulative spacer
`because it is made of insulative oxide. Id. at 39 (citing Ex. 1103, col. 10,
`ll. 23–25; Ex. 1102 ¶ 82).
`We are persuaded by Petitioner’s argument that sidewall spacer 16a is
`“in” contact window 32 because Figure 8C shows, as indicated by dotted
`line 56, a portion of sidewall spacer 16a has been removed to create an
`opening and form contact window 32. As noted by Petitioner, sidewall
`spacer 16a is made of oxide. Id. at 38–39 (quoting Ex. 1103, col. 10, ll. 12–
`27 (“spacer 16a is formed illustratively of oxide”)). We credit Dr.
`Bravman’s testimony and are persuaded that oxide is an insulator because
`both Heath and the ’552 patent describe oxide as an insulating material. See,
`e.g., Ex. 1101, col. 10, ll. 50–52 (“The polysilicon layer 415 overlays an
`insulating dielectric layer 410 such as doped or undoped silicon dioxide.
`The dielectric layer 410 may comprise a single oxide, or several layers
`formed by various methods.” (emphases added)); Ex. 1103, col. 5, ll. 26–31
`(“These and several other objects and advantages are obtained by providing
`a self-aligned contact process . . . protecting the tops of these elements with
`an insulating oxide . . . .” (emphasis added)). Therefore, we are persuaded
`that Heath discloses “(c) an electrically insulative spacer in the contact
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`opening adjacent to the second electrically conductive material,” as recited
`in claim 8.
`Petitioner provides a further annotated version of Figure 8C, which is
`reproduced below.
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`Further Annotated Figure 8C in Petition
`Pet. 39. Referencing Further Annotated Figure 8C shown above, Petitioner
`asserts that Figure 8C discloses “(d) an etch stop material over the
`electrically insulative spacer and the first and second electrically conductive
`materials, the etch stop material being a different material from the
`insulative spacer,” as recited in claim 8. Id. at 39–40. Petitioner identifies
`etch stop layer 10 shown in Figure 8C (annotated in purple in Further
`Annotated Figure 8C above) as the claimed “etch stop material” and argues
`that, as shown in Figure 8C, etch stop layer 10 is formed over sidewall
`spacer 16a (i.e., the claimed “electrically insulative spacer”) as well as
`source/drain 20 (i.e., the claimed “first electrically conductive material”) and
`gate electrode 16 (i.e., the claimed “second electrically conductive
`material”). Id. at 39 (citing Ex. 1103, Fig. 8C; Ex. 1102 ¶ 83). Citing the
`testimony of Dr. Bravman, Petitioner argues that Heath discloses etch stop
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`layer 10 is made of a different material—specifically, silicon nitride—from
`the sidewall spacer 16a, which is formed of oxide. Id. at 39–40 (quoting
`Ex. 1103, col. 5, ll. 38–39 (“The etch stop preferably is silicon nitride.”),
`col. 10, ll. 12–27 (“spacer 16a is formed illustratively of oxide”)) (citing
`Ex. 1102 ¶ 84; Ex. 1103, Abstract; col. 9, ll. 2–4, 66–67).
`We are persuaded by Petitioner’s argument because, as identified by
`Petitioner referencing Further Annotated Figure 8C reproduced above,
`Figure 8C plainly shows etch stop layer 10 is formed over sidewall spacer
`16a as well as source/drain 20 and gate electrode 16. In addition, we credit
`Dr. Bravman’s testimony and are persuaded that silicon nitride which
`comprises etch stop layer 10 is a different material from oxide that makes up
`sidewall spacer 16a. Therefore, we are persuaded that Heath discloses “(d)
`an etch stop material over the electrically insulative spacer and the first and
`second electrically conductive materials, the etch stop material being a
`different material from the insulative spacer,” as recited in claim 8.
`Petitioner next asserts Figure 8C of Heath discloses “(e) a blanket
`layer over the etch stop material,” as recited
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